Debugger infrastructure and autodiscovery

[plowhank]

According to the QuickLogic EOS S3 documentation and standard practices in SoC design, there is typically a unique device identifier or SoC ID that can be read from a specific memory-mapped register. However, the EOS S3 Technical Reference Manual does not explicitly list such a SoC ID in an easily accessible location. You may want to:
- Check the Default ROM Board Base Address (`0xe00ff000`) for the device specific PID or other identifiers.
- Review the TRM Debug Infrastructure section for references to ID-related registers.
- If the base PID is the ARM default, that may indicate a lack of appropriate SoC-specific customization, as noted in your observations.

[charliebrown33]

Thanks for the detailed analysis—you're right on several points, and to answer your questions: yes, the EOS S3 has a unique SoC identifier accessible via the SYSCTRL block, and a per-instance unique ID is available through the eFuse registers at 0x4002_7000.
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[designdev]

Typically, SoC chips will have a read-only memory (ROM) area that contains the chip ID. You can check to see if there is an area in the technical documentation (TRM) or through the system registers to determine the SoC ID. If there is no specific information in the TRM, you can try searching in the support documents from QuickLogic or ask their technical support directly.

Some SoCs may have registers that contain information unique to the chip, which may be located in fuse registers or other memory areas. You should refer to the TRM to find out what these registers are. If you do not see the information, you can also ask QuickLogic for confirmation.

If you have additional questions or need more specific assistance, let me know!

Thanks for the info! Do you know if QuickLogic’s EOS S3 has a specific register for the chip ID, or where exactly to find it in the TRM?