I'm working on a project using a QuickLogic FPGA and trying to minimize power consumption. I've already implemented clock gating and voltage scaling where possible. I'm particularly interested in techniques for optimizing the placement and routing to reduce dynamic power.
Does anyone have experience with specific strategies or tools that are particularly effective for power optimization on QuickLogic FPGAs? Are there any specific power estimation tools that are recommended for these devices? Any insights into minimizing leakage current would also be greatly appreciated. I'm using the QuickLogic IDE and would welcome suggestions for settings or configurations that can help with power reduction..