8-bit ECUs for FIR filters

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Joined: Mon May 18, 2020 1:20 am

Is it possible to use 8-bit ECUs modules for multiply-accumulate with 32-bit input data (for 2-channel audio FIR filter - oversampling)?
Posts: 16
Joined: Fri May 15, 2020 8:27 am

QuickLogic was the first FPGA company to add DSP into the FPGA with the EclipsePlus family. Unfortunately, these DSP’s are only 8-bits and they need to use FPGA routing to cascade together. I don’t believe that it would be very efficient to implement 32x32.

Another alternative is the EOS S3, which has ~900 Logic elements and two dedicated 32x32 Multipliers connected to the FPGA.
Page 62 and 63 of the datasheet at https://www.quicklogic.com/wp-content/u ... t-2020.pdf

Multiplier selection
Built-in signed multipliers are also available in the on-chip programmable logic. The multiplier relieves the use of logic to implement such functions. There are two instances embedded in the on-chip programmable logic. The multiplier can be configured as one 32x32 bit multiplier or two 16x16 bit multipliers. A block diagram of the multiplier is shown on page 63.

As this device also has Cortex M4-F and dual PDM or I2S MIC interface it might be a better choice.
The PDM / I2S is ideally suited for low power voice applications.
Is there a reason for looking at PolarPro or EclipsePlus?
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