EOS S3 Interrupt Numbers

btashton
Posts: 14
Joined: Thu Jul 02, 2020 6:34 am

I have searched through the datasheet and the reference manual and I see lots of documentation on the NVIC and the interrupt configuration for the peripherals, but no listing of the interrupt numbers for them. I see them defined in the HAL on antmicro, but I do not see where these came from. Additionally there is a inrt_ctrl peripheral that is undocumented but seems to gate the peripheral interrupts to the M4 or AP and it is critical to use interrupts with these device.
gmartin
Posts: 17
Joined: Thu May 14, 2020 2:50 am

Here is a snippet of code from the HAL that specified the Interrupt numbers

Code: Select all

typedef enum
{
/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
/******  Specific Interrupt Numbers **********************************************************************/
  SwInt2_IRQn                    = 0,
  SwInt1_IRQn                            = 1,
  Reserved1_IRQn                     = 2,
  Ffe0Msg_IRQn                = 3,
  FbMsg_IRQn                        = 4,
  Gpio_IRQn                   = 5,
  SramSleep_IRQn              = 6,
  Uart_IRQn                   = 7,
  Timer_IRQn                  = 8,
  CpuWdtInt_IRQn              = 9,
  CpuWdtRst_IRQn              = 10,
  BusTimeout_IRQn             = 11,
  Fpu_IRQn                    = 12,
  Pkfb_IRQn                   = 13,
  Reserved_I2s_IRQn           = 14,
  Reserved_Audio_IRQn         = 15,
  SpiMs_IRQn                  = 16,
  CfgDma_IRQn                 = 17,
  PmuTimer_IRQn               = 18,
  AdcDone_IRQn                = 19,
  RtcAlarm_IRQn               = 20,
  ResetInt_IRQn               = 21,
  Ffe0_IRQn                   = 22,
  FfeWdt_IRQn                 = 23,
  ApBoot_IRQn                 = 24,
  Ldo30_pg_IRQn               = 25,
  Ldo50_pg_IRQn               = 26,
  Sram_to_IRQn                = 27,
  Lpsd_IRQn                                                                   = 28,
  Dmic_IRQn                                                                  = 29,
  Reserved2_IRQn                                          = 30,
  Sdma_Done1_IRQn                                     = 31,
  Sdma_Done2_IRQn                                     = 32,
  Sdma_Done3_IRQn                                     = 33,
  Sdma_Done4_IRQn                                     = 34,
  Sdma_Done5_IRQn                                     = 35,
  Sdma_Done6_IRQn                                     = 36,
  Sdma_Done7_IRQn                                     = 37,
  Sdma_Done8_IRQn                                     = 38,
  Sdma_Done9_IRQn                                     = 39,
  Sdma_Done10_IRQn                    = 40,
  Sdma_Done11_IRQn                    = 41,
  Ap_Pdm_Clock_On_IRQn                          = 42,
  Ap_Pdm_Clock_Off_IRQn       = 43,
  Dmac0_Block_Done_IRQn          = 44,
  Dmac0_Buffer_Done_IRQn      = 45,
  Dmac1_Block_Done_IRQn       = 46,
  Dmac1_Buffer_Done_IRQn      = 47,
  Sdma_Done0_IRQn                                     = 48,
  Sdma_Err_IRQn                                 = 49,
  I2SSlv_M4_IRQn                                = 50,
  Lpsd_Voice_Off_IRQn                  = 51,
  Dmic_Voice_Off_IRQn                 = 52

} IRQn_Type;
btashton
Posts: 14
Joined: Thu Jul 02, 2020 6:34 am

Thanks for posted that. I did see that code in the SDK, but I was wondering if it was in documentation anywhere. There is another part of this which is the the INTR_CTRL (0x40004800) this seems to be the top level interrupt controller that routes interrupts between the AP and the M4 from looking at the SDK, but once again I had to go digging into the the HAL for the registers. One bit that is especially not clear is how to clear interrupts with this. With the M4 normally the NVIC will clear the handled interrupts, but with this it appears from implementing the UART driver that I need to clear the detect bit in the INTR_CTRL for the UART. Your SDK only does this when setting it up, but I would keep getting the interrupt called even when UART_MIS register would return 0, clearing the interrupt det bit in this top level controller provided the expected behaviour. Is there an additional datasheet that goes into this, or is this only in the HAL?
gmartin
Posts: 17
Joined: Thu May 14, 2020 2:50 am

Looking to get the information you requested. We will be updating our TRM as appropriate, but will reply separately with the information you requested.
gmartin
Posts: 17
Joined: Thu May 14, 2020 2:50 am

A better description of the Interrupt structure is available at
https://www.quicklogic.com/products/soc ... ntroller/
This information will be incorporated into the Technical Reference Manual.
btashton
Posts: 14
Joined: Thu Jul 02, 2020 6:34 am

Really appreciate it, this is the information I was looking for.
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Thanks..........
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