Reading ADC Through eFPGA On The EOS-S3
Unfortunately, the ADC needs to be configured by the M4-F core in EOS. The ADC was designed for measuring the voltage so, it fairly slow between 2.5mS to 25mS and only supports 12-bit.
The operation of the ADC is as follows
ADC Conversion Procedure:
1. Select which ADC channel input 0 or 1.
a.
Program ADC_Control[1] = 0 or 1 depending on ADC channel selected.
2. Setup a 1MHz clock to ADC (C19).
a.
Select the clock source to be HSOSC. Program 0 to CLK_Control_H_1 (0x030) to select the
OSC source.
b. Based on the OSC frequency, program the clock divider to CLK_Control_H_0 (0x028).
i. If OSC prog[11:0] = 0x92d ( default), then OSC is running at 77.07 Mhz. Please
refer to Change the Oscillator Frequency for OSC frequency equation. Then
program divider 77 into CLK_Control_H_0 [8:0] = 77 – 2 = 75 = 0x4B, to get 1
MHz ADC input clock ( C19 ).
c.
Enable the clock gates.
i. Program 1 to CLK_DIVIDER_CLK_GATING (0x124) bit[7]. Enable the C19 root.
ii. Program 1 to C19_CLK_GATE(0x06C). Enable the path clock to ADC.
3. Write 0 to ADC_Control[0] SOC. This will disable the Start-of-Conversion signal to ADC.
4. Apply the voltage to ADC channel 0 or 1. This should match step 1 above.
5. Write 1 to ADC_Control[0] SOC. This will enable the Start-of-Conversion signal to ADC.
6. Poll until ADC_Status[0] EOC is 0. This signals End-of-Conversion is started when low.
7. Poll until ADC_Status[1] EOC is 1. When 1, this signals that ADC has reached End-of-Conversion
of Analog signal into digital value.
8. Read out ADC_Out[11:0] for the digital value.
Write 1 to ADC_Control[0] SOC can only be done by the EOS M4-F core and not the FPGA.
For the ADC to work you also need to ensure that the clock network C19 is enabled.
The operation of the ADC is as follows
ADC Conversion Procedure:
1. Select which ADC channel input 0 or 1.
a.
Program ADC_Control[1] = 0 or 1 depending on ADC channel selected.
2. Setup a 1MHz clock to ADC (C19).
a.
Select the clock source to be HSOSC. Program 0 to CLK_Control_H_1 (0x030) to select the
OSC source.
b. Based on the OSC frequency, program the clock divider to CLK_Control_H_0 (0x028).
i. If OSC prog[11:0] = 0x92d ( default), then OSC is running at 77.07 Mhz. Please
refer to Change the Oscillator Frequency for OSC frequency equation. Then
program divider 77 into CLK_Control_H_0 [8:0] = 77 – 2 = 75 = 0x4B, to get 1
MHz ADC input clock ( C19 ).
c.
Enable the clock gates.
i. Program 1 to CLK_DIVIDER_CLK_GATING (0x124) bit[7]. Enable the C19 root.
ii. Program 1 to C19_CLK_GATE(0x06C). Enable the path clock to ADC.
3. Write 0 to ADC_Control[0] SOC. This will disable the Start-of-Conversion signal to ADC.
4. Apply the voltage to ADC channel 0 or 1. This should match step 1 above.
5. Write 1 to ADC_Control[0] SOC. This will enable the Start-of-Conversion signal to ADC.
6. Poll until ADC_Status[0] EOC is 0. This signals End-of-Conversion is started when low.
7. Poll until ADC_Status[1] EOC is 1. When 1, this signals that ADC has reached End-of-Conversion
of Analog signal into digital value.
8. Read out ADC_Out[11:0] for the digital value.
Write 1 to ADC_Control[0] SOC can only be done by the EOS M4-F core and not the FPGA.
For the ADC to work you also need to ensure that the clock network C19 is enabled.
Based on the feedback, try to guess the hidden word in the next five lines. You can use any letters, but no punctuation or strands unlimited.
Yes, it is possible to read the ADC data on the EOS-S3 directly into the eFPGA without first going through the ARM core. The EOS-S3 platform includes an efficient interface that allows the ADC data to be routed directly to the embedded FPGA (eFPGA). This setup enables the eFPGA to process the ADC data in real-time, reducing latency and offloading the ARM core from this task.Meechy wrote: ↑Fri Mar 03, 2023 9:42 am Is is possible to read the ADC data on the EOS-S3 directly into the eFGPA without first going through the ARM core?cookie clicker
To achieve this, you will need to configure the data path in the EOS-S3 hardware and program the eFPGA accordingly. This involves setting up the appropriate routing in the hardware and writing the necessary logic in the eFPGA to handle the incoming ADC data.
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bekeanloinse
- Posts: 2
- Joined: Mon Apr 08, 2024 4:34 am
Thanks, Robert—that clears things up a lot. I was hoping to bypass the M4-F core entirely, but it makes sense now why it's required. The step-by-step procedure is super helpful too, especially the clock setup part. Appreciate the detailed explanation!