Is it possible to reach 72Mhz clocked design in eFPGA ?

[Martoni]

I saw in datasheet that FPGA clock domain can be configured up to 72Mhz. But If I synthesize the helloworldhw example I get a max frequency of 27.8Mhz.

In route.log :

Final critical path delay (least slack): 35.8776 ns, Fmax: 27.8725 MHz

Is it possible to increase this performances ?

Thanks

[Robert]

Unfortunately, The EOS S3 FPGA is designed for low power and is not able to achieve 72MHz performance.

This is why the FPGA clocks are separated from the main Cortex clock M4-F

Realistically the performance is limited to around the frequency you are seeing. We have done some highly tuned simple shift registers type interfaces running slightly higher frequency.

The wishbone interface from the eFPGA to the internal SoC AMBA bus is also limited in performance.

What frequency do you need to achieve?

[Martoni]

Unfortunately, The EOS S3 FPGA is designed for low power and is not able to achieve 72MHz performance.
This is why the FPGA clocks are separated from the main Cortex clock M4-F
Realistically the performance is limited to around the frequency you are seeing. We have done some highly tuned simple shift registers type interfaces running slightly higher frequency.
The wishbone interface from the eFPGA to the internal SoC AMBA bus is also limited in performance.

Ok,

What frequency do you need to achieve?

I had no particular frequency to reach. It was mainly to find out the limits of the eFPGA.
And I have my answer ~27Mhz
Thanks

[Robert]

We have implemented the simple USB interface for TinyFPGA where the IO run at 48MHz but this involved a hand placing the Flip-Flops etc.

So, 30MHz is a safe number.

Thanks
Robert

[lisawindy907]

i want to know any update about this issue? io games

[jonesphedra]

I saw in datasheet that FPGA clock domain can be configured up to 72Mhz. But If I synthesize the helloworldhw example I get a max frequency of 27.8Mhz.

In route.log :

Final critical path delay (least slack): 35.8776 ns, Fmax: 27.8725 MHz

Is it possible to increase this performances ?
wordle
Thanks

Yes, it's possible to achieve higher clock frequencies in eFPGA designs, including reaching 72 MHz.

Strategies to Increase Performance:

1. Logic Optimization: Carefully review your design for logic optimizations. Simplify expressions, use efficient coding styles, and leverage FPGA-specific optimizations like pipelining and resource sharing.

2. Floorplanning: If your eFPGA tool supports it, use floorplanning to strategically place critical logic blocks closer together. This can minimize routing delays.

3. Timing Constraints: Apply appropriate timing constraints during synthesis and P&R. This guides the tools to prioritize timing closure for critical paths.

4. Explore Tool Settings: Experiment with different synthesis and P&R tool settings. Sometimes, adjusting effort levels, timing-driven optimizations, or placement algorithms can yield better results.

[shinecatcher]

Yes, it is possible to reach a 72MHz clocked design in an embedded FPGA (eFPGA), but achieving this depends on various factors including the specific eFPGA architecture, the design implementation, and the optimization techniques used.