Looking for documentation about eFPGA macrocells (EOS-S3)

[Martoni]

Hello,

When I launch synthesis with QORC commands I get log files that give occupancy statistics in file «/opt/qorc-sdk/qf_apps/qf_helloworldhw/fpga/rtl/build/helloworldfpga_synth.log» (for helloworld app) :

Code: Select all

13. Printing statistics.

=== helloworldfpga ===

   Number of wires:               1055
   Number of wire bits:           1055
   Number of public wires:        1055
   Number of public wire bits:    1055
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                119
     ASSP                            1
     BIDIR_CELL                      3
     C_FRAG                         13
     F_FRAG                          1
     Q_FRAG                         44
     T_FRAG                         57

route.log give more cells :

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Pb types usage...
  PB-SYN_GND        : 1
   GND              : 1
  PB-BIDIR          : 3
   BIDIR            : 3
    OUTPUT          : 3
     bidir          : 3
     outpad         : 3
  PB-ASSP           : 1
   ASSP             : 1
  PB-LOGIC          : 56
   LOGIC            : 56
    FRAGS           : 56
     c_frag_modes   : 56
      SINGLE        : 13
       c_frag       : 13
      SPLIT         : 43
       b_frag       : 43
       t_frag       : 14
     f_frag         : 1
     q_frag_modes   : 44
      INT           : 43
       q_frag       : 43
      EXT           : 1
       q_frag       : 1
  PB-SYN_VCC        : 1
   VCC              : 1

...

Device Utilization: 0.05 (target 1.00)
	Physical Tile TL-LOGIC:
	Block Utilization: 0.06 Logical Block: PB-LOGIC
	Physical Tile TL-RAM:
	Block Utilization: 0.00 Logical Block: PB-RAM
	Physical Tile TL-MULT:
	Block Utilization: 0.00 Logical Block: PB-MULT
	Physical Tile TL-BIDIR:
	Block Utilization: 0.09 Logical Block: PB-BIDIR
	Physical Tile TL-CLOCK:
	Block Utilization: 0.00 Logical Block: PB-CLOCK
	Physical Tile TL-SDIOMUX:
	Block Utilization: 0.00 Logical Block: PB-SDIOMUX
	Physical Tile TL-GMUX:
	Block Utilization: 0.00 Logical Block: PB-GMUX
	Physical Tile TL-ASSP:
	Block Utilization: 1.00 Logical Block: PB-ASSP
	Physical Tile TL-SYN_VCC:
	Block Utilization: 1.00 Logical Block: PB-SYN_VCC
	Physical Tile TL-SYN_GND:
	Block Utilization: 1.00 Logical Block: PB-SYN_GND

Where can I found documentation about this cells ?

Thanks

[Martoni]

I can't find eFPGA mapping of macrocells in this datasheet or this.

[Robert]

The reference manual has a section of the FPGA. If you want to understand how to interface the FPGA I would suggest the following additional resources

https://github.com/coolbreeze413/qorc-onion-apps

This has a range of basic examples of how to interface the EOS device with your FPGA design.

A video tutorial is also available at https://www.quicklogic.com/products/soc ... ontroller/
Then select the SymbiFlow with QuickFeather – A simple FPGA Programming Example video

Additional documentation is also available at https://quicklogic-quicklogic-fpga-tool ... ecoun.html

I will update with the naming of the Logic cell fragmentation.

[Robert]

The FPGA Logic Cell in EOS S3 can be fragmented into four pieces

[img][

PP3 .png (23.93 KiB) Viewed 358717 times

/img]

The frag F is also referred to as b.

[Boiaten]

The architecture of the macrocells and how they interact with the rest of the device
Timing constraints and optimization techniques for these macrocells
Best practices for configuring and programming the eFPGA using the available tools
If anyone has any experience with the EOS-S3 eFPGA and could provide some insights or recommendations, I would be very grateful.
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