How to stop QuickWork P & R from split buses into individual signals in post-layout simulation

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Robert
Posts: 8
Joined: Fri May 15, 2020 8:27 am

If you find that the top-level module in the back-annotation netlist (<design_name>.vq file) bus signals have been split into individual signals then please use the following fix to resolve.

If you take a basic 8-bit counter design through Yosys and then QuickWorks P & R the .vq post-layout simulation netlist file, top-level module count bus will be split into individual signals as you can see.

module example(\count[6] , \count[7] , \count[0] , \count[1] , \count[4] ,
\count[5] , \count[2] , \count[3] , reset, enable, clk);
supply0 GND;
supply1 VCC;
input reset,enable,clk;
output \count[6] ,\count[7] ,\count[0] ,\count[1] ,\count[4] ,\count[5] ,
\count[2] ,\count[3] ;


To maintain the count signals as a bus count[7:0] you need to add a file with just the top-level module, in the above example you need to include another file called <design_name>.vh that should be in the same directory as the <design_name>.edif file.

------------------------------------------------------------------------------------------------------------------------------------
// START OF FILE
//
// Copyright (c) 2022 QuickLogic Corporation. All Rights Reserved.
//
// Description :
// Example of a simple 8 bit up counter in Verilog HDL
//
// Version 1.0 : Initial Creation
//
module example (clk, reset, enable, count);
input clk, reset, enable;
output [7:0] count;


//END OF FILE
------------------------------------------------------------------------------------------------------------------------------------


You then need to reload the <design_name>.edif into QuickWorks and re-run all the tools.

The <design_name>.vq will then change to


module example (clk, reset, enable, count);
input clk, reset, enable;
output [7:0] count;
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