Quicklogic Forums

Hello everyone,
I am learning about how to utilize QuickLogic's core IP for AI/ML applications running on an FPGA. I see some documents discussing eFPGA and supporting tools, but I am unsure how people have implemented it in practice to optimize performance and reduce latency.
Pokerogue
Has anyone done AI/ML projects on an FPGA with QuickLogic and can share their experiences, challenges, and optimization tips?

Thank you very much!

Have you tried using the QuickAI or EOS S3 platform for your experiments yet? I’m curious how the performance compared to traditional FPGA setups.

Run INT8/INT4 instead of float32 to save LUTs/DSPs/BRAM and increase throughput. This is best practice on most FPGAs/MCU-MLs. Have you tried it yet?

The biggest challenges tend to be memory bandwidth and tool-flow iteration, but starting with a small kernel and scaling up works well.