Experience using QuickLogic IP to optimize AI/ML performance on FPGA?

[lyly19]

Hello everyone,
I am learning about how to utilize QuickLogic's core IP for AI/ML applications running on an FPGA. I see some documents discussing eFPGA and supporting tools, but I am unsure how people have implemented it in practice to optimize performance and reduce latency.
Pokerogue
Has anyone done AI/ML projects on an FPGA with QuickLogic and can share their experiences, challenges, and optimization tips?

Thank you very much!

[speedstars]

Have you tried using the QuickAI or EOS S3 platform for your experiments yet? I’m curious how the performance compared to traditional FPGA setups.

[lasagnevolcanic]

Run INT8/INT4 instead of float32 to save LUTs/DSPs/BRAM and increase throughput. This is best practice on most FPGAs/MCU-MLs. Have you tried it yet?

[wstagnat]

The biggest challenges tend to be memory bandwidth and tool-flow iteration, but starting with a small kernel and scaling up works well.

[Owenburrows]

My brain cells felt like they were in a gladiatorial arena. One project, we wrestled with a neural network model, struggling to port it efficiently. It was a true test of my Slice Master skills and patience to make those circuits hum.

[CharlesVikulte]

Hey everyone, I'm diving into AI/ML on QuickLogic FPGAs and exploring eFPGA capabilities. The documentation is helpful, but real-world examples are scarce. Has anyone tackled similar AI/ML projects using QuickLogic? I'm particularly interested in your experiences, hurdles faced, and any optimization secrets you've discovered. Pokerogue is a fun game.