QuickLogic (CHP) format to Link Object Format (LOF)
Using QuickLogic SpDE 9.1 Release Build2 Eval to open .CHP file format and save as .LOF file format after 3rd party programming adapter broke. 002 worked successfully, but not 001. When saving as .LOF a log file is generated. As seen in image comparing the log files, 001 appears to stop during .LOF creation, although a file is still generated. When programmed into the device, the device does not work correctly.
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Hi Ngueron, I am also corresponding with one of your colleagues on this issue, as this relates to QuickLogic mature antifuse FPGA devices, please contact me directly for support on this issue dawson@quicklogic.com.
We need to look at the report file for the original .chp to understand which version of the tools were used for the design.
Thanks
Robert
We need to look at the report file for the original .chp to understand which version of the tools were used for the design.
Thanks
Robert
The mature anti-fuse FPGA use QuickWork SpDE to generate the <design_name>.chp (design database), from the <design_name>.chp file a programming file is generated <design_name>.lof.
The .chp references the database from version of QuickWorks that it was generated. It is important to ensure that QuickWork 9.7.4 is used to generate the .lof file for pASIC3.
The steps are as follows
1.. Open QuickLogic SpDE 9.7.4 tool.
2. Click “File”. Click “Open…”. Locate the target CHP file “<design_name>.chp” in the working directory (ensure that there are no spaces in the directory path.
3. Click “File”, Click “Save LOF”
You might need to re-run the sequencer tool before saving the .lof file.
The Sequencer generates the order which the fuses are programmed on the design and re-running this tool doesn't change the functionality or timing of the design.
Please let me know if you have any additional questions.
The .chp references the database from version of QuickWorks that it was generated. It is important to ensure that QuickWork 9.7.4 is used to generate the .lof file for pASIC3.
The steps are as follows
1.. Open QuickLogic SpDE 9.7.4 tool.
2. Click “File”. Click “Open…”. Locate the target CHP file “<design_name>.chp” in the working directory (ensure that there are no spaces in the directory path.
3. Click “File”, Click “Save LOF”
You might need to re-run the sequencer tool before saving the .lof file.
The Sequencer generates the order which the fuses are programmed on the design and re-running this tool doesn't change the functionality or timing of the design.
Please let me know if you have any additional questions.