Minimum RGB Display Requirements

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Posts: 5
Joined: Fri May 15, 2020 8:31 am
Location: London

I have a NXP processor that has an MIPI Tx output and I need to use an RGB display.

I am looking at your family of MIPI to RGB bridges Bx5BxA? and I wanted to understand if there are any restrictions with the RGB display requirements?
Posts: 7
Joined: Fri May 15, 2020 8:27 am

The RGB Display needs to support DataEnable (DE) Mode and not sync mode, as we have found that in some systems the HBP can vary by +/- 1 pixel clock. This is not an issue if the display supports Data Enable.
RGB_DE.JPG (35.76 KiB) Viewed 70 times

The pixel data can be changed on the rising or falling edge of the pixel clock and the HYSNC/VSYNC/DE signals are all configurable to be active HIGH or LOW.

If the Pixel Clock for the display is less than 12.5MHz then the SYS_CLK input needs to match the required Pixel CLK.
The minimum PCLK that we have used to-date is 8MHz

The Bx5B2A supports resolutions up to 1366 x 768 @ 24 bpp @ 60 fps
The Bx5B3A supports resolutions up to 1920 x 1200 @ 24 bpp @ 60 fps
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