PolarPro 3 FIFO IP
Posted: Wed Aug 28, 2024 3:06 pm
Hello all,
I'm a new QL user looking for details (or documentation) on the FIFO IP for the PolarPro 3 SRAM device.
The PolarPro 3 datasheet says the part contains 8x 8kbits RAM blocks, but it seems to say that the larger FIFO that can be implemented is only 2 blocks. Is that true???
My needs are as follow:
.synchronous dual-clock
.64kbits (hence 8 blocks)
.8k x 8 input @ 1MHz max
.4k x 16 output @ 120MHz max
.Endianness conversion
.FWFT
Is this possible?
Cheers,
Claude
I'm a new QL user looking for details (or documentation) on the FIFO IP for the PolarPro 3 SRAM device.
The PolarPro 3 datasheet says the part contains 8x 8kbits RAM blocks, but it seems to say that the larger FIFO that can be implemented is only 2 blocks. Is that true???
My needs are as follow:
.synchronous dual-clock
.64kbits (hence 8 blocks)
.8k x 8 input @ 1MHz max
.4k x 16 output @ 120MHz max
.Endianness conversion
.FWFT
Is this possible?
Cheers,
Claude