eFPGA access to Voice subsystem data

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charkster
Posts: 2
Joined: Sat Feb 27, 2021 12:25 am

Hi,
I was wanting to process 16bit PCM data in the eFPGA, and was wondering which FIFO and ram to use for that? In the datasheet (Figure 29) FIFO_0 and FIFO_1 appear to connect to the VOICE subsystem. FIFO_0, FIFO_1 and FIFO_2 appear to not be accessible to the eFPGA. Is there a DMA method to get the PCM data to a SRAM that the eFPGA can access with one of its FIFOs?
Also, I was thinking of using the LPSD to enable the PCM data being loaded into the FIFO for the eFPGA. Would I need the MCU to enable the DMA and then notify the eFPGA?
Thanks.
anthony-ql
Posts: 49
Joined: Thu Jun 04, 2020 1:26 am

This topic is complicated and we have plan to cover in future webinars.

In short, the audio data is stored in a circular buffer made of M4 SRAM (part of 512KB SRAM). The audio block's 16-bit PCM data can be sent to eFPGA using System DMA (SDMA). you will need to design an IP in eFPGA to accept the data and perform further data processing and SDMA back to M4 SRAM or send the processed PCM data out via eFPGA FBIO.

There is no direct access between the audio FIFO blocks and the eFPGA.

Project qorc-sdk/qf_vr_apps/qf_1micvr_app shows the flow for audio data to circular buffer in M4 SRAM. This project is a good example for SDMA usage and the location of stored audio data.

Project qorc-sdk/qf_apps/qd_helloworldhw shows the configuration for using M4 to configured eFPGA with Symbiflow bit file.
charkster
Posts: 2
Joined: Sat Feb 27, 2021 12:25 am

anthony-ql wrote: Tue Mar 02, 2021 4:38 pm Project qorc-sdk/qf_vr_apps/qf_1micvr_app shows the flow for audio data to circular buffer in M4 SRAM. This project is a good example for SDMA usage and the location of stored audio data.

Project qorc-sdk/qf_apps/qd_helloworldhw shows the configuration for using M4 to configured eFPGA with Symbiflow bit file.
Thanks for the answer. I will first get my keyword capture working in software and then I will try to increase the amplitude of the sample using the eFPGA.
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