Power on / reset circuit recommendation for EOS-S3

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matt_mets
Posts: 4
Joined: Wed Nov 11, 2020 12:37 pm

I'm developing a barebones breakout board for the EOS-S3, and have run into a snag with the device behavior at power-on. I implemented a minimal design based on the QuickFeather dev board, and my schematic is here: https://github.com/Blinkinlabs/QL-EOS-S ... _RevB1.pdf

The board fails to boot on power-on, and appears to have some spurious activity on the SPI lines:
QL_EOS_S3 power-on boot failure.png
QL_EOS_S3 power-on boot failure.png (53.43 KiB) Viewed 15415 times
If i press and release the reset button after power-on (or hold it down during reset, then release some time after power-on), the device is able to load and execute the bootloader as expected:
QL_EOS_S3 boot success after pressing reset button.png
QL_EOS_S3 boot success after pressing reset button.png (47.36 KiB) Viewed 15415 times
According to the Technical reference manual r1.01a, Figure 31-1 the power lines should be brought up in sequence (VCC, then AVDD/VCCIO, then release SYS_RSTn). However, the QuickFeather reference board doesn't seem to take this into account- it has the VDD/AVDD/VCCIO pins tied to the +3V3 line from the voltage regulator, and the SYS_RST line pulled to +3V3 with a 10k resistor.

The major differences I can see are that my board is using the BGA variant of the part, and that my board is using an LDO instead of a buck regulator.

I've tried using slow and fast rising bench supplies, increasing the value of and removing the capacitor on the reset line, but with no noticeable change in behavior.

Are there any obvious mistakes with the power circuit on my board?
anthony-ql
Posts: 49
Joined: Thu Jun 04, 2020 1:26 am

The QuickFeather is designed with the intention that the user need to press the reset button after power on (or changing boot-strap on IO19 and IO20) to start up the EOS S3. The state of IO19 and IO20 is latched at rising edge of SYS_RSTn to determine the boot state for EOS S3.

When the SYS_RSTn is held low and release after the VCCIOB has crossed the valid threshold, the EOS S3 will either wait for input from debugger, SPI Slave or execute boot-from-flash. The EOS S3 behaves as expected when the reset button is pressed or held low until VCCIOB (3.3V) has reached threshold level (~1.2V)

To control the precise timing for SYS_RSTn upon power on, there are LDO with built-in POR circuit to control the delay of SYS_RSTn released time. We have used device such as MIC68200 for EOS S3 in final product.

If the intention is to have the EOS S3 to boot-from-flash after power on, adding extra cap or increase the cap value of C5 to slow down the rise time of SYS_RSTn, may do the trick.
matt_mets
Posts: 4
Joined: Wed Nov 11, 2020 12:37 pm

Thanks! I increased the value of C5 to 4.7uF, and it's stretched the rise time on the reset pin far enough to allow it to boot:
QL_EOS_S3 boot success with 4.7uF cap.png
QL_EOS_S3 boot success with 4.7uF cap.png (50.67 KiB) Viewed 15394 times
That should be good enough for a dev board. Out of curiosity, is there a more 'production ready' reference design available for the QL-EOS-S3?
anthony-ql
Posts: 49
Joined: Thu Jun 04, 2020 1:26 am

We do have other HW platforms that is not available for general public. My recommendation for production product, you can use LDO with POR built-in or using an external POR circuit (similar to NCP803SN parts).
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