In route.log :
Is it possible to increase this performances ?Final critical path delay (least slack): 35.8776 ns, Fmax: 27.8725 MHz
Thanks
Is it possible to increase this performances ?Final critical path delay (least slack): 35.8776 ns, Fmax: 27.8725 MHz
Ok,Unfortunately, The EOS S3 FPGA is designed for low power and is not able to achieve 72MHz performance.
This is why the FPGA clocks are separated from the main Cortex clock M4-F
Realistically the performance is limited to around the frequency you are seeing. We have done some highly tuned simple shift registers type interfaces running slightly higher frequency.
The wishbone interface from the eFPGA to the internal SoC AMBA bus is also limited in performance.
I had no particular frequency to reach. It was mainly to find out the limits of the eFPGA.What frequency do you need to achieve?