Dear QuickLogic,
I have a question regarding the reconfiguration of the eFPGA of the EOS-S3.
Some background for my use case:
I am a student working on a university semester project. The end goal is to have a reconfigurable hardware system for accelerating neural networks (i.e. turning a NN description into hardware), specifically for NNs which are too large to fit into a single FPGA design. Because the design is too large, the NN would be split into smaller sub designs and run sequentially on the FPGA by reconfiguring the FPGA at runtime through the M4. Partial reconfiguration of the fabric, which the EOS-S3 seems to support, would also be very useful as it could have significant impact on reconfiguration speed.
The hardware used for this project is the Sparkfun Thing+.
My question:
How does one reconfigure the FPGA without a system reset?
There is some code given in the file "Libraries/FPGA/src/fpga_loader.c" in the qorc-sdk github repo. The code works after a system reset, and implements the flow chart found in the "Libraries/FPGA" directory in the same repo.
However, there are no resources at all regarding the configuration of the FPGA fabric after it has already been configured. The readme file, also located in the folder ""Libraries/FPGA", even points this out. The direct quote from the readme:
" TODO: Add more detailed FPGA Load process, adding in the necessary steps, when EOS S3 is not starting at RESET.
For example, when we have to load a different FPGA bitstream, without resetting the EOS S3."
The datasheet and TRM are also of no help as they either don't mention the reconfiguration process or just contain a note along the likes of "[topic to be added in future]" or "discussion to be added".
I would appreciate either some instructions and explanations of the whole reconfiguration process or a bare metal c code sample which "just works". Technical documentation of the CFG_CTL module would also be gladly welcome.
Many thanks in advance!