FPGA routing structure and other pnr questions
Posted: Tue Jun 16, 2020 1:47 pm
Is there any documents / diagram that detail how the routing structure works and what kind of "faster path" exist ?
Looking at some timing reports and some parts of the toolchain I had also some questions :
* The LUT4 from yosys get broken out in LUT3 + a F_FRAG. But will VTR stil map them properly to not use the F_MUX but the TBS one ?
* I saw a comment that the dedicated path from TBS mux to the FF isn't use and it always goes from CZ to switchbox to QDI, is that still the case ?
* Is there any dedicated / faster routing to go from Fmux to/from other signals in the same LC ?
You also mentionned you have a proprietary toolchain for that fpga, do you have any comparison or rough idea how the current yosys+vtr stack compares performance/area wise to your dedicated tool ? Just to get an idea of how much potential gain there could be by improving the synthesis and pnr part of the current OSS stack.
Cheers,
Sylvain
Looking at some timing reports and some parts of the toolchain I had also some questions :
* The LUT4 from yosys get broken out in LUT3 + a F_FRAG. But will VTR stil map them properly to not use the F_MUX but the TBS one ?
* I saw a comment that the dedicated path from TBS mux to the FF isn't use and it always goes from CZ to switchbox to QDI, is that still the case ?
* Is there any dedicated / faster routing to go from Fmux to/from other signals in the same LC ?
You also mentionned you have a proprietary toolchain for that fpga, do you have any comparison or rough idea how the current yosys+vtr stack compares performance/area wise to your dedicated tool ? Just to get an idea of how much potential gain there could be by improving the synthesis and pnr part of the current OSS stack.
Cheers,
Sylvain