Quicklogic Forums

Hi,

I tried to set up a design using the eFPGA to push data to the Packet FIFO and pop it from the M4. Nevertheless, I think that the available documentation in both the datasheet and the TRM is not enough to get to know how to drive it. Also, I didn't find any example using the eFPGA - Packet FIFO tandem. Is there any more documentation relating to this topic available/to be published?

I really appreciate any help,

Pablo

Hi,

I tried setting up eFPGA to push data to the Packet FIFO and pop it from the M4, but the datasheet and TRM lack details on driving it. Also, I couldn't find an eFPGA - Packet FIFO example. Is there additional documentation or examples available?

Thanks,
Pablo

Have any update about this issue?
moto x3m

I tried setting up eFPGA to push data to the Packet FIFO and pop it from the M4, but the datasheet and TRM lack details on driving it. Also, I couldn't find an eFPGA - Packet FIFO example. Is there additional documentation or examples available?

Also, I didn't find any example using the eFPGA - Packet FIFO tandem. Is there any more documentation relating to this topic available/to be published?

listlesspolite wrote: ↑Wed Oct 30, 2024 9:20 am Hi,

I tried setting up eFPGA to push data to the Packet FIFO and pop it from the M4, but the datasheet and TRM lack details on driving it. Also, I couldn't find an eFPGA - Packet FIFO example. Is there additional documentation or examples available?

Thanks,
Pablo

Thanks

Hey Pablo, I understand your frustration with the eFPGA-Packet FIFO setup. Documentation can be tricky! Have you tried looking for forum threads mentioning similar data transfer challenges? Sometimes, approaching the problem like a game of Block Blast, focusing on clearing one hurdle at a time, can help. Sharing your specific code snippets might attract users who have experience with this exact tandem. Good luck!