Hi,
I tried to set up a design using the eFPGA to push data to the Packet FIFO and pop it from the M4. Nevertheless, I think that the available documentation in both the datasheet and the TRM is not enough to get to know how to drive it. Also, I didn't find any example using the eFPGA - Packet FIFO tandem. Is there any more documentation relating to this topic available/to be published?
I really appreciate any help,
Pablo