Hi,
Is there any examples on how to use RAM blocks in the S3 ?
Doesn't look like there is any inference support (which is fine, tbh I often prefer to instanciate them).
I see a ram8k_2x1_cell_macro in the cells_sim.v from yosys but :
* No documentation I could find.
* Is it for 2 blocks at a time ? That seems *very* inconvenient to use if you need only 1 ...
Did I miss something ?
Cheers,
Sylvain
RAM blocks in S3 programmable logic
There is documentation on the RAM / FIFO usage in the installation package (<Install_Path>/symbiflow-arch-defs/install/docs/S3B_Hardmacro_User_Guide.docx)
Regarding the design examples of using RAM and FIFO blocks, they are at:
https://github.com/QuickLogic-Corp/symb ... FIFO_Block
https://github.com/QuickLogic-Corp/symb ... SRAM_Block
Regarding the RAM and FIFO Examples, they are at:
https://github.com/QuickLogic-Corp/symb ... O_Examples
https://github.com/QuickLogic-Corp/symb ... M_Examples
Regarding the design examples of using RAM and FIFO blocks, they are at:
https://github.com/QuickLogic-Corp/symb ... FIFO_Block
https://github.com/QuickLogic-Corp/symb ... SRAM_Block
Regarding the RAM and FIFO Examples, they are at:
https://github.com/QuickLogic-Corp/symb ... O_Examples
https://github.com/QuickLogic-Corp/symb ... M_Examples
Regarding the initialization of the RAM block, HW supports 2 ways of initializing the FPGA RAMs:
1. RAM initialization during the FPGA configuration by the M4
2. RAM can be initialized by M4 through the Wishbone interface as part of the FPGA IP
RAM initialization as part of the FPGA configuration is not supported in this release. It would be supported in the next release.
Currently, we can initialize the FPGA RAM from M4 through the wishbone interface (after the FPGA configuration):
M4 -> Wishbone master (part of the ASSP) -> Wishbone slave (part of the FPGA IP) -> FPGA RAMs
1. RAM initialization during the FPGA configuration by the M4
2. RAM can be initialized by M4 through the Wishbone interface as part of the FPGA IP
RAM initialization as part of the FPGA configuration is not supported in this release. It would be supported in the next release.
Currently, we can initialize the FPGA RAM from M4 through the wishbone interface (after the FPGA configuration):
M4 -> Wishbone master (part of the ASSP) -> Wishbone slave (part of the FPGA IP) -> FPGA RAMs
For the init: Yeah (2) was my fallback. Thankfully the RAM I need initialized is actually a large ROM which mean the "Write side" can trivially be connected to the wishbone with very little logic cost. But it's good to know that (1) is supported by the hardware itself.
For the example, yeah, I saw those, but I was more looking for actually ... documentation / text that explains what does what rather than trying to reverse engineer it from a couple of example. Especially for stuff like different width of the R/W ports and how the data/address mapping works in that case, etc, etc ...
For the example, yeah, I saw those, but I was more looking for actually ... documentation / text that explains what does what rather than trying to reverse engineer it from a couple of example. Especially for stuff like different width of the R/W ports and how the data/address mapping works in that case, etc, etc ...
The RAMs and FIFOs can be created by instantiating the basic RAM block (RAM_16K_BLK) and FIFO Block (FIFO_16K_BLK) respectively.
The documentation regarding the RAM / FIFO usage is at:
https://github.com/QuickLogic-Corp/quic ... _Guide.pdf
The documentation regarding the RAM / FIFO usage is at:
https://github.com/QuickLogic-Corp/quic ... _Guide.pdf