Some questions about EOS S3 platform: packaging, LV variant, Sensor Processing Subsystem and documentation

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jon-fl
Posts: 4
Joined: Mon Mar 15, 2021 3:25 pm

Hello,

I am interested in using the EOS S3 multicore MCU in an open source battery operated hobby project (~1000 units) but have several questions:
  1. I understand from forum posts here that the QFN packaging is effectively end-of-life and that, as of last year, Quicklogic had been looking for a similarly user-friendly replacement package. Has Quicklogic made any headway in identifying one?
    .
  2. On Mouser I see several EOS S3 SKUs tagged with the part number suffix LV and the description text "low voltage," but I see no such distinction made in the ordering information in the datasheet and TRM. What is the difference between these parts? Are the LV parts binned to run at a lower voltage, and can these be sampled in QFN on a Quickfeather board for power evaluation?
    .
  3. Will the documentation and tooling for the Sensor Processing Subsystem be made available for open source projects? Even just an ISA description with encoding for the uDSP would be great for writing an open source assembler, and could be further extended later with an LLVM backend.
    .
  4. Typically FPGA parts from other manufacturers have more than just a basic datasheet and TRM. Will Quicklogic be making more information publicly available for the EOS S3, such as basic benchmark information for FPGA logic and I/O performance, and high-level user-visible details on the routing like the maximum number of unshared signals that can be used by the independent muxes in a logic block?
Thanks!

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Jon
anthony-ql
Posts: 49
Joined: Thu Jun 04, 2020 1:26 am

Will pass your request to marketing team.
jon-fl
Posts: 4
Joined: Mon Mar 15, 2021 3:25 pm

Thanks Anthony!
mwang
Posts: 16
Joined: Thu Jun 11, 2020 2:07 am

Hi Jon,

sent you a PM on this.

Regards
Mao
tome
Posts: 1
Joined: Fri Jun 03, 2022 2:43 am

Hi Mao

I have almost exactly the same questions as Jon. We prefer to use QFN for visual inspection. Could you answer those questions for me too please?


Thanks,
Tom
nimish
Posts: 4
Joined: Mon Jun 19, 2023 10:03 pm

Hi, are the answers to these public?

I would also like to know if the "TBD" stuff about FPGA configuration will be updated, including whether it's possible to reconfigure the FPGA on the fly.
Robert
Posts: 29
Joined: Fri May 15, 2020 8:27 am

Please find the answers to some of your questions.

I understand from forum posts here that the QFN packaging is effectively end-of-life and that, as of last year, Quicklogic had been looking for a similarly user-friendly replacement package. Has Quicklogic made any headway in identifying one?
Rob>> Unfortunately we haven't seen a large enough demand for this package, so a replacement for the QFN is still on hold, we have had several customers use the BGA package on a one layer PCB.
.
On Mouser I see several EOS S3 SKUs tagged with the part number suffix LV and the description text "low voltage," but I see no such distinction made in the ordering information in the datasheet and TRM. What is the difference between these parts? Are the LV parts binned to run at a lower voltage, and can these be sampled in QFN on a Quickfeather board for power evaluation?
Rob>> I would recommend using the standard devices, as there are several limitations with the LV silicon for example maximum clock speed is reduced from 80MHz to 48MHz
.
Will the documentation and tooling for the Sensor Processing Subsystem be made available for open source projects? Even just an ISA description with encoding for the uDSP would be great for writing an open source assembler, and could be further extended later with an LLVM backend.
Rob>> I will investigate and get back to you, we would need to look at how we could support openning up this IP block.
.
Typically FPGA parts from other manufacturers have more than just a basic datasheet and TRM. Will Quicklogic be making more information publicly available for the EOS S3, such as basic benchmark information for FPGA logic and I/O performance, and high-level user-visible details on the routing like the maximum number of unshared signals that can be used by the independent muxes in a logic block?
Rob>> For more details on the FPGA structure please reference the https://www.quicklogic.com/wp-content/u ... 3_2021.pdf
nimish
Posts: 4
Joined: Mon Jun 19, 2023 10:03 pm

Robert wrote: Thu Jun 22, 2023 1:41 pm Please find the answers to some of your questions.
FPGA ...

Hi Robert,

Thanks for the answers!

Re FPGA configuration, I'm referring to https://www.quicklogic.com/wp-content/u ... -Vol-1.pdf the TRM section 30.7 where there's a [to be added]

as well as https://github.com/QuickLogic-Corp/qorc ... aries/FPGA where there's a
TODO: Add more detailed FPGA Load process, adding in the necessary steps, when EOS S3 is not starting at RESET.
For example, when we have to load a different FPGA bitstream, without resetting the EOS S3.
My use case is reconfiguring the FPGA on the fly, sort of like Xilinx's DFX
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