Is it possible to reach 72Mhz clocked design in eFPGA ?

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Martoni
Posts: 16
Joined: Fri Mar 19, 2021 8:37 am

I saw in datasheet that FPGA clock domain can be configured up to 72Mhz. But If I synthesize the helloworldhw example I get a max frequency of 27.8Mhz.

In route.log :
Final critical path delay (least slack): 35.8776 ns, Fmax: 27.8725 MHz
Is it possible to increase this performances ?

Thanks
Robert
Posts: 29
Joined: Fri May 15, 2020 8:27 am

Unfortunately, The EOS S3 FPGA is designed for low power and is not able to achieve 72MHz performance.

This is why the FPGA clocks are separated from the main Cortex clock M4-F

Realistically the performance is limited to around the frequency you are seeing. We have done some highly tuned simple shift registers type interfaces running slightly higher frequency.

The wishbone interface from the eFPGA to the internal SoC AMBA bus is also limited in performance.

What frequency do you need to achieve?
Martoni
Posts: 16
Joined: Fri Mar 19, 2021 8:37 am

Unfortunately, The EOS S3 FPGA is designed for low power and is not able to achieve 72MHz performance.
This is why the FPGA clocks are separated from the main Cortex clock M4-F
Realistically the performance is limited to around the frequency you are seeing. We have done some highly tuned simple shift registers type interfaces running slightly higher frequency.
The wishbone interface from the eFPGA to the internal SoC AMBA bus is also limited in performance.
Ok,
What frequency do you need to achieve?
I had no particular frequency to reach. It was mainly to find out the limits of the eFPGA.
And I have my answer ~27Mhz :)
Thanks
Robert
Posts: 29
Joined: Fri May 15, 2020 8:27 am

We have implemented the simple USB interface for TinyFPGA where the IO run at 48MHz but this involved a hand placing the Flip-Flops etc.

So, 30MHz is a safe number.

Thanks
Robert
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