Customer Question: How do you interface the Quick Feather Dev board with other sensors ? or is that the only available input (from the external world) is the UART ? Answer>> Typically most sensors have I2C or SPI interfaces. The easiest interface to connect to one of the two I2C interfaces on the EO...

If you find that the top-level module in the back-annotation netlist (<design_name>.vq file) bus signals have been split into individual signals then please use the following fix to resolve. If you take a basic 8-bit counter design through Yosys and then QuickWorks P & R the .vq post-layout simu...

Thank you for your interest in Quicklogic. Please let me answer your technical questions and I will get Sales to contact you will availability and lead-time. You are correct QuickLogic has a family of ASSP display bridges Bx5_family.JPG The devices that you are most interested in are the Bx5B1D (MIP...

The pASIC3 family is Low Power, High-Reliability Antifuse FPGA, which means that it is One-Time Programmable and is Non-volatile, and Instant-On, so it doesn't need to be configured like an SRAM based FPGA QuickLogic Antifuse families pASIC1, pASIC2, pASIC3, QuickRAM, Eclipse 1 and 2, PolarPro 1 and...

The SPI Flash on the QuickFeather board has the following address map QuickFeather Flash is 2MB. First 1MB is fixed * for use with Bootloader, FPGA, FFE, APP images * * 0x0000’0000 0x0000’FFFF QuickFeather Boot Loader (raw flash) * 0x0001’0000 0x0001’0007 {CRC,ByteCount} USB to serial flash FPGA ima...

Currently the board is available from https://www.crowdsupply.com/quicklogic/quickfeather, with $9 shipping charge to Germany. The board will also be stocked by Future Electronics shortly https://www.futureelectronics.com/p/development-tools--development-tool-hardware/qfb-s3bdevkit-aa-1-0-quicklogic...

The mature anti-fuse FPGA use QuickWork SpDE to generate the <design_name>.chp (design database), from the <design_name>.chp file a programming file is generated <design_name>.lof. The .chp references the database from version of QuickWorks that it was generated. It is important to ensure that Quick...

The RGB Display needs to support DataEnable (DE) Mode and not sync mode, as we have found that in some systems the HBP can vary by +/- 1 pixel clock. This is not an issue if the display supports Data Enable. RGB_DE.JPG The pixel data can be changed on the rising or falling edge of the pixel clock an...

Hi Ngueron, I am also corresponding with one of your colleagues on this issue, as this relates to QuickLogic mature antifuse FPGA devices, please contact me directly for support on this issue dawson@quicklogic.com. We need to look at the report file for the original .chp to understand which version ...