Unfortunately not, I need that <= pointing the other way. The OS is streaming data into the FIFO faster than it leaves, so say I am writing 100 bytes and I fill the FIFO, I need to block the service routine until there is room again, as far as I can tell this is not possible via the supplied interru...

The platform datasheet makes reference to supporting DMA for the UART peripheral, but the Reference Manual does not contain any information on this. Additionally the HAL defines some registers for the UART around this, but that is all. One of the reasons that I would like to use DMA is the UART does...

Thanks for posted that. I did see that code in the SDK, but I was wondering if it was in documentation anywhere. There is another part of this which is the the INTR_CTRL (0x40004800) this seems to be the top level interrupt controller that routes interrupts between the AP and the M4 from looking at ...

I have searched through the datasheet and the reference manual and I see lots of documentation on the NVIC and the interrupt configuration for the peripherals, but no listing of the interrupt numbers for them. I see them defined in the HAL on antmicro, but I do not see where these came from. Additio...