The simplest approach is to use a J-Link 9‑pin Cortex‑M adapter or an equivalent option. https://www.segger.com/products/debug-probes/j-link/accessories/adapters/9-pin-cortex-m-adapter/ This also gives you the pin-out information, if you want to make your own cable. Or for For hobbyists and educatio...

We’ve developed a battery‑powered keyword‑detection solution that uses an FSM‑based state machine to dynamically adjust the clock frequency and enable or disable peripherals to achieve low‑power operation. This will only work if you are using FreeRTOS. I’ll work on providing a video and supporting d...

We have implemented the simple USB interface for TinyFPGA where the IO run at 48MHz but this involved a hand placing the Flip-Flops etc.

So, 30MHz is a safe number.

Thanks
Robert

Unfortunately, The EOS S3 FPGA is designed for low power and is not able to achieve 72MHz performance. This is why the FPGA clocks are separated from the main Cortex clock M4-F Realistically the performance is limited to around the frequency you are seeing. We have done some highly tuned simple shif...

Sorry for the delayed reply, I would need to check the date code marking to see if we still have record as this device. It would appear at first glance to have a date code of week 5 2002. The QL4009-1PF100C is a ViaLink device which is one time programmable. As this has custom marking I would sugges...

What frequency external clock are you trying to use?

I would suggest bring the clock in on a FBIO pin and then instantiating a global clock buffer. I will look at creating an example if this is still an issue.

You could try the latest release of the F4PGA group as they are maintaining Symbiflow

https://f4pga-examples.readthedocs.io/e ... ml#getting

They only support Ubuntu, Debian, Centos and Fedora so this may not fix the issue you have with Mint

The FPGA Logic Cell in EOS S3 can be fragmented into four pieces

[img][/img]

The frag F is also referred to as b.

I believe that you need to update the FPGA firmware. I know that this is the case with QuickFeather board. I will test and update some additional information.

Unfortunately, the ADC needs to be configured by the M4-F core in EOS. The ADC was designed for measuring the voltage so, it fairly slow between 2.5mS to 25mS and only supports 12-bit. The operation of the ADC is as follows ADC Conversion Procedure: 1. Select which ADC channel input 0 or 1. a. Progr...