Great topic! A few things that have made a real difference for us on EOS S3 projects: Bypassing the onboard LDOs and feeding the 1.1V core rail externally — the datasheet spec's the core at 1.1V and explicitly supports this as one of three power configurations (dual LDO, single LDO, or external supp...

The Lite version is identical in schematic and layout, except it does not have the pressure‑sensor device populated on the PCB.

I would suggest reloading the binary images for the board at https://github.com/QuickLogic-Corp/qf-initial-bins

Hi, good question — happy to summarize how this works and where its limits are. The implementation is intentionally minimal. USB 1.1 full-speed signaling is 3.3 V, which standard LVCMOS33 FPGA I/O can drive directly, so the hardware is just: D+ and D− wired to two FPGA pins (usually through ~33 Ω se...

The simplest approach is to use a J-Link 9‑pin Cortex‑M adapter or an equivalent option. https://www.segger.com/products/debug-probes/j-link/accessories/adapters/9-pin-cortex-m-adapter/ This also gives you the pin-out information, if you want to make your own cable. Or for For hobbyists and educatio...

We’ve developed a battery‑powered keyword‑detection solution that uses an FSM‑based state machine to dynamically adjust the clock frequency and enable or disable peripherals to achieve low‑power operation. This will only work if you are using FreeRTOS. I’ll work on providing a video and supporting d...

We have implemented the simple USB interface for TinyFPGA where the IO run at 48MHz but this involved a hand placing the Flip-Flops etc.

So, 30MHz is a safe number.

Thanks
Robert

Unfortunately, The EOS S3 FPGA is designed for low power and is not able to achieve 72MHz performance. This is why the FPGA clocks are separated from the main Cortex clock M4-F Realistically the performance is limited to around the frequency you are seeing. We have done some highly tuned simple shif...

Sorry for the delayed reply, I would need to check the date code marking to see if we still have record as this device. It would appear at first glance to have a date code of week 5 2002. The QL4009-1PF100C is a ViaLink device which is one time programmable. As this has custom marking I would sugges...

What frequency external clock are you trying to use?

I would suggest bring the clock in on a FBIO pin and then instantiating a global clock buffer. I will look at creating an example if this is still an issue.