Search found 17 matches

by gmartin
Tue Jan 19, 2021 10:48 pm
Forum: General Discussion
Topic: Error; "Permission denied /dev/ttySCM0" on Linux UBUNTU
Replies: 1
Views: 11

Re: Error; "Permission denied /dev/ttySCM0" on Linux UBUNTU

This was probably due to a permissions error. Assuming your on a linux host, the /dev/ttyACM0 may be a member of the dialout or plugdev groups. the simples way is identify this as the issue is to try a the command with the prefix sudo to run the command as root. If that works, then the following com...
by gmartin
Sat Sep 19, 2020 10:32 am
Forum: SymbiFlow
Topic: Symbiflow Pin constraint names
Replies: 0
Views: 264

Symbiflow Pin constraint names

Symbiflow 1.1.0 release was updated to use device package pin names for Pin placement constraints (.pcf) nstead of using internal names (e.g. FBIO_*/SFBIIO_*). Since IO Mux setting generation script relied on internal names, it didn’t generate the IO mux settings for IOs used inside FPGA correctly. ...
by gmartin
Thu Jul 16, 2020 3:15 pm
Forum: EOS-S3
Topic: I2C Master Registers
Replies: 15
Views: 1729

Re: I2C Master Registers

Looking more into your issues. Please check the FFE Power Domain is enabled. We have an app note on setting up the FFE and accessing the I2C. It will be ready in a day or so, but here is a relevant snippet that is part of a jlink script -- hope this helps in the meantime. ; setup IO0 and IO1 for SCL...
by gmartin
Wed Jul 15, 2020 2:27 pm
Forum: EOS-S3
Topic: I2C Master Registers
Replies: 15
Views: 1729

Re: I2C Master Registers

Are you still having issues with the wishbone accesses? I see you have restructured the eoss3_hal_wb.c functionality. assuming your attempting to access an I2C device, have you programmed the IO PAD and provided appropriate pullup resistors? I found an updated version of the I2C specification that c...
by gmartin
Mon Jul 13, 2020 4:43 pm
Forum: EOS-S3
Topic: I2C Master Registers
Replies: 15
Views: 1729

Re: I2C Master Registers

Attached is a partial register list. This information is being incorporated into the TRM, but here is an early dump. The I2C registers are part of the EXTRegFFE section. Ive include the PMU registers also. Let me know if you need additional information or clarification. The I2C core is from OpenCore...
by gmartin
Sun Jul 12, 2020 5:15 pm
Forum: EOS-S3
Topic: I2C Master Registers
Replies: 15
Views: 1729

Re: I2C Master Registers

I have your request and am tracking down the information.. Thanks for finding all these missing/conflicting pieces of Information.
by gmartin
Wed Jul 08, 2020 11:58 pm
Forum: General Discussion
Topic: EOS S3 Interrupt Numbers
Replies: 5
Views: 1302

Re: EOS S3 Interrupt Numbers

A better description of the Interrupt structure is available at
https://www.quicklogic.com/products/soc ... ntroller/
This information will be incorporated into the Technical Reference Manual.
by gmartin
Wed Jul 08, 2020 7:57 pm
Forum: EOS-S3
Topic: UART DMA support
Replies: 2
Views: 543

Re: UART DMA support

Unfortunately the S3 does not support SDMA to/from the UART. -- From the Platform Datasheet The blocks that can initiate transfer using SDMA are: 1. I2S slave port 2. M4F processor 3. FFE 4. On-chip programmable logic The FIFO transmit interrupt can be programmed to <= 1/8 full in the Interrupt FIFO...
by gmartin
Wed Jul 08, 2020 5:22 pm
Forum: General Discussion
Topic: EOS S3 Interrupt Numbers
Replies: 5
Views: 1302

Re: EOS S3 Interrupt Numbers

Looking to get the information you requested. We will be updating our TRM as appropriate, but will reply separately with the information you requested.
by gmartin
Wed Jul 08, 2020 1:07 pm
Forum: General Discussion
Topic: EOS S3 Interrupt Numbers
Replies: 5
Views: 1302

Re: EOS S3 Interrupt Numbers

Here is a snippet of code from the HAL that specified the Interrupt numbers typedef enum { /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 ...