Thanks for sharing this—power optimization in FPGAs is always tricky. In my last project, the biggest gains came from careful clock gating and trimming unnecessary logic/registers, rather than chasing every tool setting. Also, documenting where the idle current actually goes helped a lot. Hopefully ...

Thank you for sharing your problem, and I’m really glad you reached out to the community. I’ve had similar issues after updating toolchains—sometimes Eclipse loses the build environment settings. In my case, rolling back to the version bundled with the SDK and re-importing the project helped. Geomet...