Search found 2 matches

by bekeanloinse
Thu Aug 07, 2025 6:46 am
Forum: EOS-S3
Topic: Reading ADC Through eFPGA On The EOS-S3
Replies: 5
Views: 47024

Re: Reading ADC Through eFPGA On The EOS-S3

Thanks, Robert—that clears things up a lot. I was hoping to bypass the M4-F core entirely, but it makes sense now why it's required. The step-by-step procedure is super helpful too, especially the clock setup part. Appreciate the detailed explanation!
by bekeanloinse
Mon Apr 08, 2024 4:37 am
Forum: FPGAs
Topic: 8-bit ECUs for FIR filters
Replies: 2
Views: 40655

Re: 8-bit ECUs for FIR filters

The EOS S3 family, with its Cortex M4-F, dual PDM or I2S MIC interface, and dedicated multipliers, seems to offer advantages such as improved efficiency and suitability for low-power voice applications. The ability to configure the multipliers as one 32x32 bit multiplier or two 16x16 bit multipliers...