Search found 16 matches
- Tue Jun 16, 2020 1:47 pm
- Forum: EOS-S3
- Topic: FPGA routing structure and other pnr questions
- Replies: 2
- Views: 22166
FPGA routing structure and other pnr questions
Is there any documents / diagram that detail how the routing structure works and what kind of "faster path" exist ? Looking at some timing reports and some parts of the toolchain I had also some questions : * The LUT4 from yosys get broken out in LUT3 + a F_FRAG. But will VTR stil map them...
- Tue Jun 16, 2020 1:41 pm
- Forum: EOS-S3
- Topic: S3 device package
- Replies: 5
- Views: 20269
Re: S3 device package
I'd definitely go for QFN or BGA. BGA really isn't that much of an obstacle especially when you go for larger pitch like 0.8 or 1mm. For QFN I actually think 64 with .5 mm pitch is pretty perfect. Good compromise between the chip size and the number of IOs. It's easy to deal with/break out on cheap ...
- Fri Jun 12, 2020 9:20 am
- Forum: EOS-S3
- Topic: S3 device package
- Replies: 5
- Views: 20269
Re: S3 device package
Which is a bit of a shame because it's a very convenient package for prototyping / experimenting. 0.4mm pitch as the "largest" pitch package is not great for OSHW devices you'd want people to be able and reproduce. No way to do that in common batch prototype PCB providers. 0.8 mm pitch (po...
- Thu Jun 11, 2020 2:31 pm
- Forum: EOS-S3
- Topic: Simulation models errors
- Replies: 1
- Views: 14290
Simulation models errors
Someone might want to do a sanity check of the models because : For instance for dffpc : always @(posedge CLK or posedge CLK or posedge PRE) if (CLR) Q <= 1'b0; else if (PRE) Q <= 1'b1; else Q <= D; One of the `posedge CLK` should be `posedge CLR` obviously. Also, the dffepc is doing a preset when C...
Re: IO block
Ok, tx for the info.
- Mon Jun 08, 2020 6:22 pm
- Forum: EOS-S3
- Topic: RAM blocks in S3 programmable logic
- Replies: 6
- Views: 20312
Re: RAM blocks in S3 programmable logic
For the init: Yeah (2) was my fallback. Thankfully the RAM I need initialized is actually a large ROM which mean the "Write side" can trivially be connected to the wishbone with very little logic cost. But it's good to know that (1) is supported by the hardware itself. For the example, yea...
- Mon Jun 08, 2020 2:38 pm
- Forum: EOS-S3
- Topic: S3 FPGA clock max frequency in Datasheet
- Replies: 2
- Views: 15247
Re: S3 FPGA clock max frequency in Datasheet
I'm starting to fear it's not a mistake :( I just did a simple design with a 24 bits counter with the 3 MSBs connected to LEDs. That results in a logic with ~ 8 LUT deep longest path and I get a ~ 22-24 MHz fmax result which is disappointingly slow :/ I don't understand how you got USB to work at al...
- Sun Jun 07, 2020 4:38 pm
- Forum: SymbiFlow
- Topic: First impressions on FPGA toolchain
- Replies: 13
- Views: 41424
Re: First impressions on FPGA toolchain
There seem to be another issue with the toolchain source : The installed scripts ( from quicklogic/toolchain_wrappers ) are completely different from the one in the binary release. I have no idea where the latter are supposed to come from, I couldn't find them in any source repository ...
IO block
So `bipad` is the IO buffer control, seems obvious. But this doesn't contain the IO registers themselves (those shown in Figure 37). I thought 'gpio_cell_macro' might be that but the simulation model doesn't show any registers there either and it's missing some signals like IQZ and ... a clock input...
- Sun Jun 07, 2020 10:33 am
- Forum: EOS-S3
- Topic: RAM blocks in S3 programmable logic
- Replies: 6
- Views: 20312
Re: RAM blocks in S3 programmable logic
Also ... you can't initialize the RAM block content can you ?