Search found 9 matches
- Wed Jun 17, 2020 1:00 pm
- Forum: EOS-S3
- Topic: FPGA routing structure and other pnr questions
- Replies: 2
- Views: 22232
Re: FPGA routing structure and other pnr questions
We are in the process of creating detailed routing architecture description. Meanwhile we will forward you document with details of the S3 FPGA routing structure. Regarding the LUT4 implementation, currently Yosys/Symbiflow does not use TBS to implement LUT4. It is in our list of improvements, we wi...
- Wed Jun 17, 2020 4:07 am
- Forum: EOS-S3
- Topic: RAM blocks in S3 programmable logic
- Replies: 6
- Views: 20393
Re: RAM blocks in S3 programmable logic
RAM initialization as part of the FPGA configuration is still not supported, we are working on it.
Re: IO block
IO register is still not supported, we are working on it.
- Fri Jun 12, 2020 2:15 pm
- Forum: EOS-S3
- Topic: Simulation models errors
- Replies: 1
- Views: 14299
Re: Simulation models errors
I have raised an issue on the same. We will review the cells_sim.v file and fix all these issues ASAP.
- Tue Jun 09, 2020 4:05 pm
- Forum: EOS-S3
- Topic: S3 FPGA clock max frequency in Datasheet
- Replies: 2
- Views: 15270
Re: S3 FPGA clock max frequency in Datasheet
Yosys is removing the gclkbuff instantiated in the design. I have filed an issue with respect to this. With regards to the tinyfpga usb bootloader, the original design could not meet the timing requirement of 48 MHz even with the proprietary tool. We modified the design, to pipeline certain paths to...
- Tue Jun 09, 2020 3:46 pm
- Forum: EOS-S3
- Topic: RAM blocks in S3 programmable logic
- Replies: 6
- Views: 20393
Re: RAM blocks in S3 programmable logic
The RAMs and FIFOs can be created by instantiating the basic RAM block (RAM_16K_BLK) and FIFO Block (FIFO_16K_BLK) respectively.
The documentation regarding the RAM / FIFO usage is at:
https://github.com/QuickLogic-Corp/quic ... _Guide.pdf
The documentation regarding the RAM / FIFO usage is at:
https://github.com/QuickLogic-Corp/quic ... _Guide.pdf
- Mon Jun 08, 2020 5:43 pm
- Forum: EOS-S3
- Topic: RAM blocks in S3 programmable logic
- Replies: 6
- Views: 20393
Re: RAM blocks in S3 programmable logic
Regarding the initialization of the RAM block, HW supports 2 ways of initializing the FPGA RAMs: 1. RAM initialization during the FPGA configuration by the M4 2. RAM can be initialized by M4 through the Wishbone interface as part of the FPGA IP RAM initialization as part of the FPGA configuration is...
- Mon Jun 08, 2020 2:56 pm
- Forum: EOS-S3
- Topic: RAM blocks in S3 programmable logic
- Replies: 6
- Views: 20393
Re: RAM blocks in S3 programmable logic
There is documentation on the RAM / FIFO usage in the installation package (<Install_Path>/symbiflow-arch-defs/install/docs/S3B_Hardmacro_User_Guide.docx) Regarding the design examples of using RAM and FIFO blocks, they are at: https://github.com/QuickLogic-Corp/symbiflow-arch-defs/tree/quicklogic-u...
Re: IO block
IO registers are not supported in this release, we will be supporting the IO registers in the next release.
Currently inpad, outpad, ckpad and bipad usage is supported. inpadff and outpadff will be supported in the next release.
Currently inpad, outpad, ckpad and bipad usage is supported. inpadff and outpadff will be supported in the next release.