/usr/bin/cmake -S/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs -B/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build --check-build-system CMakeFiles/Makefile.cmake 0
/usr/bin/cmake -E cmake_progress_start /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/CMakeFiles /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/CMakeFiles/progress.marks
make -f CMakeFiles/Makefile2 all
make[1]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/devices/ql-pp3e-virt/CMakeFiles/file_quicklogic_devices_ql-pp3e-virt_db_vpr.pickle.dir/build.make quicklogic/devices/ql-pp3e-virt/CMakeFiles/file_quicklogic_devices_ql-pp3e-virt_db_vpr.pickle.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/devices/ql-pp3e-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-pp3e-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-pp3e-virt/CMakeFiles/file_quicklogic_devices_ql-pp3e-virt_db_vpr.pickle.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/devices/ql-pp3e-virt/CMakeFiles/file_quicklogic_devices_ql-pp3e-virt_db_vpr.pickle.dir/build.make quicklogic/devices/ql-pp3e-virt/CMakeFiles/file_quicklogic_devices_ql-pp3e-virt_db_vpr.pickle.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating db_phy.pickle
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-pp3e-virt && /opt/openfpga/vtr/_pyenv/bin/python3 /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/data_import.py --techfile /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/ql-pp3e/Device\ Architecture\ Files/QLAL3S2.xml --routing-timing /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/ql-pp3e/Timing\ Data\ Files/qlal3s2_RoutingDelays.csv --db db_phy.pickle
WARNING: No pin in tile at 'Loc(x=8, y=10)' found for switchbox pin 'CZ' of 'SB_LC_X8Y10' at 'Loc(x=8, y=10)'
WARNING: No pin in tile at 'Loc(x=8, y=10)' found for switchbox pin 'FZ' of 'SB_LC_X8Y10' at 'Loc(x=8, y=10)'
WARNING: No pin in tile at 'Loc(x=8, y=10)' found for switchbox pin 'QZ' of 'SB_LC_X8Y10' at 'Loc(x=8, y=10)'
WARNING: No pin in tile at 'Loc(x=8, y=10)' found for switchbox pin 'TZ' of 'SB_LC_X8Y10' at 'Loc(x=8, y=10)'
WARNING: No pin in tile at 'Loc(x=8, y=10)' found for switchbox pin 'TBS' of 'SB_LC_X8Y10' at 'Loc(x=8, y=10)'
WARNING: No pin in tile at 'Loc(x=8, y=10)' found for switchbox pin 'TB2' of 'SB_LC_X8Y10' at 'Loc(x=8, y=10)'
WARNING: No pin in tile at 'Loc(x=8, y=10)' found for switchbox pin 'BA2' of 'SB_LC_X8Y10' at 'Loc(x=8, y=10)'
WARNING: No pin in tile at 'Loc(x=8, y=10)' found for switchbox pin 'BB1' of 'SB_LC_X8Y10' at 'Loc(x=8, y=10)'
WARNING: No pin in tile at 'Loc(x=8, y=10)' found for switchbox pin 'QCK' of 'SB_LC_X8Y10' at 'Loc(x=8, y=10)'
WARNING: No pin in tile at 'Loc(x=8, y=10)' found for switchbox pin 'QRT' of 'SB_LC_X8Y10' at 'Loc(x=8, y=10)'
WARNING: No pin in tile at 'Loc(x=8, y=10)' found for switchbox pin 'F2' of 'SB_LC_X8Y10' at 'Loc(x=8, y=10)'
WARNING: No pin in tile at 'Loc(x=8, y=10)' found for switchbox pin 'TAB' of 'SB_LC_X8Y10' at 'Loc(x=8, y=10)'
WARNING: No pin in tile at 'Loc(x=8, y=10)' found for switchbox pin 'QDI' of 'SB_LC_X8Y10' at 'Loc(x=8, y=10)'
WARNING: No pin in tile at 'Loc(x=24, y=10)' found for switchbox pin 'CZ' of 'SB_LC_X24Y10' at 'Loc(x=24, y=10)'
WARNING: No pin in tile at 'Loc(x=24, y=10)' found for switchbox pin 'FZ' of 'SB_LC_X24Y10' at 'Loc(x=24, y=10)'
WARNING: No pin in tile at 'Loc(x=24, y=10)' found for switchbox pin 'QZ' of 'SB_LC_X24Y10' at 'Loc(x=24, y=10)'
WARNING: No pin in tile at 'Loc(x=24, y=10)' found for switchbox pin 'TZ' of 'SB_LC_X24Y10' at 'Loc(x=24, y=10)'
WARNING: No pin in tile at 'Loc(x=24, y=10)' found for switchbox pin 'TBS' of 'SB_LC_X24Y10' at 'Loc(x=24, y=10)'
WARNING: No pin in tile at 'Loc(x=24, y=10)' found for switchbox pin 'TB2' of 'SB_LC_X24Y10' at 'Loc(x=24, y=10)'
WARNING: No pin in tile at 'Loc(x=24, y=10)' found for switchbox pin 'BA2' of 'SB_LC_X24Y10' at 'Loc(x=24, y=10)'
WARNING: No pin in tile at 'Loc(x=24, y=10)' found for switchbox pin 'BB1' of 'SB_LC_X24Y10' at 'Loc(x=24, y=10)'
WARNING: No pin in tile at 'Loc(x=24, y=10)' found for switchbox pin 'QCK' of 'SB_LC_X24Y10' at 'Loc(x=24, y=10)'
WARNING: No pin in tile at 'Loc(x=24, y=10)' found for switchbox pin 'QRT' of 'SB_LC_X24Y10' at 'Loc(x=24, y=10)'
WARNING: No pin in tile at 'Loc(x=24, y=10)' found for switchbox pin 'F2' of 'SB_LC_X24Y10' at 'Loc(x=24, y=10)'
WARNING: No pin in tile at 'Loc(x=24, y=10)' found for switchbox pin 'TAB' of 'SB_LC_X24Y10' at 'Loc(x=24, y=10)'
WARNING: No pin in tile at 'Loc(x=24, y=10)' found for switchbox pin 'QDI' of 'SB_LC_X24Y10' at 'Loc(x=24, y=10)'
WARNING: No pin in tile at 'Loc(x=16, y=18)' found for switchbox pin 'CZ' of 'SB_LC_X16Y18' at 'Loc(x=16, y=18)'
WARNING: No pin in tile at 'Loc(x=16, y=18)' found for switchbox pin 'FZ' of 'SB_LC_X16Y18' at 'Loc(x=16, y=18)'
WARNING: No pin in tile at 'Loc(x=16, y=18)' found for switchbox pin 'QZ' of 'SB_LC_X16Y18' at 'Loc(x=16, y=18)'
WARNING: No pin in tile at 'Loc(x=16, y=18)' found for switchbox pin 'TZ' of 'SB_LC_X16Y18' at 'Loc(x=16, y=18)'
WARNING: No pin in tile at 'Loc(x=16, y=18)' found for switchbox pin 'QST' of 'SB_LC_X16Y18' at 'Loc(x=16, y=18)'
WARNING: No pin in tile at 'Loc(x=16, y=18)' found for switchbox pin 'TBS' of 'SB_LC_X16Y18' at 'Loc(x=16, y=18)'
WARNING: No pin in tile at 'Loc(x=16, y=18)' found for switchbox pin 'TB2' of 'SB_LC_X16Y18' at 'Loc(x=16, y=18)'
WARNING: No pin in tile at 'Loc(x=16, y=18)' found for switchbox pin 'BAB' of 'SB_LC_X16Y18' at 'Loc(x=16, y=18)'
WARNING: No pin in tile at 'Loc(x=16, y=18)' found for switchbox pin 'BA2' of 'SB_LC_X16Y18' at 'Loc(x=16, y=18)'
WARNING: No pin in tile at 'Loc(x=16, y=18)' found for switchbox pin 'BB1' of 'SB_LC_X16Y18' at 'Loc(x=16, y=18)'
WARNING: No pin in tile at 'Loc(x=16, y=18)' found for switchbox pin 'QEN' of 'SB_LC_X16Y18' at 'Loc(x=16, y=18)'
WARNING: No pin in tile at 'Loc(x=16, y=18)' found for switchbox pin 'QCK' of 'SB_LC_X16Y18' at 'Loc(x=16, y=18)'
WARNING: No pin in tile at 'Loc(x=16, y=18)' found for switchbox pin 'QRT' of 'SB_LC_X16Y18' at 'Loc(x=16, y=18)'
WARNING: No pin in tile at 'Loc(x=16, y=18)' found for switchbox pin 'F2' of 'SB_LC_X16Y18' at 'Loc(x=16, y=18)'
WARNING: No pin in tile at 'Loc(x=16, y=18)' found for switchbox pin 'FS' of 'SB_LC_X16Y18' at 'Loc(x=16, y=18)'
WARNING: No pin in tile at 'Loc(x=16, y=18)' found for switchbox pin 'TAB' of 'SB_LC_X16Y18' at 'Loc(x=16, y=18)'
WARNING: No pin in tile at 'Loc(x=16, y=18)' found for switchbox pin 'QDI' of 'SB_LC_X16Y18' at 'Loc(x=16, y=18)'
WARNING: No pin in tile at 'Loc(x=16, y=18)' found for switchbox pin 'F1' of 'SB_LC_X16Y18' at 'Loc(x=16, y=18)'
WARNING: No pin in tile at 'Loc(x=8, y=26)' found for switchbox pin 'CZ' of 'SB_LC_X8Y26' at 'Loc(x=8, y=26)'
WARNING: No pin in tile at 'Loc(x=8, y=26)' found for switchbox pin 'FZ' of 'SB_LC_X8Y26' at 'Loc(x=8, y=26)'
WARNING: No pin in tile at 'Loc(x=8, y=26)' found for switchbox pin 'QZ' of 'SB_LC_X8Y26' at 'Loc(x=8, y=26)'
WARNING: No pin in tile at 'Loc(x=8, y=26)' found for switchbox pin 'TZ' of 'SB_LC_X8Y26' at 'Loc(x=8, y=26)'
WARNING: No pin in tile at 'Loc(x=8, y=26)' found for switchbox pin 'TBS' of 'SB_LC_X8Y26' at 'Loc(x=8, y=26)'
WARNING: No pin in tile at 'Loc(x=8, y=26)' found for switchbox pin 'TB2' of 'SB_LC_X8Y26' at 'Loc(x=8, y=26)'
WARNING: No pin in tile at 'Loc(x=8, y=26)' found for switchbox pin 'BA2' of 'SB_LC_X8Y26' at 'Loc(x=8, y=26)'
WARNING: No pin in tile at 'Loc(x=8, y=26)' found for switchbox pin 'BB1' of 'SB_LC_X8Y26' at 'Loc(x=8, y=26)'
WARNING: No pin in tile at 'Loc(x=8, y=26)' found for switchbox pin 'QCK' of 'SB_LC_X8Y26' at 'Loc(x=8, y=26)'
WARNING: No pin in tile at 'Loc(x=8, y=26)' found for switchbox pin 'QRT' of 'SB_LC_X8Y26' at 'Loc(x=8, y=26)'
WARNING: No pin in tile at 'Loc(x=8, y=26)' found for switchbox pin 'F2' of 'SB_LC_X8Y26' at 'Loc(x=8, y=26)'
WARNING: No pin in tile at 'Loc(x=8, y=26)' found for switchbox pin 'TAB' of 'SB_LC_X8Y26' at 'Loc(x=8, y=26)'
WARNING: No pin in tile at 'Loc(x=8, y=26)' found for switchbox pin 'QDI' of 'SB_LC_X8Y26' at 'Loc(x=8, y=26)'
WARNING: No pin in tile at 'Loc(x=24, y=26)' found for switchbox pin 'CZ' of 'SB_LC_X24Y26' at 'Loc(x=24, y=26)'
WARNING: No pin in tile at 'Loc(x=24, y=26)' found for switchbox pin 'FZ' of 'SB_LC_X24Y26' at 'Loc(x=24, y=26)'
WARNING: No pin in tile at 'Loc(x=24, y=26)' found for switchbox pin 'QZ' of 'SB_LC_X24Y26' at 'Loc(x=24, y=26)'
WARNING: No pin in tile at 'Loc(x=24, y=26)' found for switchbox pin 'TZ' of 'SB_LC_X24Y26' at 'Loc(x=24, y=26)'
WARNING: No pin in tile at 'Loc(x=24, y=26)' found for switchbox pin 'TBS' of 'SB_LC_X24Y26' at 'Loc(x=24, y=26)'
WARNING: No pin in tile at 'Loc(x=24, y=26)' found for switchbox pin 'TB2' of 'SB_LC_X24Y26' at 'Loc(x=24, y=26)'
WARNING: No pin in tile at 'Loc(x=24, y=26)' found for switchbox pin 'BA2' of 'SB_LC_X24Y26' at 'Loc(x=24, y=26)'
WARNING: No pin in tile at 'Loc(x=24, y=26)' found for switchbox pin 'BB1' of 'SB_LC_X24Y26' at 'Loc(x=24, y=26)'
WARNING: No pin in tile at 'Loc(x=24, y=26)' found for switchbox pin 'QCK' of 'SB_LC_X24Y26' at 'Loc(x=24, y=26)'
WARNING: No pin in tile at 'Loc(x=24, y=26)' found for switchbox pin 'QRT' of 'SB_LC_X24Y26' at 'Loc(x=24, y=26)'
WARNING: No pin in tile at 'Loc(x=24, y=26)' found for switchbox pin 'F2' of 'SB_LC_X24Y26' at 'Loc(x=24, y=26)'
WARNING: No pin in tile at 'Loc(x=24, y=26)' found for switchbox pin 'TAB' of 'SB_LC_X24Y26' at 'Loc(x=24, y=26)'
WARNING: No pin in tile at 'Loc(x=24, y=26)' found for switchbox pin 'QDI' of 'SB_LC_X24Y26' at 'Loc(x=24, y=26)'
WARNING: No pin in tile at 'Loc(x=1, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X1Y1' at 'Loc(x=1, y=1)'
WARNING: No pin in tile at 'Loc(x=1, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X1Y1' at 'Loc(x=1, y=1)'
WARNING: No pin in tile at 'Loc(x=1, y=1)' found for switchbox pin 'FIFO_EN_0' of 'SB_TOP_IFC_X1Y1' at 'Loc(x=1, y=1)'
WARNING: No pin in tile at 'Loc(x=1, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X1Y1' at 'Loc(x=1, y=1)'
WARNING: No pin in tile at 'Loc(x=1, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X1Y1' at 'Loc(x=1, y=1)'
WARNING: No pin in tile at 'Loc(x=2, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X2Y1' at 'Loc(x=2, y=1)'
WARNING: No pin in tile at 'Loc(x=2, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X2Y1' at 'Loc(x=2, y=1)'
WARNING: No pin in tile at 'Loc(x=2, y=1)' found for switchbox pin 'SYNC_FIFO_0' of 'SB_TOP_IFC_X2Y1' at 'Loc(x=2, y=1)'
WARNING: No pin in tile at 'Loc(x=2, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X2Y1' at 'Loc(x=2, y=1)'
WARNING: No pin in tile at 'Loc(x=2, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X2Y1' at 'Loc(x=2, y=1)'
WARNING: No pin in tile at 'Loc(x=3, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X3Y1' at 'Loc(x=3, y=1)'
WARNING: No pin in tile at 'Loc(x=3, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X3Y1' at 'Loc(x=3, y=1)'
WARNING: No pin in tile at 'Loc(x=3, y=1)' found for switchbox pin 'PIPELINE_RD_0' of 'SB_TOP_IFC_X3Y1' at 'Loc(x=3, y=1)'
WARNING: No pin in tile at 'Loc(x=3, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X3Y1' at 'Loc(x=3, y=1)'
WARNING: No pin in tile at 'Loc(x=3, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X3Y1' at 'Loc(x=3, y=1)'
WARNING: No pin in tile at 'Loc(x=4, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X4Y1' at 'Loc(x=4, y=1)'
WARNING: No pin in tile at 'Loc(x=4, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X4Y1' at 'Loc(x=4, y=1)'
WARNING: No pin in tile at 'Loc(x=4, y=1)' found for switchbox pin 'CONCAT_EN_0' of 'SB_TOP_IFC_X4Y1' at 'Loc(x=4, y=1)'
WARNING: No pin in tile at 'Loc(x=4, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X4Y1' at 'Loc(x=4, y=1)'
WARNING: No pin in tile at 'Loc(x=4, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X4Y1' at 'Loc(x=4, y=1)'
WARNING: No pin in tile at 'Loc(x=5, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X5Y1' at 'Loc(x=5, y=1)'
WARNING: No pin in tile at 'Loc(x=5, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X5Y1' at 'Loc(x=5, y=1)'
WARNING: No pin in tile at 'Loc(x=5, y=1)' found for switchbox pin 'WIDTH_SELECT1_0[0]' of 'SB_TOP_IFC_X5Y1' at 'Loc(x=5, y=1)'
WARNING: No pin in tile at 'Loc(x=5, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X5Y1' at 'Loc(x=5, y=1)'
WARNING: No pin in tile at 'Loc(x=5, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X5Y1' at 'Loc(x=5, y=1)'
WARNING: No pin in tile at 'Loc(x=6, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X6Y1' at 'Loc(x=6, y=1)'
WARNING: No pin in tile at 'Loc(x=6, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X6Y1' at 'Loc(x=6, y=1)'
WARNING: No pin in tile at 'Loc(x=6, y=1)' found for switchbox pin 'WIDTH_SELECT1_0[1]' of 'SB_TOP_IFC_X6Y1' at 'Loc(x=6, y=1)'
WARNING: No pin in tile at 'Loc(x=6, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X6Y1' at 'Loc(x=6, y=1)'
WARNING: No pin in tile at 'Loc(x=6, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X6Y1' at 'Loc(x=6, y=1)'
WARNING: No pin in tile at 'Loc(x=7, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X7Y1' at 'Loc(x=7, y=1)'
WARNING: No pin in tile at 'Loc(x=7, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X7Y1' at 'Loc(x=7, y=1)'
WARNING: No pin in tile at 'Loc(x=7, y=1)' found for switchbox pin 'WIDTH_SELECT2_0[0]' of 'SB_TOP_IFC_X7Y1' at 'Loc(x=7, y=1)'
WARNING: No pin in tile at 'Loc(x=7, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X7Y1' at 'Loc(x=7, y=1)'
WARNING: No pin in tile at 'Loc(x=7, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X7Y1' at 'Loc(x=7, y=1)'
WARNING: No pin in tile at 'Loc(x=8, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X8Y1' at 'Loc(x=8, y=1)'
WARNING: No pin in tile at 'Loc(x=8, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X8Y1' at 'Loc(x=8, y=1)'
WARNING: No pin in tile at 'Loc(x=8, y=1)' found for switchbox pin 'WIDTH_SELECT2_0[1]' of 'SB_TOP_IFC_X8Y1' at 'Loc(x=8, y=1)'
WARNING: No pin in tile at 'Loc(x=8, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X8Y1' at 'Loc(x=8, y=1)'
WARNING: No pin in tile at 'Loc(x=8, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X8Y1' at 'Loc(x=8, y=1)'
WARNING: No pin in tile at 'Loc(x=9, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X9Y1' at 'Loc(x=9, y=1)'
WARNING: No pin in tile at 'Loc(x=9, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X9Y1' at 'Loc(x=9, y=1)'
WARNING: No pin in tile at 'Loc(x=9, y=1)' found for switchbox pin 'FIFO_EN_1' of 'SB_TOP_IFC_X9Y1' at 'Loc(x=9, y=1)'
WARNING: No pin in tile at 'Loc(x=9, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X9Y1' at 'Loc(x=9, y=1)'
WARNING: No pin in tile at 'Loc(x=9, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X9Y1' at 'Loc(x=9, y=1)'
WARNING: No pin in tile at 'Loc(x=10, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X10Y1' at 'Loc(x=10, y=1)'
WARNING: No pin in tile at 'Loc(x=10, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X10Y1' at 'Loc(x=10, y=1)'
WARNING: No pin in tile at 'Loc(x=10, y=1)' found for switchbox pin 'SYNC_FIFO_1' of 'SB_TOP_IFC_X10Y1' at 'Loc(x=10, y=1)'
WARNING: No pin in tile at 'Loc(x=10, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X10Y1' at 'Loc(x=10, y=1)'
WARNING: No pin in tile at 'Loc(x=10, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X10Y1' at 'Loc(x=10, y=1)'
WARNING: No pin in tile at 'Loc(x=11, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X11Y1' at 'Loc(x=11, y=1)'
WARNING: No pin in tile at 'Loc(x=11, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X11Y1' at 'Loc(x=11, y=1)'
WARNING: No pin in tile at 'Loc(x=11, y=1)' found for switchbox pin 'PIPELINE_RD_1' of 'SB_TOP_IFC_X11Y1' at 'Loc(x=11, y=1)'
WARNING: No pin in tile at 'Loc(x=11, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X11Y1' at 'Loc(x=11, y=1)'
WARNING: No pin in tile at 'Loc(x=11, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X11Y1' at 'Loc(x=11, y=1)'
WARNING: No pin in tile at 'Loc(x=12, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X12Y1' at 'Loc(x=12, y=1)'
WARNING: No pin in tile at 'Loc(x=12, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X12Y1' at 'Loc(x=12, y=1)'
WARNING: No pin in tile at 'Loc(x=12, y=1)' found for switchbox pin 'CONCAT_EN_1' of 'SB_TOP_IFC_X12Y1' at 'Loc(x=12, y=1)'
WARNING: No pin in tile at 'Loc(x=12, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X12Y1' at 'Loc(x=12, y=1)'
WARNING: No pin in tile at 'Loc(x=12, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X12Y1' at 'Loc(x=12, y=1)'
WARNING: No pin in tile at 'Loc(x=13, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X13Y1' at 'Loc(x=13, y=1)'
WARNING: No pin in tile at 'Loc(x=13, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X13Y1' at 'Loc(x=13, y=1)'
WARNING: No pin in tile at 'Loc(x=13, y=1)' found for switchbox pin 'WIDTH_SELECT1_1[0]' of 'SB_TOP_IFC_X13Y1' at 'Loc(x=13, y=1)'
WARNING: No pin in tile at 'Loc(x=13, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X13Y1' at 'Loc(x=13, y=1)'
WARNING: No pin in tile at 'Loc(x=13, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X13Y1' at 'Loc(x=13, y=1)'
WARNING: No pin in tile at 'Loc(x=14, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X14Y1' at 'Loc(x=14, y=1)'
WARNING: No pin in tile at 'Loc(x=14, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X14Y1' at 'Loc(x=14, y=1)'
WARNING: No pin in tile at 'Loc(x=14, y=1)' found for switchbox pin 'WIDTH_SELECT1_1[1]' of 'SB_TOP_IFC_X14Y1' at 'Loc(x=14, y=1)'
WARNING: No pin in tile at 'Loc(x=14, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X14Y1' at 'Loc(x=14, y=1)'
WARNING: No pin in tile at 'Loc(x=14, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X14Y1' at 'Loc(x=14, y=1)'
WARNING: No pin in tile at 'Loc(x=15, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X15Y1' at 'Loc(x=15, y=1)'
WARNING: No pin in tile at 'Loc(x=15, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X15Y1' at 'Loc(x=15, y=1)'
WARNING: No pin in tile at 'Loc(x=15, y=1)' found for switchbox pin 'WIDTH_SELECT2_1[0]' of 'SB_TOP_IFC_X15Y1' at 'Loc(x=15, y=1)'
WARNING: No pin in tile at 'Loc(x=15, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X15Y1' at 'Loc(x=15, y=1)'
WARNING: No pin in tile at 'Loc(x=15, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X15Y1' at 'Loc(x=15, y=1)'
WARNING: No pin in tile at 'Loc(x=16, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X16Y1' at 'Loc(x=16, y=1)'
WARNING: No pin in tile at 'Loc(x=16, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X16Y1' at 'Loc(x=16, y=1)'
WARNING: No pin in tile at 'Loc(x=16, y=1)' found for switchbox pin 'WIDTH_SELECT2_1[1]' of 'SB_TOP_IFC_X16Y1' at 'Loc(x=16, y=1)'
WARNING: No pin in tile at 'Loc(x=16, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X16Y1' at 'Loc(x=16, y=1)'
WARNING: No pin in tile at 'Loc(x=16, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X16Y1' at 'Loc(x=16, y=1)'
WARNING: No pin in tile at 'Loc(x=17, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X17Y1' at 'Loc(x=17, y=1)'
WARNING: No pin in tile at 'Loc(x=17, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X17Y1' at 'Loc(x=17, y=1)'
WARNING: No pin in tile at 'Loc(x=17, y=1)' found for switchbox pin 'FIFO_EN_0' of 'SB_TOP_IFC_X17Y1' at 'Loc(x=17, y=1)'
WARNING: No pin in tile at 'Loc(x=17, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X17Y1' at 'Loc(x=17, y=1)'
WARNING: No pin in tile at 'Loc(x=17, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X17Y1' at 'Loc(x=17, y=1)'
WARNING: No pin in tile at 'Loc(x=18, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X18Y1' at 'Loc(x=18, y=1)'
WARNING: No pin in tile at 'Loc(x=18, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X18Y1' at 'Loc(x=18, y=1)'
WARNING: No pin in tile at 'Loc(x=18, y=1)' found for switchbox pin 'SYNC_FIFO_0' of 'SB_TOP_IFC_X18Y1' at 'Loc(x=18, y=1)'
WARNING: No pin in tile at 'Loc(x=18, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X18Y1' at 'Loc(x=18, y=1)'
WARNING: No pin in tile at 'Loc(x=18, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X18Y1' at 'Loc(x=18, y=1)'
WARNING: No pin in tile at 'Loc(x=19, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X19Y1' at 'Loc(x=19, y=1)'
WARNING: No pin in tile at 'Loc(x=19, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X19Y1' at 'Loc(x=19, y=1)'
WARNING: No pin in tile at 'Loc(x=19, y=1)' found for switchbox pin 'PIPELINE_RD_0' of 'SB_TOP_IFC_X19Y1' at 'Loc(x=19, y=1)'
WARNING: No pin in tile at 'Loc(x=19, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X19Y1' at 'Loc(x=19, y=1)'
WARNING: No pin in tile at 'Loc(x=19, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X19Y1' at 'Loc(x=19, y=1)'
WARNING: No pin in tile at 'Loc(x=20, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X20Y1' at 'Loc(x=20, y=1)'
WARNING: No pin in tile at 'Loc(x=20, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X20Y1' at 'Loc(x=20, y=1)'
WARNING: No pin in tile at 'Loc(x=20, y=1)' found for switchbox pin 'CONCAT_EN_0' of 'SB_TOP_IFC_X20Y1' at 'Loc(x=20, y=1)'
WARNING: No pin in tile at 'Loc(x=20, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X20Y1' at 'Loc(x=20, y=1)'
WARNING: No pin in tile at 'Loc(x=20, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X20Y1' at 'Loc(x=20, y=1)'
WARNING: No pin in tile at 'Loc(x=21, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X21Y1' at 'Loc(x=21, y=1)'
WARNING: No pin in tile at 'Loc(x=21, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X21Y1' at 'Loc(x=21, y=1)'
WARNING: No pin in tile at 'Loc(x=21, y=1)' found for switchbox pin 'WIDTH_SELECT1_0[0]' of 'SB_TOP_IFC_X21Y1' at 'Loc(x=21, y=1)'
WARNING: No pin in tile at 'Loc(x=21, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X21Y1' at 'Loc(x=21, y=1)'
WARNING: No pin in tile at 'Loc(x=21, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X21Y1' at 'Loc(x=21, y=1)'
WARNING: No pin in tile at 'Loc(x=22, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X22Y1' at 'Loc(x=22, y=1)'
WARNING: No pin in tile at 'Loc(x=22, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X22Y1' at 'Loc(x=22, y=1)'
WARNING: No pin in tile at 'Loc(x=22, y=1)' found for switchbox pin 'WIDTH_SELECT1_0[1]' of 'SB_TOP_IFC_X22Y1' at 'Loc(x=22, y=1)'
WARNING: No pin in tile at 'Loc(x=22, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X22Y1' at 'Loc(x=22, y=1)'
WARNING: No pin in tile at 'Loc(x=22, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X22Y1' at 'Loc(x=22, y=1)'
WARNING: No pin in tile at 'Loc(x=23, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X23Y1' at 'Loc(x=23, y=1)'
WARNING: No pin in tile at 'Loc(x=23, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X23Y1' at 'Loc(x=23, y=1)'
WARNING: No pin in tile at 'Loc(x=23, y=1)' found for switchbox pin 'WIDTH_SELECT2_0[0]' of 'SB_TOP_IFC_X23Y1' at 'Loc(x=23, y=1)'
WARNING: No pin in tile at 'Loc(x=23, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X23Y1' at 'Loc(x=23, y=1)'
WARNING: No pin in tile at 'Loc(x=23, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X23Y1' at 'Loc(x=23, y=1)'
WARNING: No pin in tile at 'Loc(x=24, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X24Y1' at 'Loc(x=24, y=1)'
WARNING: No pin in tile at 'Loc(x=24, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X24Y1' at 'Loc(x=24, y=1)'
WARNING: No pin in tile at 'Loc(x=24, y=1)' found for switchbox pin 'WIDTH_SELECT2_0[1]' of 'SB_TOP_IFC_X24Y1' at 'Loc(x=24, y=1)'
WARNING: No pin in tile at 'Loc(x=24, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X24Y1' at 'Loc(x=24, y=1)'
WARNING: No pin in tile at 'Loc(x=24, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X24Y1' at 'Loc(x=24, y=1)'
WARNING: No pin in tile at 'Loc(x=25, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X25Y1' at 'Loc(x=25, y=1)'
WARNING: No pin in tile at 'Loc(x=25, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X25Y1' at 'Loc(x=25, y=1)'
WARNING: No pin in tile at 'Loc(x=25, y=1)' found for switchbox pin 'FIFO_EN_1' of 'SB_TOP_IFC_X25Y1' at 'Loc(x=25, y=1)'
WARNING: No pin in tile at 'Loc(x=25, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X25Y1' at 'Loc(x=25, y=1)'
WARNING: No pin in tile at 'Loc(x=25, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X25Y1' at 'Loc(x=25, y=1)'
WARNING: No pin in tile at 'Loc(x=26, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X26Y1' at 'Loc(x=26, y=1)'
WARNING: No pin in tile at 'Loc(x=26, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X26Y1' at 'Loc(x=26, y=1)'
WARNING: No pin in tile at 'Loc(x=26, y=1)' found for switchbox pin 'SYNC_FIFO_1' of 'SB_TOP_IFC_X26Y1' at 'Loc(x=26, y=1)'
WARNING: No pin in tile at 'Loc(x=26, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X26Y1' at 'Loc(x=26, y=1)'
WARNING: No pin in tile at 'Loc(x=26, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X26Y1' at 'Loc(x=26, y=1)'
WARNING: No pin in tile at 'Loc(x=27, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X27Y1' at 'Loc(x=27, y=1)'
WARNING: No pin in tile at 'Loc(x=27, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X27Y1' at 'Loc(x=27, y=1)'
WARNING: No pin in tile at 'Loc(x=27, y=1)' found for switchbox pin 'PIPELINE_RD_1' of 'SB_TOP_IFC_X27Y1' at 'Loc(x=27, y=1)'
WARNING: No pin in tile at 'Loc(x=27, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X27Y1' at 'Loc(x=27, y=1)'
WARNING: No pin in tile at 'Loc(x=27, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X27Y1' at 'Loc(x=27, y=1)'
WARNING: No pin in tile at 'Loc(x=28, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X28Y1' at 'Loc(x=28, y=1)'
WARNING: No pin in tile at 'Loc(x=28, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X28Y1' at 'Loc(x=28, y=1)'
WARNING: No pin in tile at 'Loc(x=28, y=1)' found for switchbox pin 'CONCAT_EN_1' of 'SB_TOP_IFC_X28Y1' at 'Loc(x=28, y=1)'
WARNING: No pin in tile at 'Loc(x=28, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X28Y1' at 'Loc(x=28, y=1)'
WARNING: No pin in tile at 'Loc(x=28, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X28Y1' at 'Loc(x=28, y=1)'
WARNING: No pin in tile at 'Loc(x=29, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X29Y1' at 'Loc(x=29, y=1)'
WARNING: No pin in tile at 'Loc(x=29, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X29Y1' at 'Loc(x=29, y=1)'
WARNING: No pin in tile at 'Loc(x=29, y=1)' found for switchbox pin 'WIDTH_SELECT1_1[0]' of 'SB_TOP_IFC_X29Y1' at 'Loc(x=29, y=1)'
WARNING: No pin in tile at 'Loc(x=29, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X29Y1' at 'Loc(x=29, y=1)'
WARNING: No pin in tile at 'Loc(x=29, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X29Y1' at 'Loc(x=29, y=1)'
WARNING: No pin in tile at 'Loc(x=30, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X30Y1' at 'Loc(x=30, y=1)'
WARNING: No pin in tile at 'Loc(x=30, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X30Y1' at 'Loc(x=30, y=1)'
WARNING: No pin in tile at 'Loc(x=30, y=1)' found for switchbox pin 'WIDTH_SELECT1_1[1]' of 'SB_TOP_IFC_X30Y1' at 'Loc(x=30, y=1)'
WARNING: No pin in tile at 'Loc(x=30, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X30Y1' at 'Loc(x=30, y=1)'
WARNING: No pin in tile at 'Loc(x=30, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X30Y1' at 'Loc(x=30, y=1)'
WARNING: No pin in tile at 'Loc(x=31, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X31Y1' at 'Loc(x=31, y=1)'
WARNING: No pin in tile at 'Loc(x=31, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X31Y1' at 'Loc(x=31, y=1)'
WARNING: No pin in tile at 'Loc(x=31, y=1)' found for switchbox pin 'WIDTH_SELECT2_1[0]' of 'SB_TOP_IFC_X31Y1' at 'Loc(x=31, y=1)'
WARNING: No pin in tile at 'Loc(x=31, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X31Y1' at 'Loc(x=31, y=1)'
WARNING: No pin in tile at 'Loc(x=31, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X31Y1' at 'Loc(x=31, y=1)'
WARNING: No pin in tile at 'Loc(x=32, y=1)' found for switchbox pin 'A2F_hop_t_io_2' of 'SB_TOP_IFC_X32Y1' at 'Loc(x=32, y=1)'
WARNING: No pin in tile at 'Loc(x=32, y=1)' found for switchbox pin 'A2F_hop_t_io_1' of 'SB_TOP_IFC_X32Y1' at 'Loc(x=32, y=1)'
WARNING: No pin in tile at 'Loc(x=32, y=1)' found for switchbox pin 'WIDTH_SELECT2_1[1]' of 'SB_TOP_IFC_X32Y1' at 'Loc(x=32, y=1)'
WARNING: No pin in tile at 'Loc(x=32, y=1)' found for switchbox pin 'WPD' of 'SB_TOP_IFC_X32Y1' at 'Loc(x=32, y=1)'
WARNING: No pin in tile at 'Loc(x=32, y=1)' found for switchbox pin 'DS' of 'SB_TOP_IFC_X32Y1' at 'Loc(x=32, y=1)'
WARNING: No pin in tile at 'Loc(x=1, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X1Y34' at 'Loc(x=1, y=34)'
WARNING: No pin in tile at 'Loc(x=1, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X1Y34' at 'Loc(x=1, y=34)'
WARNING: No pin in tile at 'Loc(x=1, y=34)' found for switchbox pin 'FIFO_EN_0' of 'SB_BOTTOM_IFC_X1Y34' at 'Loc(x=1, y=34)'
WARNING: No pin in tile at 'Loc(x=1, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X1Y34' at 'Loc(x=1, y=34)'
WARNING: No pin in tile at 'Loc(x=1, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X1Y34' at 'Loc(x=1, y=34)'
WARNING: No pin in tile at 'Loc(x=2, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X2Y34' at 'Loc(x=2, y=34)'
WARNING: No pin in tile at 'Loc(x=2, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X2Y34' at 'Loc(x=2, y=34)'
WARNING: No pin in tile at 'Loc(x=2, y=34)' found for switchbox pin 'SYNC_FIFO_0' of 'SB_BOTTOM_IFC_X2Y34' at 'Loc(x=2, y=34)'
WARNING: No pin in tile at 'Loc(x=2, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X2Y34' at 'Loc(x=2, y=34)'
WARNING: No pin in tile at 'Loc(x=2, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X2Y34' at 'Loc(x=2, y=34)'
WARNING: No pin in tile at 'Loc(x=3, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X3Y34' at 'Loc(x=3, y=34)'
WARNING: No pin in tile at 'Loc(x=3, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X3Y34' at 'Loc(x=3, y=34)'
WARNING: No pin in tile at 'Loc(x=3, y=34)' found for switchbox pin 'PIPELINE_RD_0' of 'SB_BOTTOM_IFC_X3Y34' at 'Loc(x=3, y=34)'
WARNING: No pin in tile at 'Loc(x=3, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X3Y34' at 'Loc(x=3, y=34)'
WARNING: No pin in tile at 'Loc(x=3, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X3Y34' at 'Loc(x=3, y=34)'
WARNING: No pin in tile at 'Loc(x=4, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X4Y34' at 'Loc(x=4, y=34)'
WARNING: No pin in tile at 'Loc(x=4, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X4Y34' at 'Loc(x=4, y=34)'
WARNING: No pin in tile at 'Loc(x=4, y=34)' found for switchbox pin 'CONCAT_EN_0' of 'SB_BOTTOM_IFC_X4Y34' at 'Loc(x=4, y=34)'
WARNING: No pin in tile at 'Loc(x=4, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X4Y34' at 'Loc(x=4, y=34)'
WARNING: No pin in tile at 'Loc(x=4, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X4Y34' at 'Loc(x=4, y=34)'
WARNING: No pin in tile at 'Loc(x=5, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X5Y34' at 'Loc(x=5, y=34)'
WARNING: No pin in tile at 'Loc(x=5, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X5Y34' at 'Loc(x=5, y=34)'
WARNING: No pin in tile at 'Loc(x=5, y=34)' found for switchbox pin 'WIDTH_SELECT1_0[0]' of 'SB_BOTTOM_IFC_X5Y34' at 'Loc(x=5, y=34)'
WARNING: No pin in tile at 'Loc(x=5, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X5Y34' at 'Loc(x=5, y=34)'
WARNING: No pin in tile at 'Loc(x=5, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X5Y34' at 'Loc(x=5, y=34)'
WARNING: No pin in tile at 'Loc(x=6, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X6Y34' at 'Loc(x=6, y=34)'
WARNING: No pin in tile at 'Loc(x=6, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X6Y34' at 'Loc(x=6, y=34)'
WARNING: No pin in tile at 'Loc(x=6, y=34)' found for switchbox pin 'WIDTH_SELECT1_0[1]' of 'SB_BOTTOM_IFC_X6Y34' at 'Loc(x=6, y=34)'
WARNING: No pin in tile at 'Loc(x=6, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X6Y34' at 'Loc(x=6, y=34)'
WARNING: No pin in tile at 'Loc(x=6, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X6Y34' at 'Loc(x=6, y=34)'
WARNING: No pin in tile at 'Loc(x=7, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X7Y34' at 'Loc(x=7, y=34)'
WARNING: No pin in tile at 'Loc(x=7, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X7Y34' at 'Loc(x=7, y=34)'
WARNING: No pin in tile at 'Loc(x=7, y=34)' found for switchbox pin 'WIDTH_SELECT2_0[0]' of 'SB_BOTTOM_IFC_X7Y34' at 'Loc(x=7, y=34)'
WARNING: No pin in tile at 'Loc(x=7, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X7Y34' at 'Loc(x=7, y=34)'
WARNING: No pin in tile at 'Loc(x=7, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X7Y34' at 'Loc(x=7, y=34)'
WARNING: No pin in tile at 'Loc(x=8, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X8Y34' at 'Loc(x=8, y=34)'
WARNING: No pin in tile at 'Loc(x=8, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X8Y34' at 'Loc(x=8, y=34)'
WARNING: No pin in tile at 'Loc(x=8, y=34)' found for switchbox pin 'WIDTH_SELECT2_0[1]' of 'SB_BOTTOM_IFC_X8Y34' at 'Loc(x=8, y=34)'
WARNING: No pin in tile at 'Loc(x=8, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X8Y34' at 'Loc(x=8, y=34)'
WARNING: No pin in tile at 'Loc(x=8, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X8Y34' at 'Loc(x=8, y=34)'
WARNING: No pin in tile at 'Loc(x=9, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X9Y34' at 'Loc(x=9, y=34)'
WARNING: No pin in tile at 'Loc(x=9, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X9Y34' at 'Loc(x=9, y=34)'
WARNING: No pin in tile at 'Loc(x=9, y=34)' found for switchbox pin 'FIFO_EN_1' of 'SB_BOTTOM_IFC_X9Y34' at 'Loc(x=9, y=34)'
WARNING: No pin in tile at 'Loc(x=9, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X9Y34' at 'Loc(x=9, y=34)'
WARNING: No pin in tile at 'Loc(x=9, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X9Y34' at 'Loc(x=9, y=34)'
WARNING: No pin in tile at 'Loc(x=10, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X10Y34' at 'Loc(x=10, y=34)'
WARNING: No pin in tile at 'Loc(x=10, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X10Y34' at 'Loc(x=10, y=34)'
WARNING: No pin in tile at 'Loc(x=10, y=34)' found for switchbox pin 'SYNC_FIFO_1' of 'SB_BOTTOM_IFC_X10Y34' at 'Loc(x=10, y=34)'
WARNING: No pin in tile at 'Loc(x=10, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X10Y34' at 'Loc(x=10, y=34)'
WARNING: No pin in tile at 'Loc(x=10, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X10Y34' at 'Loc(x=10, y=34)'
WARNING: No pin in tile at 'Loc(x=11, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X11Y34' at 'Loc(x=11, y=34)'
WARNING: No pin in tile at 'Loc(x=11, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X11Y34' at 'Loc(x=11, y=34)'
WARNING: No pin in tile at 'Loc(x=11, y=34)' found for switchbox pin 'PIPELINE_RD_1' of 'SB_BOTTOM_IFC_X11Y34' at 'Loc(x=11, y=34)'
WARNING: No pin in tile at 'Loc(x=11, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X11Y34' at 'Loc(x=11, y=34)'
WARNING: No pin in tile at 'Loc(x=11, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X11Y34' at 'Loc(x=11, y=34)'
WARNING: No pin in tile at 'Loc(x=12, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X12Y34' at 'Loc(x=12, y=34)'
WARNING: No pin in tile at 'Loc(x=12, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X12Y34' at 'Loc(x=12, y=34)'
WARNING: No pin in tile at 'Loc(x=12, y=34)' found for switchbox pin 'CONCAT_EN_1' of 'SB_BOTTOM_IFC_X12Y34' at 'Loc(x=12, y=34)'
WARNING: No pin in tile at 'Loc(x=12, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X12Y34' at 'Loc(x=12, y=34)'
WARNING: No pin in tile at 'Loc(x=12, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X12Y34' at 'Loc(x=12, y=34)'
WARNING: No pin in tile at 'Loc(x=13, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X13Y34' at 'Loc(x=13, y=34)'
WARNING: No pin in tile at 'Loc(x=13, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X13Y34' at 'Loc(x=13, y=34)'
WARNING: No pin in tile at 'Loc(x=13, y=34)' found for switchbox pin 'WIDTH_SELECT1_1[0]' of 'SB_BOTTOM_IFC_X13Y34' at 'Loc(x=13, y=34)'
WARNING: No pin in tile at 'Loc(x=13, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X13Y34' at 'Loc(x=13, y=34)'
WARNING: No pin in tile at 'Loc(x=13, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X13Y34' at 'Loc(x=13, y=34)'
WARNING: No pin in tile at 'Loc(x=14, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X14Y34' at 'Loc(x=14, y=34)'
WARNING: No pin in tile at 'Loc(x=14, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X14Y34' at 'Loc(x=14, y=34)'
WARNING: No pin in tile at 'Loc(x=14, y=34)' found for switchbox pin 'WIDTH_SELECT1_1[1]' of 'SB_BOTTOM_IFC_X14Y34' at 'Loc(x=14, y=34)'
WARNING: No pin in tile at 'Loc(x=14, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X14Y34' at 'Loc(x=14, y=34)'
WARNING: No pin in tile at 'Loc(x=14, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X14Y34' at 'Loc(x=14, y=34)'
WARNING: No pin in tile at 'Loc(x=15, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X15Y34' at 'Loc(x=15, y=34)'
WARNING: No pin in tile at 'Loc(x=15, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X15Y34' at 'Loc(x=15, y=34)'
WARNING: No pin in tile at 'Loc(x=15, y=34)' found for switchbox pin 'WIDTH_SELECT2_1[0]' of 'SB_BOTTOM_IFC_X15Y34' at 'Loc(x=15, y=34)'
WARNING: No pin in tile at 'Loc(x=15, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X15Y34' at 'Loc(x=15, y=34)'
WARNING: No pin in tile at 'Loc(x=15, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X15Y34' at 'Loc(x=15, y=34)'
WARNING: No pin in tile at 'Loc(x=16, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X16Y34' at 'Loc(x=16, y=34)'
WARNING: No pin in tile at 'Loc(x=16, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X16Y34' at 'Loc(x=16, y=34)'
WARNING: No pin in tile at 'Loc(x=16, y=34)' found for switchbox pin 'WIDTH_SELECT2_1[1]' of 'SB_BOTTOM_IFC_X16Y34' at 'Loc(x=16, y=34)'
WARNING: No pin in tile at 'Loc(x=16, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X16Y34' at 'Loc(x=16, y=34)'
WARNING: No pin in tile at 'Loc(x=16, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X16Y34' at 'Loc(x=16, y=34)'
WARNING: No pin in tile at 'Loc(x=17, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X17Y34' at 'Loc(x=17, y=34)'
WARNING: No pin in tile at 'Loc(x=17, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X17Y34' at 'Loc(x=17, y=34)'
WARNING: No pin in tile at 'Loc(x=17, y=34)' found for switchbox pin 'FIFO_EN_0' of 'SB_BOTTOM_IFC_X17Y34' at 'Loc(x=17, y=34)'
WARNING: No pin in tile at 'Loc(x=17, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X17Y34' at 'Loc(x=17, y=34)'
WARNING: No pin in tile at 'Loc(x=17, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X17Y34' at 'Loc(x=17, y=34)'
WARNING: No pin in tile at 'Loc(x=18, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X18Y34' at 'Loc(x=18, y=34)'
WARNING: No pin in tile at 'Loc(x=18, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X18Y34' at 'Loc(x=18, y=34)'
WARNING: No pin in tile at 'Loc(x=18, y=34)' found for switchbox pin 'SYNC_FIFO_0' of 'SB_BOTTOM_IFC_X18Y34' at 'Loc(x=18, y=34)'
WARNING: No pin in tile at 'Loc(x=18, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X18Y34' at 'Loc(x=18, y=34)'
WARNING: No pin in tile at 'Loc(x=18, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X18Y34' at 'Loc(x=18, y=34)'
WARNING: No pin in tile at 'Loc(x=19, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X19Y34' at 'Loc(x=19, y=34)'
WARNING: No pin in tile at 'Loc(x=19, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X19Y34' at 'Loc(x=19, y=34)'
WARNING: No pin in tile at 'Loc(x=19, y=34)' found for switchbox pin 'PIPELINE_RD_0' of 'SB_BOTTOM_IFC_X19Y34' at 'Loc(x=19, y=34)'
WARNING: No pin in tile at 'Loc(x=19, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X19Y34' at 'Loc(x=19, y=34)'
WARNING: No pin in tile at 'Loc(x=19, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X19Y34' at 'Loc(x=19, y=34)'
WARNING: No pin in tile at 'Loc(x=20, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X20Y34' at 'Loc(x=20, y=34)'
WARNING: No pin in tile at 'Loc(x=20, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X20Y34' at 'Loc(x=20, y=34)'
WARNING: No pin in tile at 'Loc(x=20, y=34)' found for switchbox pin 'CONCAT_EN_0' of 'SB_BOTTOM_IFC_X20Y34' at 'Loc(x=20, y=34)'
WARNING: No pin in tile at 'Loc(x=20, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X20Y34' at 'Loc(x=20, y=34)'
WARNING: No pin in tile at 'Loc(x=20, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X20Y34' at 'Loc(x=20, y=34)'
WARNING: No pin in tile at 'Loc(x=21, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X21Y34' at 'Loc(x=21, y=34)'
WARNING: No pin in tile at 'Loc(x=21, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X21Y34' at 'Loc(x=21, y=34)'
WARNING: No pin in tile at 'Loc(x=21, y=34)' found for switchbox pin 'WIDTH_SELECT1_0[0]' of 'SB_BOTTOM_IFC_X21Y34' at 'Loc(x=21, y=34)'
WARNING: No pin in tile at 'Loc(x=21, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X21Y34' at 'Loc(x=21, y=34)'
WARNING: No pin in tile at 'Loc(x=21, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X21Y34' at 'Loc(x=21, y=34)'
WARNING: No pin in tile at 'Loc(x=22, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X22Y34' at 'Loc(x=22, y=34)'
WARNING: No pin in tile at 'Loc(x=22, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X22Y34' at 'Loc(x=22, y=34)'
WARNING: No pin in tile at 'Loc(x=22, y=34)' found for switchbox pin 'WIDTH_SELECT1_0[1]' of 'SB_BOTTOM_IFC_X22Y34' at 'Loc(x=22, y=34)'
WARNING: No pin in tile at 'Loc(x=22, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X22Y34' at 'Loc(x=22, y=34)'
WARNING: No pin in tile at 'Loc(x=22, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X22Y34' at 'Loc(x=22, y=34)'
WARNING: No pin in tile at 'Loc(x=23, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X23Y34' at 'Loc(x=23, y=34)'
WARNING: No pin in tile at 'Loc(x=23, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X23Y34' at 'Loc(x=23, y=34)'
WARNING: No pin in tile at 'Loc(x=23, y=34)' found for switchbox pin 'WIDTH_SELECT2_0[0]' of 'SB_BOTTOM_IFC_X23Y34' at 'Loc(x=23, y=34)'
WARNING: No pin in tile at 'Loc(x=23, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X23Y34' at 'Loc(x=23, y=34)'
WARNING: No pin in tile at 'Loc(x=23, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X23Y34' at 'Loc(x=23, y=34)'
WARNING: No pin in tile at 'Loc(x=24, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X24Y34' at 'Loc(x=24, y=34)'
WARNING: No pin in tile at 'Loc(x=24, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X24Y34' at 'Loc(x=24, y=34)'
WARNING: No pin in tile at 'Loc(x=24, y=34)' found for switchbox pin 'WIDTH_SELECT2_0[1]' of 'SB_BOTTOM_IFC_X24Y34' at 'Loc(x=24, y=34)'
WARNING: No pin in tile at 'Loc(x=24, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X24Y34' at 'Loc(x=24, y=34)'
WARNING: No pin in tile at 'Loc(x=24, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X24Y34' at 'Loc(x=24, y=34)'
WARNING: No pin in tile at 'Loc(x=25, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X25Y34' at 'Loc(x=25, y=34)'
WARNING: No pin in tile at 'Loc(x=25, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X25Y34' at 'Loc(x=25, y=34)'
WARNING: No pin in tile at 'Loc(x=25, y=34)' found for switchbox pin 'FIFO_EN_1' of 'SB_BOTTOM_IFC_X25Y34' at 'Loc(x=25, y=34)'
WARNING: No pin in tile at 'Loc(x=25, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X25Y34' at 'Loc(x=25, y=34)'
WARNING: No pin in tile at 'Loc(x=25, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X25Y34' at 'Loc(x=25, y=34)'
WARNING: No pin in tile at 'Loc(x=26, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X26Y34' at 'Loc(x=26, y=34)'
WARNING: No pin in tile at 'Loc(x=26, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X26Y34' at 'Loc(x=26, y=34)'
WARNING: No pin in tile at 'Loc(x=26, y=34)' found for switchbox pin 'SYNC_FIFO_1' of 'SB_BOTTOM_IFC_X26Y34' at 'Loc(x=26, y=34)'
WARNING: No pin in tile at 'Loc(x=26, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X26Y34' at 'Loc(x=26, y=34)'
WARNING: No pin in tile at 'Loc(x=26, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X26Y34' at 'Loc(x=26, y=34)'
WARNING: No pin in tile at 'Loc(x=27, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X27Y34' at 'Loc(x=27, y=34)'
WARNING: No pin in tile at 'Loc(x=27, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X27Y34' at 'Loc(x=27, y=34)'
WARNING: No pin in tile at 'Loc(x=27, y=34)' found for switchbox pin 'PIPELINE_RD_1' of 'SB_BOTTOM_IFC_X27Y34' at 'Loc(x=27, y=34)'
WARNING: No pin in tile at 'Loc(x=27, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X27Y34' at 'Loc(x=27, y=34)'
WARNING: No pin in tile at 'Loc(x=27, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X27Y34' at 'Loc(x=27, y=34)'
WARNING: No pin in tile at 'Loc(x=28, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X28Y34' at 'Loc(x=28, y=34)'
WARNING: No pin in tile at 'Loc(x=28, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X28Y34' at 'Loc(x=28, y=34)'
WARNING: No pin in tile at 'Loc(x=28, y=34)' found for switchbox pin 'CONCAT_EN_1' of 'SB_BOTTOM_IFC_X28Y34' at 'Loc(x=28, y=34)'
WARNING: No pin in tile at 'Loc(x=28, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X28Y34' at 'Loc(x=28, y=34)'
WARNING: No pin in tile at 'Loc(x=28, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X28Y34' at 'Loc(x=28, y=34)'
WARNING: No pin in tile at 'Loc(x=29, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X29Y34' at 'Loc(x=29, y=34)'
WARNING: No pin in tile at 'Loc(x=29, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X29Y34' at 'Loc(x=29, y=34)'
WARNING: No pin in tile at 'Loc(x=29, y=34)' found for switchbox pin 'WIDTH_SELECT1_1[0]' of 'SB_BOTTOM_IFC_X29Y34' at 'Loc(x=29, y=34)'
WARNING: No pin in tile at 'Loc(x=29, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X29Y34' at 'Loc(x=29, y=34)'
WARNING: No pin in tile at 'Loc(x=29, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X29Y34' at 'Loc(x=29, y=34)'
WARNING: No pin in tile at 'Loc(x=30, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X30Y34' at 'Loc(x=30, y=34)'
WARNING: No pin in tile at 'Loc(x=30, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X30Y34' at 'Loc(x=30, y=34)'
WARNING: No pin in tile at 'Loc(x=30, y=34)' found for switchbox pin 'WIDTH_SELECT1_1[1]' of 'SB_BOTTOM_IFC_X30Y34' at 'Loc(x=30, y=34)'
WARNING: No pin in tile at 'Loc(x=30, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X30Y34' at 'Loc(x=30, y=34)'
WARNING: No pin in tile at 'Loc(x=30, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X30Y34' at 'Loc(x=30, y=34)'
WARNING: No pin in tile at 'Loc(x=31, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X31Y34' at 'Loc(x=31, y=34)'
WARNING: No pin in tile at 'Loc(x=31, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X31Y34' at 'Loc(x=31, y=34)'
WARNING: No pin in tile at 'Loc(x=31, y=34)' found for switchbox pin 'WIDTH_SELECT2_1[0]' of 'SB_BOTTOM_IFC_X31Y34' at 'Loc(x=31, y=34)'
WARNING: No pin in tile at 'Loc(x=31, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X31Y34' at 'Loc(x=31, y=34)'
WARNING: No pin in tile at 'Loc(x=31, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X31Y34' at 'Loc(x=31, y=34)'
WARNING: No pin in tile at 'Loc(x=32, y=34)' found for switchbox pin 'A2F_hop_b_io_2' of 'SB_BOTTOM_IFC_X32Y34' at 'Loc(x=32, y=34)'
WARNING: No pin in tile at 'Loc(x=32, y=34)' found for switchbox pin 'A2F_hop_b_io_1' of 'SB_BOTTOM_IFC_X32Y34' at 'Loc(x=32, y=34)'
WARNING: No pin in tile at 'Loc(x=32, y=34)' found for switchbox pin 'WIDTH_SELECT2_1[1]' of 'SB_BOTTOM_IFC_X32Y34' at 'Loc(x=32, y=34)'
WARNING: No pin in tile at 'Loc(x=32, y=34)' found for switchbox pin 'WPD' of 'SB_BOTTOM_IFC_X32Y34' at 'Loc(x=32, y=34)'
WARNING: No pin in tile at 'Loc(x=32, y=34)' found for switchbox pin 'DS' of 'SB_BOTTOM_IFC_X32Y34' at 'Loc(x=32, y=34)'
WARNING: No pin in tile at 'Loc(x=0, y=4)' found for switchbox pin 'WPD' of 'SB_LEFT_IFC_X0Y4' at 'Loc(x=0, y=4)'
WARNING: No pin in tile at 'Loc(x=0, y=4)' found for switchbox pin 'DS' of 'SB_LEFT_IFC_X0Y4' at 'Loc(x=0, y=4)'
WARNING: No pin in tile at 'Loc(x=0, y=6)' found for switchbox pin 'WPD' of 'SB_LEFT_IFC_X0Y6' at 'Loc(x=0, y=6)'
WARNING: No pin in tile at 'Loc(x=0, y=6)' found for switchbox pin 'DS' of 'SB_LEFT_IFC_X0Y6' at 'Loc(x=0, y=6)'
WARNING: No pin in tile at 'Loc(x=0, y=11)' found for switchbox pin 'WPD' of 'SB_LEFT_IFC_X0Y11' at 'Loc(x=0, y=11)'
WARNING: No pin in tile at 'Loc(x=0, y=11)' found for switchbox pin 'DS' of 'SB_LEFT_IFC_X0Y11' at 'Loc(x=0, y=11)'
WARNING: No pin in tile at 'Loc(x=0, y=12)' found for switchbox pin 'WPD' of 'SB_LEFT_IFC_X0Y12' at 'Loc(x=0, y=12)'
WARNING: No pin in tile at 'Loc(x=0, y=12)' found for switchbox pin 'DS' of 'SB_LEFT_IFC_X0Y12' at 'Loc(x=0, y=12)'
WARNING: No pin in tile at 'Loc(x=0, y=13)' found for switchbox pin 'WPD' of 'SB_LEFT_IFC_X0Y13' at 'Loc(x=0, y=13)'
WARNING: No pin in tile at 'Loc(x=0, y=13)' found for switchbox pin 'DS' of 'SB_LEFT_IFC_X0Y13' at 'Loc(x=0, y=13)'
WARNING: No pin in tile at 'Loc(x=0, y=14)' found for switchbox pin 'WPD' of 'SB_LEFT_IFC_X0Y14' at 'Loc(x=0, y=14)'
WARNING: No pin in tile at 'Loc(x=0, y=14)' found for switchbox pin 'DS' of 'SB_LEFT_IFC_X0Y14' at 'Loc(x=0, y=14)'
WARNING: No pin in tile at 'Loc(x=0, y=19)' found for switchbox pin 'WPD' of 'SB_LEFT_IFC_X0Y19' at 'Loc(x=0, y=19)'
WARNING: No pin in tile at 'Loc(x=0, y=19)' found for switchbox pin 'DS' of 'SB_LEFT_IFC_X0Y19' at 'Loc(x=0, y=19)'
WARNING: No pin in tile at 'Loc(x=0, y=21)' found for switchbox pin 'WPD' of 'SB_LEFT_IFC_X0Y21' at 'Loc(x=0, y=21)'
WARNING: No pin in tile at 'Loc(x=0, y=21)' found for switchbox pin 'DS' of 'SB_LEFT_IFC_X0Y21' at 'Loc(x=0, y=21)'
WARNING: No pin in tile at 'Loc(x=0, y=24)' found for switchbox pin 'WPD' of 'SB_LEFT_IFC_X0Y24' at 'Loc(x=0, y=24)'
WARNING: No pin in tile at 'Loc(x=0, y=24)' found for switchbox pin 'DS' of 'SB_LEFT_IFC_X0Y24' at 'Loc(x=0, y=24)'
WARNING: No pin in tile at 'Loc(x=0, y=26)' found for switchbox pin 'WPD' of 'SB_LEFT_IFC_X0Y26' at 'Loc(x=0, y=26)'
WARNING: No pin in tile at 'Loc(x=0, y=26)' found for switchbox pin 'DS' of 'SB_LEFT_IFC_X0Y26' at 'Loc(x=0, y=26)'
WARNING: No pin in tile at 'Loc(x=0, y=29)' found for switchbox pin 'WPD' of 'SB_LEFT_IFC_X0Y29' at 'Loc(x=0, y=29)'
WARNING: No pin in tile at 'Loc(x=0, y=29)' found for switchbox pin 'DS' of 'SB_LEFT_IFC_X0Y29' at 'Loc(x=0, y=29)'
WARNING: No pin in tile at 'Loc(x=33, y=2)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y2' at 'Loc(x=33, y=2)'
WARNING: No pin in tile at 'Loc(x=33, y=2)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y2' at 'Loc(x=33, y=2)'
WARNING: No pin in tile at 'Loc(x=33, y=2)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y2' at 'Loc(x=33, y=2)'
WARNING: No pin in tile at 'Loc(x=33, y=2)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y2' at 'Loc(x=33, y=2)'
WARNING: No pin in tile at 'Loc(x=33, y=3)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y3' at 'Loc(x=33, y=3)'
WARNING: No pin in tile at 'Loc(x=33, y=3)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y3' at 'Loc(x=33, y=3)'
WARNING: No pin in tile at 'Loc(x=33, y=3)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y3' at 'Loc(x=33, y=3)'
WARNING: No pin in tile at 'Loc(x=33, y=3)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y3' at 'Loc(x=33, y=3)'
WARNING: No pin in tile at 'Loc(x=33, y=3)' found for switchbox pin 'WPD' of 'SB_RIGHT_IFC_X33Y3' at 'Loc(x=33, y=3)'
WARNING: No pin in tile at 'Loc(x=33, y=3)' found for switchbox pin 'DS' of 'SB_RIGHT_IFC_X33Y3' at 'Loc(x=33, y=3)'
WARNING: No pin in tile at 'Loc(x=33, y=4)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y4' at 'Loc(x=33, y=4)'
WARNING: No pin in tile at 'Loc(x=33, y=4)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y4' at 'Loc(x=33, y=4)'
WARNING: No pin in tile at 'Loc(x=33, y=4)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y4' at 'Loc(x=33, y=4)'
WARNING: No pin in tile at 'Loc(x=33, y=4)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y4' at 'Loc(x=33, y=4)'
WARNING: No pin in tile at 'Loc(x=33, y=5)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y5' at 'Loc(x=33, y=5)'
WARNING: No pin in tile at 'Loc(x=33, y=5)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y5' at 'Loc(x=33, y=5)'
WARNING: No pin in tile at 'Loc(x=33, y=5)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y5' at 'Loc(x=33, y=5)'
WARNING: No pin in tile at 'Loc(x=33, y=5)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y5' at 'Loc(x=33, y=5)'
WARNING: No pin in tile at 'Loc(x=33, y=5)' found for switchbox pin 'WPD' of 'SB_RIGHT_IFC_X33Y5' at 'Loc(x=33, y=5)'
WARNING: No pin in tile at 'Loc(x=33, y=5)' found for switchbox pin 'DS' of 'SB_RIGHT_IFC_X33Y5' at 'Loc(x=33, y=5)'
WARNING: No pin in tile at 'Loc(x=33, y=6)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y6' at 'Loc(x=33, y=6)'
WARNING: No pin in tile at 'Loc(x=33, y=6)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y6' at 'Loc(x=33, y=6)'
WARNING: No pin in tile at 'Loc(x=33, y=6)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y6' at 'Loc(x=33, y=6)'
WARNING: No pin in tile at 'Loc(x=33, y=6)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y6' at 'Loc(x=33, y=6)'
WARNING: No pin in tile at 'Loc(x=33, y=7)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y7' at 'Loc(x=33, y=7)'
WARNING: No pin in tile at 'Loc(x=33, y=7)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y7' at 'Loc(x=33, y=7)'
WARNING: No pin in tile at 'Loc(x=33, y=7)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y7' at 'Loc(x=33, y=7)'
WARNING: No pin in tile at 'Loc(x=33, y=7)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y7' at 'Loc(x=33, y=7)'
WARNING: No pin in tile at 'Loc(x=33, y=8)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y8' at 'Loc(x=33, y=8)'
WARNING: No pin in tile at 'Loc(x=33, y=8)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y8' at 'Loc(x=33, y=8)'
WARNING: No pin in tile at 'Loc(x=33, y=8)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y8' at 'Loc(x=33, y=8)'
WARNING: No pin in tile at 'Loc(x=33, y=8)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y8' at 'Loc(x=33, y=8)'
WARNING: No pin in tile at 'Loc(x=33, y=8)' found for switchbox pin 'WPD' of 'SB_RIGHT_IFC_X33Y8' at 'Loc(x=33, y=8)'
WARNING: No pin in tile at 'Loc(x=33, y=8)' found for switchbox pin 'DS' of 'SB_RIGHT_IFC_X33Y8' at 'Loc(x=33, y=8)'
WARNING: No pin in tile at 'Loc(x=33, y=9)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y9' at 'Loc(x=33, y=9)'
WARNING: No pin in tile at 'Loc(x=33, y=9)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y9' at 'Loc(x=33, y=9)'
WARNING: No pin in tile at 'Loc(x=33, y=9)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y9' at 'Loc(x=33, y=9)'
WARNING: No pin in tile at 'Loc(x=33, y=9)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y9' at 'Loc(x=33, y=9)'
WARNING: No pin in tile at 'Loc(x=33, y=10)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y10' at 'Loc(x=33, y=10)'
WARNING: No pin in tile at 'Loc(x=33, y=10)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y10' at 'Loc(x=33, y=10)'
WARNING: No pin in tile at 'Loc(x=33, y=10)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y10' at 'Loc(x=33, y=10)'
WARNING: No pin in tile at 'Loc(x=33, y=10)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y10' at 'Loc(x=33, y=10)'
WARNING: No pin in tile at 'Loc(x=33, y=10)' found for switchbox pin 'WPD' of 'SB_RIGHT_IFC_X33Y10' at 'Loc(x=33, y=10)'
WARNING: No pin in tile at 'Loc(x=33, y=10)' found for switchbox pin 'DS' of 'SB_RIGHT_IFC_X33Y10' at 'Loc(x=33, y=10)'
WARNING: No pin in tile at 'Loc(x=33, y=11)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y11' at 'Loc(x=33, y=11)'
WARNING: No pin in tile at 'Loc(x=33, y=11)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y11' at 'Loc(x=33, y=11)'
WARNING: No pin in tile at 'Loc(x=33, y=11)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y11' at 'Loc(x=33, y=11)'
WARNING: No pin in tile at 'Loc(x=33, y=11)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y11' at 'Loc(x=33, y=11)'
WARNING: No pin in tile at 'Loc(x=33, y=12)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y12' at 'Loc(x=33, y=12)'
WARNING: No pin in tile at 'Loc(x=33, y=12)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y12' at 'Loc(x=33, y=12)'
WARNING: No pin in tile at 'Loc(x=33, y=12)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y12' at 'Loc(x=33, y=12)'
WARNING: No pin in tile at 'Loc(x=33, y=12)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y12' at 'Loc(x=33, y=12)'
WARNING: No pin in tile at 'Loc(x=33, y=13)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y13' at 'Loc(x=33, y=13)'
WARNING: No pin in tile at 'Loc(x=33, y=13)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y13' at 'Loc(x=33, y=13)'
WARNING: No pin in tile at 'Loc(x=33, y=13)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y13' at 'Loc(x=33, y=13)'
WARNING: No pin in tile at 'Loc(x=33, y=13)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y13' at 'Loc(x=33, y=13)'
WARNING: No pin in tile at 'Loc(x=33, y=14)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y14' at 'Loc(x=33, y=14)'
WARNING: No pin in tile at 'Loc(x=33, y=14)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y14' at 'Loc(x=33, y=14)'
WARNING: No pin in tile at 'Loc(x=33, y=14)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y14' at 'Loc(x=33, y=14)'
WARNING: No pin in tile at 'Loc(x=33, y=14)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y14' at 'Loc(x=33, y=14)'
WARNING: No pin in tile at 'Loc(x=33, y=15)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y15' at 'Loc(x=33, y=15)'
WARNING: No pin in tile at 'Loc(x=33, y=15)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y15' at 'Loc(x=33, y=15)'
WARNING: No pin in tile at 'Loc(x=33, y=15)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y15' at 'Loc(x=33, y=15)'
WARNING: No pin in tile at 'Loc(x=33, y=15)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y15' at 'Loc(x=33, y=15)'
WARNING: No pin in tile at 'Loc(x=33, y=16)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y16' at 'Loc(x=33, y=16)'
WARNING: No pin in tile at 'Loc(x=33, y=16)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y16' at 'Loc(x=33, y=16)'
WARNING: No pin in tile at 'Loc(x=33, y=16)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y16' at 'Loc(x=33, y=16)'
WARNING: No pin in tile at 'Loc(x=33, y=16)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y16' at 'Loc(x=33, y=16)'
WARNING: No pin in tile at 'Loc(x=33, y=16)' found for switchbox pin 'WPD' of 'SB_RIGHT_IFC_X33Y16' at 'Loc(x=33, y=16)'
WARNING: No pin in tile at 'Loc(x=33, y=16)' found for switchbox pin 'DS' of 'SB_RIGHT_IFC_X33Y16' at 'Loc(x=33, y=16)'
WARNING: No pin in tile at 'Loc(x=33, y=17)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y17' at 'Loc(x=33, y=17)'
WARNING: No pin in tile at 'Loc(x=33, y=17)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y17' at 'Loc(x=33, y=17)'
WARNING: No pin in tile at 'Loc(x=33, y=17)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y17' at 'Loc(x=33, y=17)'
WARNING: No pin in tile at 'Loc(x=33, y=17)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y17' at 'Loc(x=33, y=17)'
WARNING: No pin in tile at 'Loc(x=33, y=17)' found for switchbox pin 'WPD' of 'SB_RIGHT_IFC_X33Y17' at 'Loc(x=33, y=17)'
WARNING: No pin in tile at 'Loc(x=33, y=17)' found for switchbox pin 'DS' of 'SB_RIGHT_IFC_X33Y17' at 'Loc(x=33, y=17)'
WARNING: No pin in tile at 'Loc(x=33, y=18)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y18' at 'Loc(x=33, y=18)'
WARNING: No pin in tile at 'Loc(x=33, y=18)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y18' at 'Loc(x=33, y=18)'
WARNING: No pin in tile at 'Loc(x=33, y=18)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y18' at 'Loc(x=33, y=18)'
WARNING: No pin in tile at 'Loc(x=33, y=18)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y18' at 'Loc(x=33, y=18)'
WARNING: No pin in tile at 'Loc(x=33, y=18)' found for switchbox pin 'WPD' of 'SB_RIGHT_IFC_X33Y18' at 'Loc(x=33, y=18)'
WARNING: No pin in tile at 'Loc(x=33, y=18)' found for switchbox pin 'DS' of 'SB_RIGHT_IFC_X33Y18' at 'Loc(x=33, y=18)'
WARNING: No pin in tile at 'Loc(x=33, y=19)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y19' at 'Loc(x=33, y=19)'
WARNING: No pin in tile at 'Loc(x=33, y=19)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y19' at 'Loc(x=33, y=19)'
WARNING: No pin in tile at 'Loc(x=33, y=19)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y19' at 'Loc(x=33, y=19)'
WARNING: No pin in tile at 'Loc(x=33, y=19)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y19' at 'Loc(x=33, y=19)'
WARNING: No pin in tile at 'Loc(x=33, y=19)' found for switchbox pin 'WPD' of 'SB_RIGHT_IFC_X33Y19' at 'Loc(x=33, y=19)'
WARNING: No pin in tile at 'Loc(x=33, y=19)' found for switchbox pin 'DS' of 'SB_RIGHT_IFC_X33Y19' at 'Loc(x=33, y=19)'
WARNING: No pin in tile at 'Loc(x=33, y=20)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y20' at 'Loc(x=33, y=20)'
WARNING: No pin in tile at 'Loc(x=33, y=20)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y20' at 'Loc(x=33, y=20)'
WARNING: No pin in tile at 'Loc(x=33, y=20)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y20' at 'Loc(x=33, y=20)'
WARNING: No pin in tile at 'Loc(x=33, y=20)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y20' at 'Loc(x=33, y=20)'
WARNING: No pin in tile at 'Loc(x=33, y=20)' found for switchbox pin 'WPD' of 'SB_RIGHT_IFC_X33Y20' at 'Loc(x=33, y=20)'
WARNING: No pin in tile at 'Loc(x=33, y=20)' found for switchbox pin 'DS' of 'SB_RIGHT_IFC_X33Y20' at 'Loc(x=33, y=20)'
WARNING: No pin in tile at 'Loc(x=33, y=21)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y21' at 'Loc(x=33, y=21)'
WARNING: No pin in tile at 'Loc(x=33, y=21)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y21' at 'Loc(x=33, y=21)'
WARNING: No pin in tile at 'Loc(x=33, y=21)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y21' at 'Loc(x=33, y=21)'
WARNING: No pin in tile at 'Loc(x=33, y=21)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y21' at 'Loc(x=33, y=21)'
WARNING: No pin in tile at 'Loc(x=33, y=22)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y22' at 'Loc(x=33, y=22)'
WARNING: No pin in tile at 'Loc(x=33, y=22)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y22' at 'Loc(x=33, y=22)'
WARNING: No pin in tile at 'Loc(x=33, y=22)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y22' at 'Loc(x=33, y=22)'
WARNING: No pin in tile at 'Loc(x=33, y=22)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y22' at 'Loc(x=33, y=22)'
WARNING: No pin in tile at 'Loc(x=33, y=23)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y23' at 'Loc(x=33, y=23)'
WARNING: No pin in tile at 'Loc(x=33, y=23)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y23' at 'Loc(x=33, y=23)'
WARNING: No pin in tile at 'Loc(x=33, y=23)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y23' at 'Loc(x=33, y=23)'
WARNING: No pin in tile at 'Loc(x=33, y=23)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y23' at 'Loc(x=33, y=23)'
WARNING: No pin in tile at 'Loc(x=33, y=23)' found for switchbox pin 'WPD' of 'SB_RIGHT_IFC_X33Y23' at 'Loc(x=33, y=23)'
WARNING: No pin in tile at 'Loc(x=33, y=23)' found for switchbox pin 'DS' of 'SB_RIGHT_IFC_X33Y23' at 'Loc(x=33, y=23)'
WARNING: No pin in tile at 'Loc(x=33, y=24)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y24' at 'Loc(x=33, y=24)'
WARNING: No pin in tile at 'Loc(x=33, y=24)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y24' at 'Loc(x=33, y=24)'
WARNING: No pin in tile at 'Loc(x=33, y=24)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y24' at 'Loc(x=33, y=24)'
WARNING: No pin in tile at 'Loc(x=33, y=24)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y24' at 'Loc(x=33, y=24)'
WARNING: No pin in tile at 'Loc(x=33, y=25)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y25' at 'Loc(x=33, y=25)'
WARNING: No pin in tile at 'Loc(x=33, y=25)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y25' at 'Loc(x=33, y=25)'
WARNING: No pin in tile at 'Loc(x=33, y=25)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y25' at 'Loc(x=33, y=25)'
WARNING: No pin in tile at 'Loc(x=33, y=25)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y25' at 'Loc(x=33, y=25)'
WARNING: No pin in tile at 'Loc(x=33, y=26)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y26' at 'Loc(x=33, y=26)'
WARNING: No pin in tile at 'Loc(x=33, y=26)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y26' at 'Loc(x=33, y=26)'
WARNING: No pin in tile at 'Loc(x=33, y=26)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y26' at 'Loc(x=33, y=26)'
WARNING: No pin in tile at 'Loc(x=33, y=26)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y26' at 'Loc(x=33, y=26)'
WARNING: No pin in tile at 'Loc(x=33, y=26)' found for switchbox pin 'WPD' of 'SB_RIGHT_IFC_X33Y26' at 'Loc(x=33, y=26)'
WARNING: No pin in tile at 'Loc(x=33, y=26)' found for switchbox pin 'DS' of 'SB_RIGHT_IFC_X33Y26' at 'Loc(x=33, y=26)'
WARNING: No pin in tile at 'Loc(x=33, y=27)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y27' at 'Loc(x=33, y=27)'
WARNING: No pin in tile at 'Loc(x=33, y=27)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y27' at 'Loc(x=33, y=27)'
WARNING: No pin in tile at 'Loc(x=33, y=27)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y27' at 'Loc(x=33, y=27)'
WARNING: No pin in tile at 'Loc(x=33, y=27)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y27' at 'Loc(x=33, y=27)'
WARNING: No pin in tile at 'Loc(x=33, y=27)' found for switchbox pin 'RAM3_P0_WR_BE[0]' of 'SB_RIGHT_IFC_X33Y27' at 'Loc(x=33, y=27)'
WARNING: No pin in tile at 'Loc(x=33, y=28)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y28' at 'Loc(x=33, y=28)'
WARNING: No pin in tile at 'Loc(x=33, y=28)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y28' at 'Loc(x=33, y=28)'
WARNING: No pin in tile at 'Loc(x=33, y=28)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y28' at 'Loc(x=33, y=28)'
WARNING: No pin in tile at 'Loc(x=33, y=28)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y28' at 'Loc(x=33, y=28)'
WARNING: No pin in tile at 'Loc(x=33, y=28)' found for switchbox pin 'WPD' of 'SB_RIGHT_IFC_X33Y28' at 'Loc(x=33, y=28)'
WARNING: No pin in tile at 'Loc(x=33, y=28)' found for switchbox pin 'DS' of 'SB_RIGHT_IFC_X33Y28' at 'Loc(x=33, y=28)'
WARNING: No pin in tile at 'Loc(x=33, y=29)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y29' at 'Loc(x=33, y=29)'
WARNING: No pin in tile at 'Loc(x=33, y=29)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y29' at 'Loc(x=33, y=29)'
WARNING: No pin in tile at 'Loc(x=33, y=29)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y29' at 'Loc(x=33, y=29)'
WARNING: No pin in tile at 'Loc(x=33, y=29)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y29' at 'Loc(x=33, y=29)'
WARNING: No pin in tile at 'Loc(x=33, y=29)' found for switchbox pin 'RAM3_P0_WR_BE[1]' of 'SB_RIGHT_IFC_X33Y29' at 'Loc(x=33, y=29)'
WARNING: No pin in tile at 'Loc(x=33, y=30)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y30' at 'Loc(x=33, y=30)'
WARNING: No pin in tile at 'Loc(x=33, y=30)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y30' at 'Loc(x=33, y=30)'
WARNING: No pin in tile at 'Loc(x=33, y=30)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y30' at 'Loc(x=33, y=30)'
WARNING: No pin in tile at 'Loc(x=33, y=30)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y30' at 'Loc(x=33, y=30)'
WARNING: No pin in tile at 'Loc(x=33, y=31)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y31' at 'Loc(x=33, y=31)'
WARNING: No pin in tile at 'Loc(x=33, y=31)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y31' at 'Loc(x=33, y=31)'
WARNING: No pin in tile at 'Loc(x=33, y=31)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y31' at 'Loc(x=33, y=31)'
WARNING: No pin in tile at 'Loc(x=33, y=31)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y31' at 'Loc(x=33, y=31)'
WARNING: No pin in tile at 'Loc(x=33, y=31)' found for switchbox pin 'WPD' of 'SB_RIGHT_IFC_X33Y31' at 'Loc(x=33, y=31)'
WARNING: No pin in tile at 'Loc(x=33, y=31)' found for switchbox pin 'DS' of 'SB_RIGHT_IFC_X33Y31' at 'Loc(x=33, y=31)'
WARNING: No pin in tile at 'Loc(x=33, y=32)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y32' at 'Loc(x=33, y=32)'
WARNING: No pin in tile at 'Loc(x=33, y=32)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y32' at 'Loc(x=33, y=32)'
WARNING: No pin in tile at 'Loc(x=33, y=32)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y32' at 'Loc(x=33, y=32)'
WARNING: No pin in tile at 'Loc(x=33, y=32)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y32' at 'Loc(x=33, y=32)'
WARNING: No pin in tile at 'Loc(x=33, y=32)' found for switchbox pin 'RAM3_P0_WR_BE[2]' of 'SB_RIGHT_IFC_X33Y32' at 'Loc(x=33, y=32)'
WARNING: No pin in tile at 'Loc(x=33, y=33)' found for switchbox pin 'A2F_HW_r_3' of 'SB_RIGHT_IFC_X33Y33' at 'Loc(x=33, y=33)'
WARNING: No pin in tile at 'Loc(x=33, y=33)' found for switchbox pin 'A2F_HW_r_1' of 'SB_RIGHT_IFC_X33Y33' at 'Loc(x=33, y=33)'
WARNING: No pin in tile at 'Loc(x=33, y=33)' found for switchbox pin 'A2F_HW_r_0' of 'SB_RIGHT_IFC_X33Y33' at 'Loc(x=33, y=33)'
WARNING: No pin in tile at 'Loc(x=33, y=33)' found for switchbox pin 'A2F_HW_r_2' of 'SB_RIGHT_IFC_X33Y33' at 'Loc(x=33, y=33)'
WARNING: No pin in tile at 'Loc(x=33, y=33)' found for switchbox pin 'RAM3_P0_WR_BE[3]' of 'SB_RIGHT_IFC_X33Y33' at 'Loc(x=33, y=33)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'H1R0_L1' of switchbox 'SB_TOP_IFC_X1Y1' at 'Loc(x=1, y=1)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'H1R2_L1' of switchbox 'SB_TOP_IFC_X1Y1' at 'Loc(x=1, y=1)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'H1R3_L1' of switchbox 'SB_TOP_IFC_X1Y1' at 'Loc(x=1, y=1)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'H1R1_L1' of switchbox 'SB_TOP_IFC_X1Y1' at 'Loc(x=1, y=1)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'H2R1_L2' of switchbox 'SB_TOP_IFC_X2Y1' at 'Loc(x=2, y=1)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'H2R0_L2' of switchbox 'SB_TOP_IFC_X2Y1' at 'Loc(x=2, y=1)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'H4R0_L4' of switchbox 'SB_TOP_IFC_X4Y1' at 'Loc(x=4, y=1)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'H4L0_R4' of switchbox 'SB_TOP_IFC_X29Y1' at 'Loc(x=29, y=1)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'H4L1_R4' of switchbox 'SB_TOP_IFC_X29Y1' at 'Loc(x=29, y=1)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'H2L0_R2' of switchbox 'SB_TOP_IFC_X31Y1' at 'Loc(x=31, y=1)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'H1L0_R1' of switchbox 'SB_TOP_IFC_X32Y1' at 'Loc(x=32, y=1)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'H1L1_R1' of switchbox 'SB_TOP_IFC_X32Y1' at 'Loc(x=32, y=1)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'H1L2_R1' of switchbox 'SB_TOP_IFC_X32Y1' at 'Loc(x=32, y=1)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'H1L3_R1' of switchbox 'SB_TOP_IFC_X32Y1' at 'Loc(x=32, y=1)'
WARNING: No switchbox at 'Loc(x=0, y=34)' for input 'H1R0_L1' of switchbox 'SB_BOTTOM_IFC_X1Y34' at 'Loc(x=1, y=34)'
WARNING: No switchbox at 'Loc(x=0, y=34)' for input 'H1R2_L1' of switchbox 'SB_BOTTOM_IFC_X1Y34' at 'Loc(x=1, y=34)'
WARNING: No switchbox at 'Loc(x=0, y=34)' for input 'H1R3_L1' of switchbox 'SB_BOTTOM_IFC_X1Y34' at 'Loc(x=1, y=34)'
WARNING: No switchbox at 'Loc(x=0, y=34)' for input 'H1R1_L1' of switchbox 'SB_BOTTOM_IFC_X1Y34' at 'Loc(x=1, y=34)'
WARNING: No switchbox at 'Loc(x=0, y=34)' for input 'H2R1_L2' of switchbox 'SB_BOTTOM_IFC_X2Y34' at 'Loc(x=2, y=34)'
WARNING: No switchbox at 'Loc(x=0, y=34)' for input 'H2R0_L2' of switchbox 'SB_BOTTOM_IFC_X2Y34' at 'Loc(x=2, y=34)'
WARNING: No switchbox at 'Loc(x=0, y=34)' for input 'H4R0_L4' of switchbox 'SB_BOTTOM_IFC_X4Y34' at 'Loc(x=4, y=34)'
WARNING: No switchbox at 'Loc(x=33, y=34)' for input 'H4L0_R4' of switchbox 'SB_BOTTOM_IFC_X29Y34' at 'Loc(x=29, y=34)'
WARNING: No switchbox at 'Loc(x=33, y=34)' for input 'H4L1_R4' of switchbox 'SB_BOTTOM_IFC_X29Y34' at 'Loc(x=29, y=34)'
WARNING: No switchbox at 'Loc(x=33, y=34)' for input 'H2L0_R2' of switchbox 'SB_BOTTOM_IFC_X31Y34' at 'Loc(x=31, y=34)'
WARNING: No switchbox at 'Loc(x=33, y=34)' for input 'H1L0_R1' of switchbox 'SB_BOTTOM_IFC_X32Y34' at 'Loc(x=32, y=34)'
WARNING: No switchbox at 'Loc(x=33, y=34)' for input 'H1L1_R1' of switchbox 'SB_BOTTOM_IFC_X32Y34' at 'Loc(x=32, y=34)'
WARNING: No switchbox at 'Loc(x=33, y=34)' for input 'H1L2_R1' of switchbox 'SB_BOTTOM_IFC_X32Y34' at 'Loc(x=32, y=34)'
WARNING: No switchbox at 'Loc(x=33, y=34)' for input 'H1L3_R1' of switchbox 'SB_BOTTOM_IFC_X32Y34' at 'Loc(x=32, y=34)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'V1B3_T1' of switchbox 'SB_LEFT_IFC_X0Y2' at 'Loc(x=0, y=2)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'V1B1_T1' of switchbox 'SB_LEFT_IFC_X0Y2' at 'Loc(x=0, y=2)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'V1B2_T1' of switchbox 'SB_LEFT_IFC_X0Y2' at 'Loc(x=0, y=2)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'V1B0_T1' of switchbox 'SB_LEFT_IFC_X0Y2' at 'Loc(x=0, y=2)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'V2B0_T2' of switchbox 'SB_LEFT_IFC_X0Y3' at 'Loc(x=0, y=3)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'V4B0_T4' of switchbox 'SB_LEFT_IFC_X0Y5' at 'Loc(x=0, y=5)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'V4B1_T4' of switchbox 'SB_LEFT_IFC_X0Y5' at 'Loc(x=0, y=5)'
WARNING: No switchbox at 'Loc(x=0, y=34)' for input 'V4T0_B4' of switchbox 'SB_LEFT_IFC_X0Y30' at 'Loc(x=0, y=30)'
WARNING: No switchbox at 'Loc(x=0, y=34)' for input 'V2T0_B2' of switchbox 'SB_LEFT_IFC_X0Y32' at 'Loc(x=0, y=32)'
WARNING: No switchbox at 'Loc(x=0, y=34)' for input 'V2T1_B2' of switchbox 'SB_LEFT_IFC_X0Y32' at 'Loc(x=0, y=32)'
WARNING: No switchbox at 'Loc(x=0, y=34)' for input 'V1T2_B1' of switchbox 'SB_LEFT_IFC_X0Y33' at 'Loc(x=0, y=33)'
WARNING: No switchbox at 'Loc(x=0, y=34)' for input 'V1T1_B1' of switchbox 'SB_LEFT_IFC_X0Y33' at 'Loc(x=0, y=33)'
WARNING: No switchbox at 'Loc(x=0, y=34)' for input 'V1T0_B1' of switchbox 'SB_LEFT_IFC_X0Y33' at 'Loc(x=0, y=33)'
WARNING: No switchbox at 'Loc(x=0, y=34)' for input 'V1T3_B1' of switchbox 'SB_LEFT_IFC_X0Y33' at 'Loc(x=0, y=33)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'V1B3_T1' of switchbox 'SB_RIGHT_IFC_X33Y2' at 'Loc(x=33, y=2)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'V1B1_T1' of switchbox 'SB_RIGHT_IFC_X33Y2' at 'Loc(x=33, y=2)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'V1B2_T1' of switchbox 'SB_RIGHT_IFC_X33Y2' at 'Loc(x=33, y=2)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'V1B0_T1' of switchbox 'SB_RIGHT_IFC_X33Y2' at 'Loc(x=33, y=2)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'V2B0_T2' of switchbox 'SB_RIGHT_IFC_X33Y3' at 'Loc(x=33, y=3)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'V4B0_T4' of switchbox 'SB_RIGHT_IFC_X33Y5' at 'Loc(x=33, y=5)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'V4B1_T4' of switchbox 'SB_RIGHT_IFC_X33Y5' at 'Loc(x=33, y=5)'
WARNING: No switchbox at 'Loc(x=33, y=34)' for input 'V4T0_B4' of switchbox 'SB_RIGHT_IFC_X33Y30' at 'Loc(x=33, y=30)'
WARNING: No switchbox at 'Loc(x=33, y=34)' for input 'V2T0_B2' of switchbox 'SB_RIGHT_IFC_X33Y32' at 'Loc(x=33, y=32)'
WARNING: No switchbox at 'Loc(x=33, y=34)' for input 'V2T1_B2' of switchbox 'SB_RIGHT_IFC_X33Y32' at 'Loc(x=33, y=32)'
WARNING: No switchbox at 'Loc(x=33, y=34)' for input 'V1T2_B1' of switchbox 'SB_RIGHT_IFC_X33Y33' at 'Loc(x=33, y=33)'
WARNING: No switchbox at 'Loc(x=33, y=34)' for input 'V1T1_B1' of switchbox 'SB_RIGHT_IFC_X33Y33' at 'Loc(x=33, y=33)'
WARNING: No switchbox at 'Loc(x=33, y=34)' for input 'V1T0_B1' of switchbox 'SB_RIGHT_IFC_X33Y33' at 'Loc(x=33, y=33)'
WARNING: No switchbox at 'Loc(x=33, y=34)' for input 'V1T3_B1' of switchbox 'SB_RIGHT_IFC_X33Y33' at 'Loc(x=33, y=33)'
[  0%] Generating db_vpr.pickle
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-pp3e-virt && /opt/openfpga/vtr/_pyenv/bin/python3 /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/prepare_vpr_database.py --phy-db db_phy.pickle --vpr-db db_vpr.pickle
Processing timing data...
WARNING: For 'SB_LC (3, 1, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 4, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 6, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 8, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 11, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 13, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 14, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 15, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 18, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 20, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 21, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 22, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 25, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 27, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: Error of the timing model of 'SB_LC (3, 1, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.384    | 0.439    | -0.055   |
| 2       | 0.388    | 0.439    | -0.051   |
| 3       | 0.393    | 0.439    | -0.046   |
| 4       | 0.397    | 0.439    | -0.042   |
| 5       | 0.401    | 0.439    | -0.038   |
| 6       | 0.406    | 0.439    | -0.033   |
| 7       | 0.411    | 0.439    | -0.028   |
| 8       | 0.414    | 0.439    | -0.025   |
| 9       | 0.419    | 0.439    | -0.020   |
| 10      | 0.423    | 0.439    | -0.015   |
| 11      | 0.428    | 0.439    | -0.011   |
| 12      | 0.432    | 0.439    | -0.007   |
| 13      | 0.436    | 0.439    | -0.002   |
| 14      | 0.025    | 0.439    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 4, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 6, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 8, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.384    | 0.439    | -0.055   |
| 2       | 0.388    | 0.439    | -0.051   |
| 3       | 0.393    | 0.439    | -0.046   |
| 4       | 0.397    | 0.439    | -0.042   |
| 5       | 0.401    | 0.439    | -0.038   |
| 6       | 0.406    | 0.439    | -0.033   |
| 7       | 0.411    | 0.439    | -0.028   |
| 8       | 0.414    | 0.439    | -0.025   |
| 9       | 0.419    | 0.439    | -0.020   |
| 10      | 0.423    | 0.439    | -0.015   |
| 11      | 0.428    | 0.439    | -0.011   |
| 12      | 0.432    | 0.439    | -0.007   |
| 13      | 0.436    | 0.439    | -0.002   |
| 14      | 0.025    | 0.439    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 11, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 13, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 14, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.404    | 0.459    | -0.055   |
| 2       | 0.408    | 0.459    | -0.051   |
| 3       | 0.413    | 0.459    | -0.046   |
| 4       | 0.416    | 0.459    | -0.042   |
| 5       | 0.421    | 0.459    | -0.038   |
| 6       | 0.426    | 0.459    | -0.033   |
| 7       | 0.430    | 0.459    | -0.028   |
| 8       | 0.434    | 0.459    | -0.025   |
| 9       | 0.439    | 0.459    | -0.020   |
| 10      | 0.443    | 0.459    | -0.015   |
| 11      | 0.448    | 0.459    | -0.011   |
| 12      | 0.452    | 0.459    | -0.007   |
| 13      | 0.456    | 0.459    | -0.002   |
| 14      | 0.045    | 0.459    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 15, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.404    | 0.459    | -0.055   |
| 2       | 0.408    | 0.459    | -0.051   |
| 3       | 0.413    | 0.459    | -0.046   |
| 4       | 0.416    | 0.459    | -0.042   |
| 5       | 0.421    | 0.459    | -0.038   |
| 6       | 0.426    | 0.459    | -0.033   |
| 7       | 0.430    | 0.459    | -0.028   |
| 8       | 0.434    | 0.459    | -0.025   |
| 9       | 0.439    | 0.459    | -0.020   |
| 10      | 0.443    | 0.459    | -0.015   |
| 11      | 0.448    | 0.459    | -0.011   |
| 12      | 0.452    | 0.459    | -0.007   |
| 13      | 0.456    | 0.459    | -0.002   |
| 14      | 0.045    | 0.459    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 18, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 20, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 21, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.404    | 0.459    | -0.055   |
| 2       | 0.408    | 0.459    | -0.051   |
| 3       | 0.413    | 0.459    | -0.046   |
| 4       | 0.416    | 0.459    | -0.042   |
| 5       | 0.421    | 0.459    | -0.038   |
| 6       | 0.426    | 0.459    | -0.033   |
| 7       | 0.430    | 0.459    | -0.028   |
| 8       | 0.434    | 0.459    | -0.025   |
| 9       | 0.439    | 0.459    | -0.020   |
| 10      | 0.443    | 0.459    | -0.015   |
| 11      | 0.448    | 0.459    | -0.011   |
| 12      | 0.452    | 0.459    | -0.007   |
| 13      | 0.456    | 0.459    | -0.002   |
| 14      | 0.045    | 0.459    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 22, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.404    | 0.459    | -0.055   |
| 2       | 0.408    | 0.459    | -0.051   |
| 3       | 0.413    | 0.459    | -0.046   |
| 4       | 0.416    | 0.459    | -0.042   |
| 5       | 0.421    | 0.459    | -0.038   |
| 6       | 0.426    | 0.459    | -0.033   |
| 7       | 0.430    | 0.459    | -0.028   |
| 8       | 0.434    | 0.459    | -0.025   |
| 9       | 0.439    | 0.459    | -0.020   |
| 10      | 0.443    | 0.459    | -0.015   |
| 11      | 0.448    | 0.459    | -0.011   |
| 12      | 0.452    | 0.459    | -0.007   |
| 13      | 0.456    | 0.459    | -0.002   |
| 14      | 0.045    | 0.459    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 25, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 27, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: For 'SB_LC (3, 0, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 2, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 3, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 5, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 7, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 9, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 10, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 12, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 16, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 17, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 19, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 23, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 24, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 26, 0, 6)' the delay model slope is negative! (a=-7.50e-12)
WARNING: Error of the timing model of 'SB_LC (3, 0, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.384    | 0.439    | -0.055   |
| 2       | 0.388    | 0.439    | -0.051   |
| 3       | 0.393    | 0.439    | -0.046   |
| 4       | 0.397    | 0.439    | -0.042   |
| 5       | 0.401    | 0.439    | -0.038   |
| 6       | 0.406    | 0.439    | -0.033   |
| 7       | 0.411    | 0.439    | -0.028   |
| 8       | 0.414    | 0.439    | -0.025   |
| 9       | 0.419    | 0.439    | -0.020   |
| 10      | 0.423    | 0.439    | -0.015   |
| 11      | 0.428    | 0.439    | -0.011   |
| 12      | 0.432    | 0.439    | -0.007   |
| 13      | 0.436    | 0.439    | -0.002   |
| 14      | 0.025    | 0.439    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 2, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.404    | 0.459    | -0.055   |
| 2       | 0.408    | 0.459    | -0.051   |
| 3       | 0.413    | 0.459    | -0.046   |
| 4       | 0.416    | 0.459    | -0.042   |
| 5       | 0.421    | 0.459    | -0.038   |
| 6       | 0.426    | 0.459    | -0.033   |
| 7       | 0.430    | 0.459    | -0.028   |
| 8       | 0.434    | 0.459    | -0.025   |
| 9       | 0.439    | 0.459    | -0.020   |
| 10      | 0.443    | 0.459    | -0.015   |
| 11      | 0.448    | 0.459    | -0.011   |
| 12      | 0.452    | 0.459    | -0.007   |
| 13      | 0.456    | 0.459    | -0.002   |
| 14      | 0.045    | 0.459    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 3, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 5, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 7, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.384    | 0.439    | -0.055   |
| 2       | 0.388    | 0.439    | -0.051   |
| 3       | 0.393    | 0.439    | -0.046   |
| 4       | 0.397    | 0.439    | -0.042   |
| 5       | 0.401    | 0.439    | -0.038   |
| 6       | 0.406    | 0.439    | -0.033   |
| 7       | 0.411    | 0.439    | -0.028   |
| 8       | 0.414    | 0.439    | -0.025   |
| 9       | 0.419    | 0.439    | -0.020   |
| 10      | 0.423    | 0.439    | -0.015   |
| 11      | 0.428    | 0.439    | -0.011   |
| 12      | 0.432    | 0.439    | -0.007   |
| 13      | 0.436    | 0.439    | -0.002   |
| 14      | 0.025    | 0.439    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 9, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.404    | 0.459    | -0.055   |
| 2       | 0.408    | 0.459    | -0.051   |
| 3       | 0.413    | 0.459    | -0.046   |
| 4       | 0.416    | 0.459    | -0.042   |
| 5       | 0.421    | 0.459    | -0.038   |
| 6       | 0.426    | 0.459    | -0.033   |
| 7       | 0.430    | 0.459    | -0.028   |
| 8       | 0.434    | 0.459    | -0.025   |
| 9       | 0.439    | 0.459    | -0.020   |
| 10      | 0.443    | 0.459    | -0.015   |
| 11      | 0.448    | 0.459    | -0.011   |
| 12      | 0.452    | 0.459    | -0.007   |
| 13      | 0.456    | 0.459    | -0.002   |
| 14      | 0.045    | 0.459    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 10, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 12, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 16, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.384    | 0.439    | -0.055   |
| 2       | 0.388    | 0.439    | -0.051   |
| 3       | 0.393    | 0.439    | -0.046   |
| 4       | 0.397    | 0.439    | -0.042   |
| 5       | 0.401    | 0.439    | -0.038   |
| 6       | 0.406    | 0.439    | -0.033   |
| 7       | 0.411    | 0.439    | -0.028   |
| 8       | 0.414    | 0.439    | -0.025   |
| 9       | 0.419    | 0.439    | -0.020   |
| 10      | 0.423    | 0.439    | -0.015   |
| 11      | 0.428    | 0.439    | -0.011   |
| 12      | 0.432    | 0.439    | -0.007   |
| 13      | 0.436    | 0.439    | -0.002   |
| 14      | 0.025    | 0.439    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 17, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 19, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 23, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.384    | 0.439    | -0.055   |
| 2       | 0.388    | 0.439    | -0.051   |
| 3       | 0.393    | 0.439    | -0.046   |
| 4       | 0.397    | 0.439    | -0.042   |
| 5       | 0.401    | 0.439    | -0.038   |
| 6       | 0.406    | 0.439    | -0.033   |
| 7       | 0.411    | 0.439    | -0.028   |
| 8       | 0.414    | 0.439    | -0.025   |
| 9       | 0.419    | 0.439    | -0.020   |
| 10      | 0.423    | 0.439    | -0.015   |
| 11      | 0.428    | 0.439    | -0.011   |
| 12      | 0.432    | 0.439    | -0.007   |
| 13      | 0.436    | 0.439    | -0.002   |
| 14      | 0.025    | 0.439    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 24, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 26, 0, 6)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: For 'SB_LC (3, 1, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 4, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 6, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 8, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 11, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 13, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 14, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 15, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 18, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 20, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 21, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 22, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 25, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 27, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: Error of the timing model of 'SB_LC (3, 1, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.384    | 0.439    | -0.055   |
| 2       | 0.388    | 0.439    | -0.051   |
| 3       | 0.393    | 0.439    | -0.046   |
| 4       | 0.397    | 0.439    | -0.042   |
| 5       | 0.401    | 0.439    | -0.038   |
| 6       | 0.406    | 0.439    | -0.033   |
| 7       | 0.411    | 0.439    | -0.028   |
| 8       | 0.414    | 0.439    | -0.025   |
| 9       | 0.419    | 0.439    | -0.020   |
| 10      | 0.423    | 0.439    | -0.015   |
| 11      | 0.428    | 0.439    | -0.011   |
| 12      | 0.432    | 0.439    | -0.007   |
| 13      | 0.436    | 0.439    | -0.002   |
| 14      | 0.025    | 0.439    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 4, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 6, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 8, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.384    | 0.439    | -0.055   |
| 2       | 0.388    | 0.439    | -0.051   |
| 3       | 0.393    | 0.439    | -0.046   |
| 4       | 0.397    | 0.439    | -0.042   |
| 5       | 0.401    | 0.439    | -0.038   |
| 6       | 0.406    | 0.439    | -0.033   |
| 7       | 0.411    | 0.439    | -0.028   |
| 8       | 0.414    | 0.439    | -0.025   |
| 9       | 0.419    | 0.439    | -0.020   |
| 10      | 0.423    | 0.439    | -0.015   |
| 11      | 0.428    | 0.439    | -0.011   |
| 12      | 0.432    | 0.439    | -0.007   |
| 13      | 0.436    | 0.439    | -0.002   |
| 14      | 0.025    | 0.439    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 11, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 13, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 14, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.404    | 0.459    | -0.055   |
| 2       | 0.408    | 0.459    | -0.051   |
| 3       | 0.413    | 0.459    | -0.046   |
| 4       | 0.416    | 0.459    | -0.042   |
| 5       | 0.421    | 0.459    | -0.038   |
| 6       | 0.426    | 0.459    | -0.033   |
| 7       | 0.430    | 0.459    | -0.028   |
| 8       | 0.434    | 0.459    | -0.025   |
| 9       | 0.439    | 0.459    | -0.020   |
| 10      | 0.443    | 0.459    | -0.015   |
| 11      | 0.448    | 0.459    | -0.011   |
| 12      | 0.452    | 0.459    | -0.007   |
| 13      | 0.456    | 0.459    | -0.002   |
| 14      | 0.045    | 0.459    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 15, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.404    | 0.459    | -0.055   |
| 2       | 0.408    | 0.459    | -0.051   |
| 3       | 0.413    | 0.459    | -0.046   |
| 4       | 0.416    | 0.459    | -0.042   |
| 5       | 0.421    | 0.459    | -0.038   |
| 6       | 0.426    | 0.459    | -0.033   |
| 7       | 0.430    | 0.459    | -0.028   |
| 8       | 0.434    | 0.459    | -0.025   |
| 9       | 0.439    | 0.459    | -0.020   |
| 10      | 0.443    | 0.459    | -0.015   |
| 11      | 0.448    | 0.459    | -0.011   |
| 12      | 0.452    | 0.459    | -0.007   |
| 13      | 0.456    | 0.459    | -0.002   |
| 14      | 0.045    | 0.459    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 18, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 20, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 21, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.404    | 0.459    | -0.055   |
| 2       | 0.408    | 0.459    | -0.051   |
| 3       | 0.413    | 0.459    | -0.046   |
| 4       | 0.416    | 0.459    | -0.042   |
| 5       | 0.421    | 0.459    | -0.038   |
| 6       | 0.426    | 0.459    | -0.033   |
| 7       | 0.430    | 0.459    | -0.028   |
| 8       | 0.434    | 0.459    | -0.025   |
| 9       | 0.439    | 0.459    | -0.020   |
| 10      | 0.443    | 0.459    | -0.015   |
| 11      | 0.448    | 0.459    | -0.011   |
| 12      | 0.452    | 0.459    | -0.007   |
| 13      | 0.456    | 0.459    | -0.002   |
| 14      | 0.045    | 0.459    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 22, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.404    | 0.459    | -0.055   |
| 2       | 0.408    | 0.459    | -0.051   |
| 3       | 0.413    | 0.459    | -0.046   |
| 4       | 0.416    | 0.459    | -0.042   |
| 5       | 0.421    | 0.459    | -0.038   |
| 6       | 0.426    | 0.459    | -0.033   |
| 7       | 0.430    | 0.459    | -0.028   |
| 8       | 0.434    | 0.459    | -0.025   |
| 9       | 0.439    | 0.459    | -0.020   |
| 10      | 0.443    | 0.459    | -0.015   |
| 11      | 0.448    | 0.459    | -0.011   |
| 12      | 0.452    | 0.459    | -0.007   |
| 13      | 0.456    | 0.459    | -0.002   |
| 14      | 0.045    | 0.459    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 25, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 27, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: For 'SB_LC (3, 0, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 2, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 3, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 5, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 7, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 9, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 10, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 12, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 16, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 17, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 19, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 23, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 24, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: For 'SB_LC (3, 26, 0, 5)' the delay model slope is negative! (a=-7.50e-12)
WARNING: Error of the timing model of 'SB_LC (3, 0, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.384    | 0.439    | -0.055   |
| 2       | 0.388    | 0.439    | -0.051   |
| 3       | 0.393    | 0.439    | -0.046   |
| 4       | 0.397    | 0.439    | -0.042   |
| 5       | 0.401    | 0.439    | -0.038   |
| 6       | 0.406    | 0.439    | -0.033   |
| 7       | 0.411    | 0.439    | -0.028   |
| 8       | 0.414    | 0.439    | -0.025   |
| 9       | 0.419    | 0.439    | -0.020   |
| 10      | 0.423    | 0.439    | -0.015   |
| 11      | 0.428    | 0.439    | -0.011   |
| 12      | 0.432    | 0.439    | -0.007   |
| 13      | 0.436    | 0.439    | -0.002   |
| 14      | 0.025    | 0.439    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 2, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.404    | 0.459    | -0.055   |
| 2       | 0.408    | 0.459    | -0.051   |
| 3       | 0.413    | 0.459    | -0.046   |
| 4       | 0.416    | 0.459    | -0.042   |
| 5       | 0.421    | 0.459    | -0.038   |
| 6       | 0.426    | 0.459    | -0.033   |
| 7       | 0.430    | 0.459    | -0.028   |
| 8       | 0.434    | 0.459    | -0.025   |
| 9       | 0.439    | 0.459    | -0.020   |
| 10      | 0.443    | 0.459    | -0.015   |
| 11      | 0.448    | 0.459    | -0.011   |
| 12      | 0.452    | 0.459    | -0.007   |
| 13      | 0.456    | 0.459    | -0.002   |
| 14      | 0.045    | 0.459    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 3, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 5, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 7, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.384    | 0.439    | -0.055   |
| 2       | 0.388    | 0.439    | -0.051   |
| 3       | 0.393    | 0.439    | -0.046   |
| 4       | 0.397    | 0.439    | -0.042   |
| 5       | 0.401    | 0.439    | -0.038   |
| 6       | 0.406    | 0.439    | -0.033   |
| 7       | 0.411    | 0.439    | -0.028   |
| 8       | 0.414    | 0.439    | -0.025   |
| 9       | 0.419    | 0.439    | -0.020   |
| 10      | 0.423    | 0.439    | -0.015   |
| 11      | 0.428    | 0.439    | -0.011   |
| 12      | 0.432    | 0.439    | -0.007   |
| 13      | 0.436    | 0.439    | -0.002   |
| 14      | 0.025    | 0.439    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 9, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.404    | 0.459    | -0.055   |
| 2       | 0.408    | 0.459    | -0.051   |
| 3       | 0.413    | 0.459    | -0.046   |
| 4       | 0.416    | 0.459    | -0.042   |
| 5       | 0.421    | 0.459    | -0.038   |
| 6       | 0.426    | 0.459    | -0.033   |
| 7       | 0.430    | 0.459    | -0.028   |
| 8       | 0.434    | 0.459    | -0.025   |
| 9       | 0.439    | 0.459    | -0.020   |
| 10      | 0.443    | 0.459    | -0.015   |
| 11      | 0.448    | 0.459    | -0.011   |
| 12      | 0.452    | 0.459    | -0.007   |
| 13      | 0.456    | 0.459    | -0.002   |
| 14      | 0.045    | 0.459    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 10, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 12, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 16, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.384    | 0.439    | -0.055   |
| 2       | 0.388    | 0.439    | -0.051   |
| 3       | 0.393    | 0.439    | -0.046   |
| 4       | 0.397    | 0.439    | -0.042   |
| 5       | 0.401    | 0.439    | -0.038   |
| 6       | 0.406    | 0.439    | -0.033   |
| 7       | 0.411    | 0.439    | -0.028   |
| 8       | 0.414    | 0.439    | -0.025   |
| 9       | 0.419    | 0.439    | -0.020   |
| 10      | 0.423    | 0.439    | -0.015   |
| 11      | 0.428    | 0.439    | -0.011   |
| 12      | 0.432    | 0.439    | -0.007   |
| 13      | 0.436    | 0.439    | -0.002   |
| 14      | 0.025    | 0.439    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 17, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 19, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 23, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.384    | 0.439    | -0.055   |
| 2       | 0.388    | 0.439    | -0.051   |
| 3       | 0.393    | 0.439    | -0.046   |
| 4       | 0.397    | 0.439    | -0.042   |
| 5       | 0.401    | 0.439    | -0.038   |
| 6       | 0.406    | 0.439    | -0.033   |
| 7       | 0.411    | 0.439    | -0.028   |
| 8       | 0.414    | 0.439    | -0.025   |
| 9       | 0.419    | 0.439    | -0.020   |
| 10      | 0.423    | 0.439    | -0.015   |
| 11      | 0.428    | 0.439    | -0.011   |
| 12      | 0.432    | 0.439    | -0.007   |
| 13      | 0.436    | 0.439    | -0.002   |
| 14      | 0.025    | 0.439    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 24, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

WARNING: Error of the timing model of 'SB_LC (3, 26, 0, 5)' is too high:
--------------------------------------------
| # loads | actual   | model    | error    |
|---------+----------+----------+----------|
| 1       | 0.373    | 0.428    | -0.055   |
| 2       | 0.377    | 0.428    | -0.051   |
| 3       | 0.382    | 0.428    | -0.046   |
| 4       | 0.386    | 0.428    | -0.042   |
| 5       | 0.390    | 0.428    | -0.038   |
| 6       | 0.395    | 0.428    | -0.033   |
| 7       | 0.400    | 0.428    | -0.028   |
| 8       | 0.403    | 0.428    | -0.025   |
| 9       | 0.408    | 0.428    | -0.020   |
| 10      | 0.413    | 0.428    | -0.015   |
| 11      | 0.417    | 0.428    | -0.011   |
| 12      | 0.421    | 0.428    | -0.007   |
| 13      | 0.426    | 0.428    | -0.002   |
| 14      | 0.014    | 0.428    | -0.414   |
--------------------------------------------

Tile grid:
  0: .......................................
  1: ..VG...................................
  2: ....R...............R..................
  3: ....BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB...
  4: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
  5: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLB..
  6: ...BLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
  7: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLB..
  8: ...BLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
  9: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 10: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLB..
 11: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 12: ....LLLLLLL.LLLLLLLLLLLLLLL.LLLLLLLLB..
 13: ...BLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 14: ...BLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 15: ...BLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 16: ...BLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 17: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 18: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLB..
 19: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLB..
 20: ....LLLLLLLLLLLLLLL.LLLLLLLLLLLLLLLLB..
 21: ...BLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLB..
 22: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLB..
 23: ...BLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 24: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 25: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLB..
 26: ...BLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 27: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 28: ...BLLLLLLL.LLLLLLLLLLLLLLL.LLLLLLLLB..
 29: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 30: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLB..
 31: ...BLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 32: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 33: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLB..
 34: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 35: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 36: ....BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB...
 37: ....R...............R..................
 38: .......................................
Switchbox grid:
  0:                                      
  1:                                      
  2:                                      
  3:     XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 
  4:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  5:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  6:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  7:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  8:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  9:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 10:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 11:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 12:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 13:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 14:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 15:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 16:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 17:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 18:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 19:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 20:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 21:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 22:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 23:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 24:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 25:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 26:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 27:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 28:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 29:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 30:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 31:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 32:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 33:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 34:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 35:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 36:     XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 
VPR Segments:
 VprSegment(name='generic', length=1, r_metal=0.0, c_metal=0.0)
 VprSegment(name='pad', length=1, r_metal=0.0, c_metal=0.0)
 VprSegment(name='sbox', length=1, r_metal=0.0, c_metal=0.0)
 VprSegment(name='vcc', length=1, r_metal=0.0, c_metal=0.0)
 VprSegment(name='gnd', length=1, r_metal=0.0, c_metal=0.0)
 VprSegment(name='hop1', length=1, r_metal=0.0, c_metal=0.0)
 VprSegment(name='hop2', length=2, r_metal=0.0, c_metal=0.0)
 VprSegment(name='hop3', length=3, r_metal=0.0, c_metal=0.0)
 VprSegment(name='hop4', length=4, r_metal=0.0, c_metal=0.0)
 VprSegment(name='special', length=1, r_metal=0.0, c_metal=0.0)
VPR Switches:
 VprSwitch(name='generic', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='short', type='short', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.187775_R1.000000_C000.000000', type='mux', t_del=1.8777500000000003e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.000000_R0.000000_C021.737500', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=2.17375e-11)
 VprSwitch(name='sw_T0.295736_R1.000000_C000.000000', type='mux', t_del=2.957357142857143e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.000000_R0.000000_C025.635714', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=2.5635714285714286e-11)
 VprSwitch(name='sw_T0.320385_R1.000000_C000.000000', type='mux', t_del=3.2038500000000003e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.000000_R0.000000_C027.287500', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=2.7287499999999995e-11)
 VprSwitch(name='sw_T0.235875_R1.000000_C000.000000', type='mux', t_del=2.35875e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.427993_R1.000000_C000.000000', type='mux', t_del=4.2799321978021983e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.010912_R0.000000_C000.000000', type='mux', t_del=1.0911999999999983e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.000000_R0.000000_C000.000000', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.030752_R0.000000_C000.000000', type='mux', t_del=3.075199999999999e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.323763_R1.000000_C000.000000', type='mux', t_del=3.2376299999999995e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.010912_R0.000000_C006.475000', type='mux', t_del=1.0912000000000034e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=6.475000000000017e-12)
 VprSwitch(name='sw_T0.000000_R0.000000_C006.475000', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=6.475000000000017e-12)
 VprSwitch(name='sw_T0.313588_R1.000000_C000.000000', type='mux', t_del=3.1358799999999993e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.010912_R0.000000_C006.937500', type='mux', t_del=1.0912000000000034e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=6.937500000000024e-12)
 VprSwitch(name='sw_T0.000000_R0.000000_C006.937500', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=6.937500000000024e-12)
 VprSwitch(name='sw_T0.315412_R1.000000_C000.000000', type='mux', t_del=3.154115714285715e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.010912_R0.000000_C007.637857', type='mux', t_del=1.0911999999999983e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=7.637857142857145e-12)
 VprSwitch(name='sw_T0.000000_R0.000000_C007.637857', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=7.637857142857145e-12)
 VprSwitch(name='sw_T0.030752_R0.000000_C006.937500', type='mux', t_del=3.075200000000009e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=6.937500000000024e-12)
 VprSwitch(name='sw_T0.030752_R0.000000_C007.637857', type='mux', t_del=3.075199999999994e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=7.637857142857145e-12)
 VprSwitch(name='sw_T0.331890_R1.000000_C000.000000', type='mux', t_del=3.3188978571428576e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.010912_R0.000000_C006.673214', type='mux', t_del=1.0911999999999983e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=6.6732142857142835e-12)
 VprSwitch(name='sw_T0.000000_R0.000000_C006.673214', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=6.6732142857142835e-12)
 VprSwitch(name='sw_T0.030752_R0.000000_C006.673214', type='mux', t_del=3.075199999999999e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=6.6732142857142835e-12)
 VprSwitch(name='sw_T0.302488_R1.000000_C000.000000', type='mux', t_del=3.0248800000000004e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.000000_R0.000000_C009.250000', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=9.249999999999994e-12)
 VprSwitch(name='sw_T0.030752_R0.000000_C006.475000', type='mux', t_del=3.075200000000009e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=6.475000000000017e-12)
 VprSwitch(name='sw_T0.327331_R1.000000_C000.000000', type='mux', t_del=3.273308571428572e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.030752_R0.000000_C007.884524', type='mux', t_del=3.075199999999994e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=7.88452380952381e-12)
 VprSwitch(name='sw_T0.000000_R0.000000_C007.884524', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=7.88452380952381e-12)
 VprSwitch(name='sw_T0.010912_R0.000000_C007.884524', type='mux', t_del=1.0911999999999931e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=7.88452380952381e-12)
 VprSwitch(name='sw_T0.318213_R1.000000_C000.000000', type='mux', t_del=3.18213e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.010912_R0.000000_C007.400000', type='mux', t_del=1.0912000000000034e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=7.400000000000021e-12)
 VprSwitch(name='sw_T0.000000_R0.000000_C007.400000', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=7.400000000000021e-12)
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_devices_ql-pp3e-virt_db_vpr.pickle
make -f quicklogic/CMakeFiles/file_quicklogic_jimbob4_pinmap.csv.dir/build.make quicklogic/CMakeFiles/file_quicklogic_jimbob4_pinmap.csv.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/CMakeFiles/file_quicklogic_jimbob4_pinmap.csv.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/CMakeFiles/file_quicklogic_jimbob4_pinmap.csv.dir/build.make quicklogic/CMakeFiles/file_quicklogic_jimbob4_pinmap.csv.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating jimbob4_pinmap.csv
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic && /opt/openfpga/vtr/_pyenv/bin/python3 /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/create_pinmap_csv.py -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/jimbob4_pinmap.csv --package WD30 --db /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-pp3e-virt/db_vpr.pickle
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_jimbob4_pinmap.csv
make -f quicklogic/CMakeFiles/PINMAP_INSTALL_jimbob4_ql-pp3e_wlcsp_jimbob4_pinmap.csv.dir/build.make quicklogic/CMakeFiles/PINMAP_INSTALL_jimbob4_ql-pp3e_wlcsp_jimbob4_pinmap.csv.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/CMakeFiles/PINMAP_INSTALL_jimbob4_ql-pp3e_wlcsp_jimbob4_pinmap.csv.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/CMakeFiles/PINMAP_INSTALL_jimbob4_ql-pp3e_wlcsp_jimbob4_pinmap.csv.dir/build.make quicklogic/CMakeFiles/PINMAP_INSTALL_jimbob4_ql-pp3e_wlcsp_jimbob4_pinmap.csv.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make[2]: Nothing to be done for 'quicklogic/CMakeFiles/PINMAP_INSTALL_jimbob4_ql-pp3e_wlcsp_jimbob4_pinmap.csv.dir/build'.
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target PINMAP_INSTALL_jimbob4_ql-pp3e_wlcsp_jimbob4_pinmap.csv
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_db_vpr.pickle.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_db_vpr.pickle.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_db_vpr.pickle.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_db_vpr.pickle.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_db_vpr.pickle.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating db_phy.pickle
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && /opt/openfpga/vtr/_pyenv/bin/python3 /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/data_import.py --techfile /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/ql-eos-s3/Device\ Architecture\ Files/QLAL4S3B.xml --routing-timing /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/ql-eos-s3/Timing\ Data\ Files/qlal4s3b_RoutingDelays_SSM40.csv --db db_phy.pickle
WARNING: No pin in tile at 'Loc(x=8, y=8)' found for switchbox pin 'CZ' of 'SB_LC_X8Y8' at 'Loc(x=8, y=8)'
WARNING: No pin in tile at 'Loc(x=8, y=8)' found for switchbox pin 'FZ' of 'SB_LC_X8Y8' at 'Loc(x=8, y=8)'
WARNING: No pin in tile at 'Loc(x=8, y=8)' found for switchbox pin 'QZ' of 'SB_LC_X8Y8' at 'Loc(x=8, y=8)'
WARNING: No pin in tile at 'Loc(x=8, y=8)' found for switchbox pin 'TZ' of 'SB_LC_X8Y8' at 'Loc(x=8, y=8)'
WARNING: No pin in tile at 'Loc(x=8, y=8)' found for switchbox pin 'TBS' of 'SB_LC_X8Y8' at 'Loc(x=8, y=8)'
WARNING: No pin in tile at 'Loc(x=8, y=8)' found for switchbox pin 'TB2' of 'SB_LC_X8Y8' at 'Loc(x=8, y=8)'
WARNING: No pin in tile at 'Loc(x=8, y=8)' found for switchbox pin 'BA2' of 'SB_LC_X8Y8' at 'Loc(x=8, y=8)'
WARNING: No pin in tile at 'Loc(x=8, y=8)' found for switchbox pin 'BB1' of 'SB_LC_X8Y8' at 'Loc(x=8, y=8)'
WARNING: No pin in tile at 'Loc(x=8, y=8)' found for switchbox pin 'QCK' of 'SB_LC_X8Y8' at 'Loc(x=8, y=8)'
WARNING: No pin in tile at 'Loc(x=8, y=8)' found for switchbox pin 'QRT' of 'SB_LC_X8Y8' at 'Loc(x=8, y=8)'
WARNING: No pin in tile at 'Loc(x=8, y=8)' found for switchbox pin 'F2' of 'SB_LC_X8Y8' at 'Loc(x=8, y=8)'
WARNING: No pin in tile at 'Loc(x=8, y=8)' found for switchbox pin 'TAB' of 'SB_LC_X8Y8' at 'Loc(x=8, y=8)'
WARNING: No pin in tile at 'Loc(x=8, y=8)' found for switchbox pin 'QDI' of 'SB_LC_X8Y8' at 'Loc(x=8, y=8)'
WARNING: No pin in tile at 'Loc(x=24, y=8)' found for switchbox pin 'CZ' of 'SB_LC_X24Y8' at 'Loc(x=24, y=8)'
WARNING: No pin in tile at 'Loc(x=24, y=8)' found for switchbox pin 'FZ' of 'SB_LC_X24Y8' at 'Loc(x=24, y=8)'
WARNING: No pin in tile at 'Loc(x=24, y=8)' found for switchbox pin 'QZ' of 'SB_LC_X24Y8' at 'Loc(x=24, y=8)'
WARNING: No pin in tile at 'Loc(x=24, y=8)' found for switchbox pin 'TZ' of 'SB_LC_X24Y8' at 'Loc(x=24, y=8)'
WARNING: No pin in tile at 'Loc(x=24, y=8)' found for switchbox pin 'TBS' of 'SB_LC_X24Y8' at 'Loc(x=24, y=8)'
WARNING: No pin in tile at 'Loc(x=24, y=8)' found for switchbox pin 'TB2' of 'SB_LC_X24Y8' at 'Loc(x=24, y=8)'
WARNING: No pin in tile at 'Loc(x=24, y=8)' found for switchbox pin 'BA2' of 'SB_LC_X24Y8' at 'Loc(x=24, y=8)'
WARNING: No pin in tile at 'Loc(x=24, y=8)' found for switchbox pin 'BB1' of 'SB_LC_X24Y8' at 'Loc(x=24, y=8)'
WARNING: No pin in tile at 'Loc(x=24, y=8)' found for switchbox pin 'QCK' of 'SB_LC_X24Y8' at 'Loc(x=24, y=8)'
WARNING: No pin in tile at 'Loc(x=24, y=8)' found for switchbox pin 'QRT' of 'SB_LC_X24Y8' at 'Loc(x=24, y=8)'
WARNING: No pin in tile at 'Loc(x=24, y=8)' found for switchbox pin 'F2' of 'SB_LC_X24Y8' at 'Loc(x=24, y=8)'
WARNING: No pin in tile at 'Loc(x=24, y=8)' found for switchbox pin 'TAB' of 'SB_LC_X24Y8' at 'Loc(x=24, y=8)'
WARNING: No pin in tile at 'Loc(x=24, y=8)' found for switchbox pin 'QDI' of 'SB_LC_X24Y8' at 'Loc(x=24, y=8)'
WARNING: No pin in tile at 'Loc(x=16, y=16)' found for switchbox pin 'CZ' of 'SB_LC_X16Y16' at 'Loc(x=16, y=16)'
WARNING: No pin in tile at 'Loc(x=16, y=16)' found for switchbox pin 'FZ' of 'SB_LC_X16Y16' at 'Loc(x=16, y=16)'
WARNING: No pin in tile at 'Loc(x=16, y=16)' found for switchbox pin 'QZ' of 'SB_LC_X16Y16' at 'Loc(x=16, y=16)'
WARNING: No pin in tile at 'Loc(x=16, y=16)' found for switchbox pin 'TZ' of 'SB_LC_X16Y16' at 'Loc(x=16, y=16)'
WARNING: No pin in tile at 'Loc(x=16, y=16)' found for switchbox pin 'QST' of 'SB_LC_X16Y16' at 'Loc(x=16, y=16)'
WARNING: No pin in tile at 'Loc(x=16, y=16)' found for switchbox pin 'TBS' of 'SB_LC_X16Y16' at 'Loc(x=16, y=16)'
WARNING: No pin in tile at 'Loc(x=16, y=16)' found for switchbox pin 'TB2' of 'SB_LC_X16Y16' at 'Loc(x=16, y=16)'
WARNING: No pin in tile at 'Loc(x=16, y=16)' found for switchbox pin 'BAB' of 'SB_LC_X16Y16' at 'Loc(x=16, y=16)'
WARNING: No pin in tile at 'Loc(x=16, y=16)' found for switchbox pin 'BA2' of 'SB_LC_X16Y16' at 'Loc(x=16, y=16)'
WARNING: No pin in tile at 'Loc(x=16, y=16)' found for switchbox pin 'BB1' of 'SB_LC_X16Y16' at 'Loc(x=16, y=16)'
WARNING: No pin in tile at 'Loc(x=16, y=16)' found for switchbox pin 'QEN' of 'SB_LC_X16Y16' at 'Loc(x=16, y=16)'
WARNING: No pin in tile at 'Loc(x=16, y=16)' found for switchbox pin 'QCK' of 'SB_LC_X16Y16' at 'Loc(x=16, y=16)'
WARNING: No pin in tile at 'Loc(x=16, y=16)' found for switchbox pin 'QRT' of 'SB_LC_X16Y16' at 'Loc(x=16, y=16)'
WARNING: No pin in tile at 'Loc(x=16, y=16)' found for switchbox pin 'F2' of 'SB_LC_X16Y16' at 'Loc(x=16, y=16)'
WARNING: No pin in tile at 'Loc(x=16, y=16)' found for switchbox pin 'FS' of 'SB_LC_X16Y16' at 'Loc(x=16, y=16)'
WARNING: No pin in tile at 'Loc(x=16, y=16)' found for switchbox pin 'TAB' of 'SB_LC_X16Y16' at 'Loc(x=16, y=16)'
WARNING: No pin in tile at 'Loc(x=16, y=16)' found for switchbox pin 'QDI' of 'SB_LC_X16Y16' at 'Loc(x=16, y=16)'
WARNING: No pin in tile at 'Loc(x=16, y=16)' found for switchbox pin 'F1' of 'SB_LC_X16Y16' at 'Loc(x=16, y=16)'
WARNING: No pin in tile at 'Loc(x=8, y=23)' found for switchbox pin 'CZ' of 'SB_LC_X8Y23' at 'Loc(x=8, y=23)'
WARNING: No pin in tile at 'Loc(x=8, y=23)' found for switchbox pin 'FZ' of 'SB_LC_X8Y23' at 'Loc(x=8, y=23)'
WARNING: No pin in tile at 'Loc(x=8, y=23)' found for switchbox pin 'QZ' of 'SB_LC_X8Y23' at 'Loc(x=8, y=23)'
WARNING: No pin in tile at 'Loc(x=8, y=23)' found for switchbox pin 'TZ' of 'SB_LC_X8Y23' at 'Loc(x=8, y=23)'
WARNING: No pin in tile at 'Loc(x=8, y=23)' found for switchbox pin 'TBS' of 'SB_LC_X8Y23' at 'Loc(x=8, y=23)'
WARNING: No pin in tile at 'Loc(x=8, y=23)' found for switchbox pin 'TB2' of 'SB_LC_X8Y23' at 'Loc(x=8, y=23)'
WARNING: No pin in tile at 'Loc(x=8, y=23)' found for switchbox pin 'BA2' of 'SB_LC_X8Y23' at 'Loc(x=8, y=23)'
WARNING: No pin in tile at 'Loc(x=8, y=23)' found for switchbox pin 'BB1' of 'SB_LC_X8Y23' at 'Loc(x=8, y=23)'
WARNING: No pin in tile at 'Loc(x=8, y=23)' found for switchbox pin 'QCK' of 'SB_LC_X8Y23' at 'Loc(x=8, y=23)'
WARNING: No pin in tile at 'Loc(x=8, y=23)' found for switchbox pin 'QRT' of 'SB_LC_X8Y23' at 'Loc(x=8, y=23)'
WARNING: No pin in tile at 'Loc(x=8, y=23)' found for switchbox pin 'F2' of 'SB_LC_X8Y23' at 'Loc(x=8, y=23)'
WARNING: No pin in tile at 'Loc(x=8, y=23)' found for switchbox pin 'TAB' of 'SB_LC_X8Y23' at 'Loc(x=8, y=23)'
WARNING: No pin in tile at 'Loc(x=8, y=23)' found for switchbox pin 'QDI' of 'SB_LC_X8Y23' at 'Loc(x=8, y=23)'
WARNING: No pin in tile at 'Loc(x=24, y=23)' found for switchbox pin 'CZ' of 'SB_LC_X24Y23' at 'Loc(x=24, y=23)'
WARNING: No pin in tile at 'Loc(x=24, y=23)' found for switchbox pin 'FZ' of 'SB_LC_X24Y23' at 'Loc(x=24, y=23)'
WARNING: No pin in tile at 'Loc(x=24, y=23)' found for switchbox pin 'QZ' of 'SB_LC_X24Y23' at 'Loc(x=24, y=23)'
WARNING: No pin in tile at 'Loc(x=24, y=23)' found for switchbox pin 'TZ' of 'SB_LC_X24Y23' at 'Loc(x=24, y=23)'
WARNING: No pin in tile at 'Loc(x=24, y=23)' found for switchbox pin 'TBS' of 'SB_LC_X24Y23' at 'Loc(x=24, y=23)'
WARNING: No pin in tile at 'Loc(x=24, y=23)' found for switchbox pin 'TB2' of 'SB_LC_X24Y23' at 'Loc(x=24, y=23)'
WARNING: No pin in tile at 'Loc(x=24, y=23)' found for switchbox pin 'BA2' of 'SB_LC_X24Y23' at 'Loc(x=24, y=23)'
WARNING: No pin in tile at 'Loc(x=24, y=23)' found for switchbox pin 'BB1' of 'SB_LC_X24Y23' at 'Loc(x=24, y=23)'
WARNING: No pin in tile at 'Loc(x=24, y=23)' found for switchbox pin 'QCK' of 'SB_LC_X24Y23' at 'Loc(x=24, y=23)'
WARNING: No pin in tile at 'Loc(x=24, y=23)' found for switchbox pin 'QRT' of 'SB_LC_X24Y23' at 'Loc(x=24, y=23)'
WARNING: No pin in tile at 'Loc(x=24, y=23)' found for switchbox pin 'F2' of 'SB_LC_X24Y23' at 'Loc(x=24, y=23)'
WARNING: No pin in tile at 'Loc(x=24, y=23)' found for switchbox pin 'TAB' of 'SB_LC_X24Y23' at 'Loc(x=24, y=23)'
WARNING: No pin in tile at 'Loc(x=24, y=23)' found for switchbox pin 'QDI' of 'SB_LC_X24Y23' at 'Loc(x=24, y=23)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'H1R0_L1' of switchbox 'SB_TOP_IFC_X1Y1' at 'Loc(x=1, y=1)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'H1R2_L1' of switchbox 'SB_TOP_IFC_X1Y1' at 'Loc(x=1, y=1)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'H1R3_L1' of switchbox 'SB_TOP_IFC_X1Y1' at 'Loc(x=1, y=1)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'H1R1_L1' of switchbox 'SB_TOP_IFC_X1Y1' at 'Loc(x=1, y=1)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'H2R1_L2' of switchbox 'SB_TOP_IFC_X2Y1' at 'Loc(x=2, y=1)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'H2R0_L2' of switchbox 'SB_TOP_IFC_X2Y1' at 'Loc(x=2, y=1)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'H4R0_L4' of switchbox 'SB_TOP_IFC_X4Y1' at 'Loc(x=4, y=1)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'H4L0_R4' of switchbox 'SB_TOP_IFC_X29Y1' at 'Loc(x=29, y=1)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'H4L1_R4' of switchbox 'SB_TOP_IFC_X29Y1' at 'Loc(x=29, y=1)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'H2L0_R2' of switchbox 'SB_TOP_IFC_X31Y1' at 'Loc(x=31, y=1)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'H1L0_R1' of switchbox 'SB_TOP_IFC_X32Y1' at 'Loc(x=32, y=1)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'H1L1_R1' of switchbox 'SB_TOP_IFC_X32Y1' at 'Loc(x=32, y=1)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'H1L2_R1' of switchbox 'SB_TOP_IFC_X32Y1' at 'Loc(x=32, y=1)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'H1L3_R1' of switchbox 'SB_TOP_IFC_X32Y1' at 'Loc(x=32, y=1)'
WARNING: No switchbox at 'Loc(x=0, y=30)' for input 'H1R0_L1' of switchbox 'SB_BOTTOM_IFC_X1Y30' at 'Loc(x=1, y=30)'
WARNING: No switchbox at 'Loc(x=0, y=30)' for input 'H1R2_L1' of switchbox 'SB_BOTTOM_IFC_X1Y30' at 'Loc(x=1, y=30)'
WARNING: No switchbox at 'Loc(x=0, y=30)' for input 'H1R3_L1' of switchbox 'SB_BOTTOM_IFC_X1Y30' at 'Loc(x=1, y=30)'
WARNING: No switchbox at 'Loc(x=0, y=30)' for input 'H1R1_L1' of switchbox 'SB_BOTTOM_IFC_X1Y30' at 'Loc(x=1, y=30)'
WARNING: No switchbox at 'Loc(x=0, y=30)' for input 'H2R1_L2' of switchbox 'SB_BOTTOM_IFC_X2Y30' at 'Loc(x=2, y=30)'
WARNING: No switchbox at 'Loc(x=0, y=30)' for input 'H2R0_L2' of switchbox 'SB_BOTTOM_IFC_X2Y30' at 'Loc(x=2, y=30)'
WARNING: No switchbox at 'Loc(x=0, y=30)' for input 'H4R0_L4' of switchbox 'SB_BOTTOM_IFC_X4Y30' at 'Loc(x=4, y=30)'
WARNING: No switchbox at 'Loc(x=33, y=30)' for input 'H4L0_R4' of switchbox 'SB_BOTTOM_IFC_X29Y30' at 'Loc(x=29, y=30)'
WARNING: No switchbox at 'Loc(x=33, y=30)' for input 'H4L1_R4' of switchbox 'SB_BOTTOM_IFC_X29Y30' at 'Loc(x=29, y=30)'
WARNING: No switchbox at 'Loc(x=33, y=30)' for input 'H2L0_R2' of switchbox 'SB_BOTTOM_IFC_X31Y30' at 'Loc(x=31, y=30)'
WARNING: No switchbox at 'Loc(x=33, y=30)' for input 'H1L0_R1' of switchbox 'SB_BOTTOM_IFC_X32Y30' at 'Loc(x=32, y=30)'
WARNING: No switchbox at 'Loc(x=33, y=30)' for input 'H1L1_R1' of switchbox 'SB_BOTTOM_IFC_X32Y30' at 'Loc(x=32, y=30)'
WARNING: No switchbox at 'Loc(x=33, y=30)' for input 'H1L2_R1' of switchbox 'SB_BOTTOM_IFC_X32Y30' at 'Loc(x=32, y=30)'
WARNING: No switchbox at 'Loc(x=33, y=30)' for input 'H1L3_R1' of switchbox 'SB_BOTTOM_IFC_X32Y30' at 'Loc(x=32, y=30)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'V1B3_T1' of switchbox 'SB_LEFT_IFC_X0Y2' at 'Loc(x=0, y=2)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'V1B1_T1' of switchbox 'SB_LEFT_IFC_X0Y2' at 'Loc(x=0, y=2)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'V1B2_T1' of switchbox 'SB_LEFT_IFC_X0Y2' at 'Loc(x=0, y=2)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'V1B0_T1' of switchbox 'SB_LEFT_IFC_X0Y2' at 'Loc(x=0, y=2)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'V2B0_T2' of switchbox 'SB_LEFT_IFC_X0Y3' at 'Loc(x=0, y=3)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'V4B0_T4' of switchbox 'SB_LEFT_IFC_X0Y5' at 'Loc(x=0, y=5)'
WARNING: No switchbox at 'Loc(x=0, y=1)' for input 'V4B1_T4' of switchbox 'SB_LEFT_IFC_X0Y5' at 'Loc(x=0, y=5)'
WARNING: No switchbox at 'Loc(x=0, y=30)' for input 'V4T0_B4' of switchbox 'SB_LEFT_IFC_X0Y26' at 'Loc(x=0, y=26)'
WARNING: No switchbox at 'Loc(x=0, y=30)' for input 'V2T0_B2' of switchbox 'SB_LEFT_IFC_X0Y28' at 'Loc(x=0, y=28)'
WARNING: No switchbox at 'Loc(x=0, y=30)' for input 'V2T1_B2' of switchbox 'SB_LEFT_IFC_X0Y28' at 'Loc(x=0, y=28)'
WARNING: No switchbox at 'Loc(x=0, y=30)' for input 'V1T2_B1' of switchbox 'SB_LEFT_IFC_X0Y29' at 'Loc(x=0, y=29)'
WARNING: No switchbox at 'Loc(x=0, y=30)' for input 'V1T1_B1' of switchbox 'SB_LEFT_IFC_X0Y29' at 'Loc(x=0, y=29)'
WARNING: No switchbox at 'Loc(x=0, y=30)' for input 'V1T0_B1' of switchbox 'SB_LEFT_IFC_X0Y29' at 'Loc(x=0, y=29)'
WARNING: No switchbox at 'Loc(x=0, y=30)' for input 'V1T3_B1' of switchbox 'SB_LEFT_IFC_X0Y29' at 'Loc(x=0, y=29)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'V1B3_T1' of switchbox 'SB_RIGHT_IFC_X33Y2' at 'Loc(x=33, y=2)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'V1B1_T1' of switchbox 'SB_RIGHT_IFC_X33Y2' at 'Loc(x=33, y=2)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'V1B2_T1' of switchbox 'SB_RIGHT_IFC_X33Y2' at 'Loc(x=33, y=2)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'V1B0_T1' of switchbox 'SB_RIGHT_IFC_X33Y2' at 'Loc(x=33, y=2)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'V2B0_T2' of switchbox 'SB_RIGHT_IFC_X33Y3' at 'Loc(x=33, y=3)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'V4B0_T4' of switchbox 'SB_RIGHT_IFC_X33Y5' at 'Loc(x=33, y=5)'
WARNING: No switchbox at 'Loc(x=33, y=1)' for input 'V4B1_T4' of switchbox 'SB_RIGHT_IFC_X33Y5' at 'Loc(x=33, y=5)'
WARNING: No switchbox at 'Loc(x=33, y=30)' for input 'V4T0_B4' of switchbox 'SB_RIGHT_IFC_X33Y26' at 'Loc(x=33, y=26)'
WARNING: No switchbox at 'Loc(x=33, y=30)' for input 'V2T0_B2' of switchbox 'SB_RIGHT_IFC_X33Y28' at 'Loc(x=33, y=28)'
WARNING: No switchbox at 'Loc(x=33, y=30)' for input 'V2T1_B2' of switchbox 'SB_RIGHT_IFC_X33Y28' at 'Loc(x=33, y=28)'
WARNING: No switchbox at 'Loc(x=33, y=30)' for input 'V1T2_B1' of switchbox 'SB_RIGHT_IFC_X33Y29' at 'Loc(x=33, y=29)'
WARNING: No switchbox at 'Loc(x=33, y=30)' for input 'V1T1_B1' of switchbox 'SB_RIGHT_IFC_X33Y29' at 'Loc(x=33, y=29)'
WARNING: No switchbox at 'Loc(x=33, y=30)' for input 'V1T0_B1' of switchbox 'SB_RIGHT_IFC_X33Y29' at 'Loc(x=33, y=29)'
WARNING: No switchbox at 'Loc(x=33, y=30)' for input 'V1T3_B1' of switchbox 'SB_RIGHT_IFC_X33Y29' at 'Loc(x=33, y=29)'
[  0%] Generating db_vpr.pickle
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && /opt/openfpga/vtr/_pyenv/bin/python3 /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/prepare_vpr_database.py --phy-db db_phy.pickle --vpr-db db_vpr.pickle
Processing timing data...
Tile grid:
  0: .......................................
  1: .AVG...................................
  2: .......................................
  3: ....B.B.B.B.B.B.B.B.B.B.B.B.B.B.B.B.R..
  4: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
  5: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL.M.
  6: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
  7: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
  8: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
  9: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 10: ....LLLLLLL.LLLLLLLLLLLLLLL.LLLLLLLL...
 11: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 12: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 13: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 14: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 15: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 16: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 17: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 18: ....LLLLLLLLLLLLLLL.LLLLLLLLLLLLLLLL.R.
 19: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 20: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 21: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 22: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 23: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 24: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 25: ....LLLLLLL.LLLLLLLLLLLLLLL.LLLLLLLL...
 26: ....LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 27: ..SSLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 28: .SSSLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 29: .SSSLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 30: .SSSLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 31: .SSSLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL...
 32: ....B.B.B.B.B.B.B.B.B.B.B.B.B.B.B.B....
 33: ....RM..............R..................
 34: .......................................
Switchbox grid:
  0:                                      
  1:                                      
  2:                                      
  3:     XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 
  4:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  5:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  6:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  7:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  8:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
  9:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 10:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 11:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 12:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 13:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 14:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 15:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 16:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 17:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 18:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 19:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 20:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 21:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 22:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 23:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 24:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 25:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 26:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 27:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 28:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 29:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 30:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 31:    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 32:     XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 
VPR Segments:
 VprSegment(name='generic', length=1, r_metal=0.0, c_metal=0.0)
 VprSegment(name='pad', length=1, r_metal=0.0, c_metal=0.0)
 VprSegment(name='sbox', length=1, r_metal=0.0, c_metal=0.0)
 VprSegment(name='vcc', length=1, r_metal=0.0, c_metal=0.0)
 VprSegment(name='gnd', length=1, r_metal=0.0, c_metal=0.0)
 VprSegment(name='hop1', length=1, r_metal=0.0, c_metal=0.0)
 VprSegment(name='hop2', length=2, r_metal=0.0, c_metal=0.0)
 VprSegment(name='hop3', length=3, r_metal=0.0, c_metal=0.0)
 VprSegment(name='hop4', length=4, r_metal=0.0, c_metal=0.0)
 VprSegment(name='special', length=1, r_metal=0.0, c_metal=0.0)
VPR Switches:
 VprSwitch(name='generic', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='short', type='short', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.672830_R1.000000_C000.000000', type='mux', t_del=6.7282995e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.138391_R0.000000_C130.045008', type='mux', t_del=1.3839140119047607e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3004500833333333e-10)
 VprSwitch(name='sw_T0.119240_R0.000000_C130.045008', type='mux', t_del=1.1923957142857157e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3004500833333333e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C130.045008', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3004500833333333e-10)
 VprSwitch(name='sw_T0.139058_R0.000000_C130.045008', type='mux', t_del=1.390579642857143e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3004500833333333e-10)
 VprSwitch(name='sw_T0.137213_R0.000000_C130.045008', type='mux', t_del=1.372129785714286e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3004500833333333e-10)
 VprSwitch(name='sw_T0.011386_R0.000000_C130.045008', type='mux', t_del=1.1385639285714564e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3004500833333333e-10)
 VprSwitch(name='sw_T0.080148_R0.000000_C130.045008', type='mux', t_del=8.014831785714296e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3004500833333333e-10)
 VprSwitch(name='sw_T0.135270_R0.000000_C130.045008', type='mux', t_del=1.3527002023809544e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3004500833333333e-10)
 VprSwitch(name='sw_T0.525112_R1.000000_C000.000000', type='mux', t_del=5.251121000000002e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.191979_R0.000000_C088.048300', type='mux', t_del=1.9197869999999968e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=8.804829999999995e-11)
 VprSwitch(name='sw_T0.124380_R0.000000_C088.048300', type='mux', t_del=1.2437969999999963e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=8.804829999999995e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C088.048300', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=8.804829999999995e-11)
 VprSwitch(name='sw_T0.693159_R1.000000_C000.000000', type='mux', t_del=6.9315875e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.091428_R0.000000_C103.241375', type='mux', t_del=9.142834999999995e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.0324137499999984e-10)
 VprSwitch(name='sw_T0.150864_R0.000000_C103.241375', type='mux', t_del=1.5086379761904747e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.0324137499999984e-10)
 VprSwitch(name='sw_T0.099520_R0.000000_C103.241375', type='mux', t_del=9.951960714285727e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.0324137499999984e-10)
 VprSwitch(name='sw_T0.082019_R0.000000_C103.241375', type='mux', t_del=8.201857857142866e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.0324137499999984e-10)
 VprSwitch(name='sw_T0.092701_R0.000000_C103.241375', type='mux', t_del=9.270100595238105e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.0324137499999984e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C103.241375', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.0324137499999984e-10)
 VprSwitch(name='sw_T0.002442_R0.000000_C103.241375', type='mux', t_del=2.4418571428573223e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=1.0324137499999984e-10)
 VprSwitch(name='sw_T0.078956_R0.000000_C103.241375', type='mux', t_del=7.895598214285727e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.0324137499999984e-10)
 VprSwitch(name='sw_T0.656676_R1.000000_C000.000000', type='mux', t_del=6.56675876190476e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.057562_R0.000000_C126.706031', type='mux', t_del=5.7562466666666856e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2670603095238095e-10)
 VprSwitch(name='sw_T0.059226_R0.000000_C126.706031', type='mux', t_del=5.922625476190503e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2670603095238095e-10)
 VprSwitch(name='sw_T0.107127_R0.000000_C126.706031', type='mux', t_del=1.071269571428575e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2670603095238095e-10)
 VprSwitch(name='sw_T0.087448_R0.000000_C126.706031', type='mux', t_del=8.744799523809547e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2670603095238095e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C126.706031', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2670603095238095e-10)
 VprSwitch(name='sw_T0.133467_R0.000000_C126.706031', type='mux', t_del=1.3346673690476212e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2670603095238095e-10)
 VprSwitch(name='sw_T0.100848_R0.000000_C126.706031', type='mux', t_del=1.0084802380952405e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2670603095238095e-10)
 VprSwitch(name='sw_T0.129196_R0.000000_C126.706031', type='mux', t_del=1.2919565952380994e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2670603095238095e-10)
 VprSwitch(name='sw_T0.568081_R1.000000_C000.000000', type='mux', t_del=5.68081e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.171102_R0.000000_C080.455200', type='mux', t_del=1.711024000000002e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=8.045520000000002e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C080.455200', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=8.045520000000002e-11)
 VprSwitch(name='sw_T0.150479_R0.000000_C080.455200', type='mux', t_del=1.5047899999999997e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=8.045520000000002e-11)
 VprSwitch(name='sw_T0.551275_R1.000000_C000.000000', type='mux', t_del=5.512753499999999e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.089001_R0.000000_C088.452250', type='mux', t_del=8.900075000000014e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=8.845225000000003e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C088.452250', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=8.845225000000003e-11)
 VprSwitch(name='sw_T0.091304_R0.000000_C088.452250', type='mux', t_del=9.130435000000023e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=8.845225000000003e-11)
 VprSwitch(name='sw_T0.706896_R1.000000_C000.000000', type='mux', t_del=7.068955476190475e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.058746_R0.000000_C133.400890', type='mux', t_del=5.874577380952396e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.334008904761905e-10)
 VprSwitch(name='sw_T0.028788_R0.000000_C133.400890', type='mux', t_del=2.8788238095238256e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.334008904761905e-10)
 VprSwitch(name='sw_T0.068959_R0.000000_C133.400890', type='mux', t_del=6.895865238095256e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.334008904761905e-10)
 VprSwitch(name='sw_T0.022180_R0.000000_C133.400890', type='mux', t_del=2.2180423809524197e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.334008904761905e-10)
 VprSwitch(name='sw_T0.048379_R0.000000_C133.400890', type='mux', t_del=4.837889285714316e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.334008904761905e-10)
 VprSwitch(name='sw_T0.116837_R0.000000_C133.400890', type='mux', t_del=1.1683706547619086e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.334008904761905e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C133.400890', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.334008904761905e-10)
 VprSwitch(name='sw_T0.070739_R0.000000_C133.400890', type='mux', t_del=7.073855238095239e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.334008904761905e-10)
 VprSwitch(name='sw_T0.532754_R1.000000_C000.000000', type='mux', t_del=5.327539e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.030991_R0.000000_C087.201900', type='mux', t_del=3.0991399999999943e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=8.72019e-11)
 VprSwitch(name='sw_T0.021025_R0.000000_C087.201900', type='mux', t_del=2.1025299999999927e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=8.72019e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C087.201900', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=8.72019e-11)
 VprSwitch(name='sw_T0.615532_R1.000000_C000.000000', type='mux', t_del=6.155320238095238e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.000000_R0.000000_C123.613595', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2361359523809527e-10)
 VprSwitch(name='sw_T0.133510_R0.000000_C123.613595', type='mux', t_del=1.3351030952380962e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2361359523809527e-10)
 VprSwitch(name='sw_T0.134853_R0.000000_C123.613595', type='mux', t_del=1.348529761904764e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2361359523809527e-10)
 VprSwitch(name='sw_T0.211957_R0.000000_C123.613595', type='mux', t_del=2.11957011904762e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2361359523809527e-10)
 VprSwitch(name='sw_T0.193279_R0.000000_C123.613595', type='mux', t_del=1.9327909523809544e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2361359523809527e-10)
 VprSwitch(name='sw_T0.213968_R0.000000_C123.613595', type='mux', t_del=2.139676976190478e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2361359523809527e-10)
 VprSwitch(name='sw_T0.216824_R0.000000_C123.613595', type='mux', t_del=2.1682351190476193e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2361359523809527e-10)
 VprSwitch(name='sw_T0.176175_R0.000000_C123.613595', type='mux', t_del=1.761753750000003e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2361359523809527e-10)
 VprSwitch(name='sw_T0.521658_R1.000000_C000.000000', type='mux', t_del=5.216581e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.006595_R0.000000_C090.983400', type='mux', t_del=6.594900000000295e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=9.098340000000003e-11)
 VprSwitch(name='sw_T0.030074_R0.000000_C090.983400', type='mux', t_del=3.007440000000004e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.098340000000003e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C090.983400', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=9.098340000000003e-11)
 VprSwitch(name='sw_T0.687100_R1.000000_C000.000000', type='mux', t_del=6.870995000000003e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.026987_R0.000000_C098.800100', type='mux', t_del=2.6987114285714132e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.88001e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C098.800100', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=9.88001e-11)
 VprSwitch(name='sw_T0.102933_R0.000000_C098.800100', type='mux', t_del=1.0293252857142866e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=9.88001e-11)
 VprSwitch(name='sw_T0.046709_R0.000000_C098.800100', type='mux', t_del=4.6709364285713826e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.88001e-11)
 VprSwitch(name='sw_T0.044350_R0.000000_C098.800100', type='mux', t_del=4.435047619047586e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.88001e-11)
 VprSwitch(name='sw_T0.092607_R0.000000_C098.800100', type='mux', t_del=9.260732142857112e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.88001e-11)
 VprSwitch(name='sw_T0.152096_R0.000000_C098.800100', type='mux', t_del=1.5209621428571384e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=9.88001e-11)
 VprSwitch(name='sw_T0.100773_R0.000000_C098.800100', type='mux', t_del=1.0077344285714261e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=9.88001e-11)
 VprSwitch(name='sw_T0.669760_R1.000000_C000.000000', type='mux', t_del=6.697601249999998e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.020483_R0.000000_C131.107975', type='mux', t_del=2.048311904761894e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3110797500000003e-10)
 VprSwitch(name='sw_T0.028678_R0.000000_C131.107975', type='mux', t_del=2.8677613095238354e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3110797500000003e-10)
 VprSwitch(name='sw_T0.064605_R0.000000_C131.107975', type='mux', t_del=6.46049678571431e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3110797500000003e-10)
 VprSwitch(name='sw_T0.046675_R0.000000_C131.107975', type='mux', t_del=4.6675017857143266e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3110797500000003e-10)
 VprSwitch(name='sw_T0.113682_R0.000000_C131.107975', type='mux', t_del=1.1368162499999986e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3110797500000003e-10)
 VprSwitch(name='sw_T0.054189_R0.000000_C131.107975', type='mux', t_del=5.418850595238128e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3110797500000003e-10)
 VprSwitch(name='sw_T0.081208_R0.000000_C131.107975', type='mux', t_del=8.120791785714304e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3110797500000003e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C131.107975', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3110797500000003e-10)
 VprSwitch(name='sw_T0.425373_R1.000000_C000.000000', type='mux', t_del=4.253731e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.000000_R0.000000_C090.041850', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=9.004185e-11)
 VprSwitch(name='sw_T0.069484_R0.000000_C090.041850', type='mux', t_del=6.948429999999987e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.004185e-11)
 VprSwitch(name='sw_T0.068114_R0.000000_C090.041850', type='mux', t_del=6.811380000000006e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.004185e-11)
 VprSwitch(name='sw_T0.472404_R1.000000_C000.000000', type='mux', t_del=4.72404e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.131263_R0.000000_C089.005650', type='mux', t_del=1.3126329999999993e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=8.900565000000005e-11)
 VprSwitch(name='sw_T0.141058_R0.000000_C089.005650', type='mux', t_del=1.4105780000000015e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=8.900565000000005e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C089.005650', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=8.900565000000005e-11)
 VprSwitch(name='sw_T0.671115_R1.000000_C000.000000', type='mux', t_del=6.711151130952384e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.110937_R0.000000_C128.056977', type='mux', t_del=1.109366964285709e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2805697738095235e-10)
 VprSwitch(name='sw_T0.061121_R0.000000_C128.056977', type='mux', t_del=6.11209166666666e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2805697738095235e-10)
 VprSwitch(name='sw_T0.128981_R0.000000_C128.056977', type='mux', t_del=1.2898117261904743e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2805697738095235e-10)
 VprSwitch(name='sw_T0.124327_R0.000000_C128.056977', type='mux', t_del=1.24327101190476e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2805697738095235e-10)
 VprSwitch(name='sw_T0.101224_R0.000000_C128.056977', type='mux', t_del=1.0122407142857103e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2805697738095235e-10)
 VprSwitch(name='sw_T0.059483_R0.000000_C128.056977', type='mux', t_del=5.94828630952379e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2805697738095235e-10)
 VprSwitch(name='sw_T0.117687_R0.000000_C128.056977', type='mux', t_del=1.1768745833333321e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2805697738095235e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C128.056977', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2805697738095235e-10)
 VprSwitch(name='sw_T0.673009_R1.000000_C000.000000', type='mux', t_del=6.730093857142856e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.140835_R0.000000_C129.035771', type='mux', t_del=1.408345e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2903577142857134e-10)
 VprSwitch(name='sw_T0.127595_R0.000000_C129.035771', type='mux', t_del=1.2759473571428594e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2903577142857134e-10)
 VprSwitch(name='sw_T0.099016_R0.000000_C129.035771', type='mux', t_del=9.901560833333335e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2903577142857134e-10)
 VprSwitch(name='sw_T0.057307_R0.000000_C129.035771', type='mux', t_del=5.730663571428554e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2903577142857134e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C129.035771', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2903577142857134e-10)
 VprSwitch(name='sw_T0.135208_R0.000000_C129.035771', type='mux', t_del=1.3520799999999997e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2903577142857134e-10)
 VprSwitch(name='sw_T0.115171_R0.000000_C129.035771', type='mux', t_del=1.1517104285714316e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2903577142857134e-10)
 VprSwitch(name='sw_T0.002619_R0.000000_C129.035771', type='mux', t_del=2.6186261904762834e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2903577142857134e-10)
 VprSwitch(name='sw_T0.504721_R1.000000_C000.000000', type='mux', t_del=5.047206e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.065740_R0.000000_C077.388950', type='mux', t_del=6.574010000000006e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=7.738895e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C077.388950', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=7.738895e-11)
 VprSwitch(name='sw_T0.152069_R0.000000_C077.388950', type='mux', t_del=1.5206900000000017e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=7.738895e-11)
 VprSwitch(name='sw_T0.713169_R1.000000_C000.000000', type='mux', t_del=7.131691000000001e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.167436_R0.000000_C099.938483', type='mux', t_del=1.6743632142857146e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=9.993848333333333e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C099.938483', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=9.993848333333333e-11)
 VprSwitch(name='sw_T0.040001_R0.000000_C099.938483', type='mux', t_del=4.000105476190507e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.993848333333333e-11)
 VprSwitch(name='sw_T0.050255_R0.000000_C099.938483', type='mux', t_del=5.025492857142863e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.993848333333333e-11)
 VprSwitch(name='sw_T0.104403_R0.000000_C099.938483', type='mux', t_del=1.0440269285714259e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=9.993848333333333e-11)
 VprSwitch(name='sw_T0.089229_R0.000000_C099.938483', type='mux', t_del=8.922925119047625e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.993848333333333e-11)
 VprSwitch(name='sw_T0.115319_R0.000000_C099.938483', type='mux', t_del=1.1531888214285713e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=9.993848333333333e-11)
 VprSwitch(name='sw_T0.091108_R0.000000_C099.938483', type='mux', t_del=9.110815714285724e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.993848333333333e-11)
 VprSwitch(name='sw_T0.682498_R1.000000_C000.000000', type='mux', t_del=6.824978869047619e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.009886_R0.000000_C130.260423', type='mux', t_del=9.88561309523824e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3026042261904765e-10)
 VprSwitch(name='sw_T0.016638_R0.000000_C130.260423', type='mux', t_del=1.6637605952380848e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3026042261904765e-10)
 VprSwitch(name='sw_T0.068310_R0.000000_C130.260423', type='mux', t_del=6.830991309523805e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3026042261904765e-10)
 VprSwitch(name='sw_T0.074519_R0.000000_C130.260423', type='mux', t_del=7.451914880952394e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3026042261904765e-10)
 VprSwitch(name='sw_T0.042204_R0.000000_C130.260423', type='mux', t_del=4.220394642857164e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3026042261904765e-10)
 VprSwitch(name='sw_T0.104882_R0.000000_C130.260423', type='mux', t_del=1.0488228571428566e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3026042261904765e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C130.260423', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3026042261904765e-10)
 VprSwitch(name='sw_T0.070110_R0.000000_C130.260423', type='mux', t_del=7.010992738095239e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3026042261904765e-10)
 VprSwitch(name='sw_T0.664050_R1.000000_C000.000000', type='mux', t_del=6.640496964285715e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.031328_R0.000000_C130.870061', type='mux', t_del=3.132806071428584e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3087006071428573e-10)
 VprSwitch(name='sw_T0.004382_R0.000000_C130.870061', type='mux', t_del=4.381958333332999e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3087006071428573e-10)
 VprSwitch(name='sw_T0.005382_R0.000000_C130.870061', type='mux', t_del=5.382217857142715e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3087006071428573e-10)
 VprSwitch(name='sw_T0.095302_R0.000000_C130.870061', type='mux', t_del=9.530155119047611e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3087006071428573e-10)
 VprSwitch(name='sw_T0.040474_R0.000000_C130.870061', type='mux', t_del=4.047440476190448e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3087006071428573e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C130.870061', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3087006071428573e-10)
 VprSwitch(name='sw_T0.061676_R0.000000_C130.870061', type='mux', t_del=6.167602976190457e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3087006071428573e-10)
 VprSwitch(name='sw_T0.039962_R0.000000_C130.870061', type='mux', t_del=3.996229880952398e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3087006071428573e-10)
 VprSwitch(name='sw_T0.627035_R1.000000_C000.000000', type='mux', t_del=6.270347952380954e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.084905_R0.000000_C129.366301', type='mux', t_del=8.490531190476189e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2936630119047616e-10)
 VprSwitch(name='sw_T0.065280_R0.000000_C129.366301', type='mux', t_del=6.528036547619049e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2936630119047616e-10)
 VprSwitch(name='sw_T0.098311_R0.000000_C129.366301', type='mux', t_del=9.831056190476188e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2936630119047616e-10)
 VprSwitch(name='sw_T0.046564_R0.000000_C129.366301', type='mux', t_del=4.656399047619049e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2936630119047616e-10)
 VprSwitch(name='sw_T0.133410_R0.000000_C129.366301', type='mux', t_del=1.3341009047619055e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2936630119047616e-10)
 VprSwitch(name='sw_T0.074648_R0.000000_C129.366301', type='mux', t_del=7.464766309523785e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2936630119047616e-10)
 VprSwitch(name='sw_T0.083579_R0.000000_C129.366301', type='mux', t_del=8.357940119047632e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2936630119047616e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C129.366301', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2936630119047616e-10)
 VprSwitch(name='sw_T0.696741_R1.000000_C000.000000', type='mux', t_del=6.967408273809526e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.089169_R0.000000_C102.071835', type='mux', t_del=8.916862976190465e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.0207183452380953e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C102.071835', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.0207183452380953e-10)
 VprSwitch(name='sw_T0.047359_R0.000000_C102.071835', type='mux', t_del=4.735872023809496e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.0207183452380953e-10)
 VprSwitch(name='sw_T0.091716_R0.000000_C102.071835', type='mux', t_del=9.171566071428553e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.0207183452380953e-10)
 VprSwitch(name='sw_T0.060669_R0.000000_C102.071835', type='mux', t_del=6.066918452380944e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.0207183452380953e-10)
 VprSwitch(name='sw_T0.106907_R0.000000_C102.071835', type='mux', t_del=1.069071071428569e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.0207183452380953e-10)
 VprSwitch(name='sw_T0.108426_R0.000000_C102.071835', type='mux', t_del=1.0842611904761877e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.0207183452380953e-10)
 VprSwitch(name='sw_T0.101416_R0.000000_C102.071835', type='mux', t_del=1.0141640119047631e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.0207183452380953e-10)
 VprSwitch(name='sw_T0.497173_R1.000000_C000.000000', type='mux', t_del=4.971727e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.013955_R0.000000_C090.128000', type='mux', t_del=1.3955400000000107e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.012800000000001e-11)
 VprSwitch(name='sw_T0.043981_R0.000000_C090.128000', type='mux', t_del=4.3980500000000146e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.012800000000001e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C090.128000', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=9.012800000000001e-11)
 VprSwitch(name='sw_T0.524581_R1.000000_C000.000000', type='mux', t_del=5.245807000000001e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.000000_R0.000000_C090.934750', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=9.093474999999993e-11)
 VprSwitch(name='sw_T0.001977_R0.000000_C090.934750', type='mux', t_del=1.9771000000000345e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=9.093474999999993e-11)
 VprSwitch(name='sw_T0.044652_R0.000000_C090.934750', type='mux', t_del=4.4652299999999953e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.093474999999993e-11)
 VprSwitch(name='sw_T0.634629_R1.000000_C000.000000', type='mux', t_del=6.346291214285716e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.086072_R0.000000_C128.661813', type='mux', t_del=8.60724440476186e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.286618130952381e-10)
 VprSwitch(name='sw_T0.072059_R0.000000_C128.661813', type='mux', t_del=7.205932499999974e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.286618130952381e-10)
 VprSwitch(name='sw_T0.057514_R0.000000_C128.661813', type='mux', t_del=5.751408690476176e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.286618130952381e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C128.661813', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.286618130952381e-10)
 VprSwitch(name='sw_T0.054788_R0.000000_C128.661813', type='mux', t_del=5.4787978571428343e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.286618130952381e-10)
 VprSwitch(name='sw_T0.060209_R0.000000_C128.661813', type='mux', t_del=6.020918809523782e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.286618130952381e-10)
 VprSwitch(name='sw_T0.027566_R0.000000_C128.661813', type='mux', t_del=2.756570595238074e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.286618130952381e-10)
 VprSwitch(name='sw_T0.123455_R0.000000_C128.661813', type='mux', t_del=1.2345459285714294e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.286618130952381e-10)
 VprSwitch(name='sw_T0.494273_R1.000000_C000.000000', type='mux', t_del=4.942726000000001e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.011478_R0.000000_C106.886900', type='mux', t_del=1.1477899999999998e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.0688689999999997e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C106.886900', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.0688689999999997e-10)
 VprSwitch(name='sw_T0.118912_R0.000000_C106.886900', type='mux', t_del=1.189120999999999e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.0688689999999997e-10)
 VprSwitch(name='sw_T0.489034_R1.000000_C000.000000', type='mux', t_del=4.890345e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.000000_R0.000000_C095.274200', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=9.527420000000002e-11)
 VprSwitch(name='sw_T0.032884_R0.000000_C095.274200', type='mux', t_del=3.288420000000009e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.527420000000002e-11)
 VprSwitch(name='sw_T0.037705_R0.000000_C095.274200', type='mux', t_del=3.7704500000000074e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.527420000000002e-11)
 VprSwitch(name='sw_T0.729889_R1.000000_C000.000000', type='mux', t_del=7.298888e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.134697_R0.000000_C088.309450', type='mux', t_del=1.3469740000000027e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=8.830945000000006e-11)
 VprSwitch(name='sw_T0.055106_R0.000000_C088.309450', type='mux', t_del=5.510550000000004e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=8.830945000000006e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C088.309450', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=8.830945000000006e-11)
 VprSwitch(name='sw_T0.539685_R1.000000_C000.000000', type='mux', t_del=5.396850000000001e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.035970_R0.000000_C094.607700', type='mux', t_del=3.5969899999999897e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.460769999999999e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C094.607700', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=9.460769999999999e-11)
 VprSwitch(name='sw_T0.036111_R0.000000_C094.607700', type='mux', t_del=3.611109999999993e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.460769999999999e-11)
 VprSwitch(name='sw_T0.638889_R1.000000_C000.000000', type='mux', t_del=6.388894142857142e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.149651_R0.000000_C098.452646', type='mux', t_del=1.4965107142857174e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=9.845264642857145e-11)
 VprSwitch(name='sw_T0.113694_R0.000000_C098.452646', type='mux', t_del=1.1369399642857158e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=9.845264642857145e-11)
 VprSwitch(name='sw_T0.154911_R0.000000_C098.452646', type='mux', t_del=1.5491127142857143e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=9.845264642857145e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C098.452646', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=9.845264642857145e-11)
 VprSwitch(name='sw_T0.164258_R0.000000_C098.452646', type='mux', t_del=1.642577583333335e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=9.845264642857145e-11)
 VprSwitch(name='sw_T0.174876_R0.000000_C098.452646', type='mux', t_del=1.7487646666666687e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=9.845264642857145e-11)
 VprSwitch(name='sw_T0.226448_R0.000000_C098.452646', type='mux', t_del=2.2644804285714298e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=9.845264642857145e-11)
 VprSwitch(name='sw_T0.172179_R0.000000_C098.452646', type='mux', t_del=1.721789785714285e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=9.845264642857145e-11)
 VprSwitch(name='sw_T0.699612_R1.000000_C000.000000', type='mux', t_del=6.996122142857143e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.144795_R0.000000_C099.147964', type='mux', t_del=1.4479549285714256e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=9.914796428571429e-11)
 VprSwitch(name='sw_T0.104085_R0.000000_C099.147964', type='mux', t_del=1.0408450714285731e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=9.914796428571429e-11)
 VprSwitch(name='sw_T0.080828_R0.000000_C099.147964', type='mux', t_del=8.08277440476192e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.914796428571429e-11)
 VprSwitch(name='sw_T0.066768_R0.000000_C099.147964', type='mux', t_del=6.676776428571438e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.914796428571429e-11)
 VprSwitch(name='sw_T0.048318_R0.000000_C099.147964', type='mux', t_del=4.8318338095238116e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.914796428571429e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C099.147964', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=9.914796428571429e-11)
 VprSwitch(name='sw_T0.086523_R0.000000_C099.147964', type='mux', t_del=8.652312857142828e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.914796428571429e-11)
 VprSwitch(name='sw_T0.047879_R0.000000_C099.147964', type='mux', t_del=4.787917857142849e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.914796428571429e-11)
 VprSwitch(name='sw_T0.727885_R1.000000_C000.000000', type='mux', t_del=7.278854e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.025369_R0.000000_C095.846450', type='mux', t_del=2.5368500000000128e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.584644999999999e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C095.846450', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=9.584644999999999e-11)
 VprSwitch(name='sw_T0.113206_R0.000000_C095.846450', type='mux', t_del=1.1320630000000013e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=9.584644999999999e-11)
 VprSwitch(name='sw_T0.516440_R1.000000_C000.000000', type='mux', t_del=5.164396e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.000000_R0.000000_C079.565600', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=7.956560000000001e-11)
 VprSwitch(name='sw_T0.032194_R0.000000_C079.565600', type='mux', t_del=3.219425000000008e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=7.956560000000001e-11)
 VprSwitch(name='sw_T0.032891_R0.000000_C079.565600', type='mux', t_del=3.289050000000003e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=7.956560000000001e-11)
 VprSwitch(name='sw_T0.482228_R1.000000_C000.000000', type='mux', t_del=4.822282e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.000000_R0.000000_C116.891600', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.168916e-10)
 VprSwitch(name='sw_T0.033475_R0.000000_C116.891600', type='mux', t_del=3.3475300000000024e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.168916e-10)
 VprSwitch(name='sw_T0.156076_R0.000000_C116.891600', type='mux', t_del=1.5607649999999996e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.168916e-10)
 VprSwitch(name='sw_T0.668315_R1.000000_C000.000000', type='mux', t_del=6.683149821428573e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.121890_R0.000000_C126.477004', type='mux', t_del=1.2189009523809524e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2647700357142856e-10)
 VprSwitch(name='sw_T0.069159_R0.000000_C126.477004', type='mux', t_del=6.91585595238098e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2647700357142856e-10)
 VprSwitch(name='sw_T0.130807_R0.000000_C126.477004', type='mux', t_del=1.3080696071428554e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2647700357142856e-10)
 VprSwitch(name='sw_T0.057222_R0.000000_C126.477004', type='mux', t_del=5.7222351190476124e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2647700357142856e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C126.477004', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2647700357142856e-10)
 VprSwitch(name='sw_T0.099210_R0.000000_C126.477004', type='mux', t_del=9.920959523809522e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2647700357142856e-10)
 VprSwitch(name='sw_T0.058621_R0.000000_C126.477004', type='mux', t_del=5.862062499999994e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2647700357142856e-10)
 VprSwitch(name='sw_T0.132742_R0.000000_C126.477004', type='mux', t_del=1.327420654761902e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2647700357142856e-10)
 VprSwitch(name='sw_T0.503143_R1.000000_C000.000000', type='mux', t_del=5.031429000000001e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.027738_R0.000000_C091.414100', type='mux', t_del=2.7737699999999938e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.141409999999996e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C091.414100', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=9.141409999999996e-11)
 VprSwitch(name='sw_T0.005502_R0.000000_C091.414100', type='mux', t_del=5.501999999999843e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=9.141409999999996e-11)
 VprSwitch(name='sw_T0.534322_R1.000000_C000.000000', type='mux', t_del=5.343220000000002e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.000000_R0.000000_C098.365000', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=9.836499999999995e-11)
 VprSwitch(name='sw_T0.035435_R0.000000_C098.365000', type='mux', t_del=3.5434899999999857e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.836499999999995e-11)
 VprSwitch(name='sw_T0.028502_R0.000000_C098.365000', type='mux', t_del=2.8501999999999764e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.836499999999995e-11)
 VprSwitch(name='sw_T0.559424_R1.000000_C000.000000', type='mux', t_del=5.594238e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.080719_R0.000000_C103.137950', type='mux', t_del=8.071889999999997e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.0313795000000004e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C103.137950', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.0313795000000004e-10)
 VprSwitch(name='sw_T0.078000_R0.000000_C103.137950', type='mux', t_del=7.800000000000014e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.0313795000000004e-10)
 VprSwitch(name='sw_T0.534639_R1.000000_C000.000000', type='mux', t_del=5.346393e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.000000_R0.000000_C095.550650', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=9.555065e-11)
 VprSwitch(name='sw_T0.011019_R0.000000_C095.550650', type='mux', t_del=1.1018599999999997e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=9.555065e-11)
 VprSwitch(name='sw_T0.006118_R0.000000_C095.550650', type='mux', t_del=6.1175999999999335e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=9.555065e-11)
 VprSwitch(name='sw_T0.639488_R1.000000_C000.000000', type='mux', t_del=6.394875000000002e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.095403_R0.000000_C085.566000', type='mux', t_del=9.54029e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=8.556599999999996e-11)
 VprSwitch(name='sw_T0.015089_R0.000000_C085.566000', type='mux', t_del=1.5088799999999924e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=8.556599999999996e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C085.566000', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=8.556599999999996e-11)
 VprSwitch(name='sw_T0.551261_R1.000000_C000.000000', type='mux', t_del=5.512609000000002e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.049756_R0.000000_C108.833300', type='mux', t_del=4.975559999999988e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.0883329999999994e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C108.833300', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.0883329999999994e-10)
 VprSwitch(name='sw_T0.179945_R0.000000_C108.833300', type='mux', t_del=1.7994509999999987e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.0883329999999994e-10)
 VprSwitch(name='sw_T0.500734_R1.000000_C000.000000', type='mux', t_del=5.007337e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.000000_R0.000000_C081.647750', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=8.164774999999998e-11)
 VprSwitch(name='sw_T0.097216_R0.000000_C081.647750', type='mux', t_del=9.72161e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=8.164774999999998e-11)
 VprSwitch(name='sw_T0.046610_R0.000000_C081.647750', type='mux', t_del=4.6610050000000024e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=8.164774999999998e-11)
 VprSwitch(name='sw_T0.401064_R1.000000_C000.000000', type='mux', t_del=4.010643000000001e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.000000_R0.000000_C126.233000', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2623299999999996e-10)
 VprSwitch(name='sw_T0.038463_R0.000000_C126.233000', type='mux', t_del=3.8463099999999943e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2623299999999996e-10)
 VprSwitch(name='sw_T0.080379_R0.000000_C126.233000', type='mux', t_del=8.037879999999991e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2623299999999996e-10)
 VprSwitch(name='sw_T0.385136_R1.000000_C000.000000', type='mux', t_del=3.851356e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.000000_R0.000000_C123.050650', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2305065e-10)
 VprSwitch(name='sw_T0.050800_R0.000000_C123.050650', type='mux', t_del=5.0799500000000017e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2305065e-10)
 VprSwitch(name='sw_T0.103340_R0.000000_C123.050650', type='mux', t_del=1.0333990000000015e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2305065e-10)
 VprSwitch(name='sw_T0.403547_R1.000000_C000.000000', type='mux', t_del=4.035474e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.000000_R0.000000_C125.798800', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.257988e-10)
 VprSwitch(name='sw_T0.016324_R0.000000_C125.798800', type='mux', t_del=1.6324000000000036e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.257988e-10)
 VprSwitch(name='sw_T0.065563_R0.000000_C125.798800', type='mux', t_del=6.556309999999998e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.257988e-10)
 VprSwitch(name='sw_T0.380959_R1.000000_C000.000000', type='mux', t_del=3.809591e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.000000_R0.000000_C125.268000', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.25268e-10)
 VprSwitch(name='sw_T0.042569_R0.000000_C125.268000', type='mux', t_del=4.256860000000006e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.25268e-10)
 VprSwitch(name='sw_T0.086549_R0.000000_C125.268000', type='mux', t_del=8.65490999999999e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.25268e-10)
 VprSwitch(name='sw_T0.437422_R1.000000_C000.000000', type='mux', t_del=4.3742209999999997e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.037433_R0.000000_C130.613400', type='mux', t_del=3.743299999999997e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3061340000000003e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C130.613400', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3061340000000003e-10)
 VprSwitch(name='sw_T0.042918_R0.000000_C130.613400', type='mux', t_del=4.291790000000005e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3061340000000003e-10)
 VprSwitch(name='sw_T0.864096_R1.000000_C000.000000', type='mux', t_del=8.640962000000002e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.020054_R0.000000_C134.751900', type='mux', t_del=2.005379999999971e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3475189999999996e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C134.751900', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3475189999999996e-10)
 VprSwitch(name='sw_T0.010404_R0.000000_C134.751900', type='mux', t_del=1.0403799999999645e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3475189999999996e-10)
 VprSwitch(name='sw_T1.032400_R1.000000_C000.000000', type='mux', t_del=1.0324000000000003e-09, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.112092_R0.000000_C039.500000', type='mux', t_del=1.1209233714285701e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=3.95e-11)
 VprSwitch(name='sw_T0.082177_R0.000000_C039.500000', type='mux', t_del=8.217701142857146e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.95e-11)
 VprSwitch(name='sw_T0.076516_R0.000000_C039.500000', type='mux', t_del=7.651551999999996e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.95e-11)
 VprSwitch(name='sw_T0.037016_R0.000000_C039.500000', type='mux', t_del=3.7015519999999836e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.95e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C039.500000', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=3.95e-11)
 VprSwitch(name='sw_T0.015862_R0.000000_C039.500000', type='mux', t_del=1.5861685714285498e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.95e-11)
 VprSwitch(name='sw_T0.155662_R0.000000_C039.500000', type='mux', t_del=1.5566168571428557e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=3.95e-11)
 VprSwitch(name='sw_T0.160200_R0.000000_C039.500000', type='mux', t_del=1.6019999999999992e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=3.95e-11)
 VprSwitch(name='sw_T0.086608_R0.000000_C039.500000', type='mux', t_del=8.660775999999971e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.95e-11)
 VprSwitch(name='sw_T0.089623_R0.000000_C039.500000', type='mux', t_del=8.962327999999967e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.95e-11)
 VprSwitch(name='sw_T0.111539_R0.000000_C039.500000', type='mux', t_del=1.1153879999999983e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=3.95e-11)
 VprSwitch(name='sw_T0.092723_R0.000000_C039.500000', type='mux', t_del=9.272327999999979e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.95e-11)
 VprSwitch(name='sw_T0.003477_R0.000000_C039.500000', type='mux', t_del=3.477011428571307e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=3.95e-11)
 VprSwitch(name='sw_T0.003262_R0.000000_C039.500000', type='mux', t_del=3.261685714285355e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=3.95e-11)
 VprSwitch(name='sw_T0.693545_R1.000000_C000.000000', type='mux', t_del=6.935454000000002e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.035850_R0.000000_C124.356850', type='mux', t_del=3.5850399999999854e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2435684999999995e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C124.356850', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2435684999999995e-10)
 VprSwitch(name='sw_T0.003802_R0.000000_C124.356850', type='mux', t_del=3.8020999999998705e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2435684999999995e-10)
 VprSwitch(name='sw_T1.068754_R1.000000_C000.000000', type='mux', t_del=1.0687540228571432e-09, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.104177_R0.000000_C038.330823', type='mux', t_del=1.0417701714285665e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8330822857143235e-11)
 VprSwitch(name='sw_T0.139415_R0.000000_C038.330823', type='mux', t_del=1.3941532571428543e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8330822857143235e-11)
 VprSwitch(name='sw_T0.090346_R0.000000_C038.330823', type='mux', t_del=9.034597714285704e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8330822857143235e-11)
 VprSwitch(name='sw_T0.082938_R0.000000_C038.330823', type='mux', t_del=8.293831428571379e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8330822857143235e-11)
 VprSwitch(name='sw_T0.052538_R0.000000_C038.330823', type='mux', t_del=5.2538314285714183e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8330822857143235e-11)
 VprSwitch(name='sw_T0.082877_R0.000000_C038.330823', type='mux', t_del=8.287701714285673e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8330822857143235e-11)
 VprSwitch(name='sw_T0.002893_R0.000000_C038.330823', type='mux', t_del=2.8925371428568706e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8330822857143235e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C038.330823', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8330822857143235e-11)
 VprSwitch(name='sw_T0.102300_R0.000000_C038.330823', type='mux', t_del=1.0229999999999953e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8330822857143235e-11)
 VprSwitch(name='sw_T0.088369_R0.000000_C038.330823', type='mux', t_del=8.836925714285694e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8330822857143235e-11)
 VprSwitch(name='sw_T0.082593_R0.000000_C038.330823', type='mux', t_del=8.259253714285692e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8330822857143235e-11)
 VprSwitch(name='sw_T0.045993_R0.000000_C038.330823', type='mux', t_del=4.5992537142856856e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8330822857143235e-11)
 VprSwitch(name='sw_T0.004961_R0.000000_C038.330823', type='mux', t_del=4.961497142856967e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8330822857143235e-11)
 VprSwitch(name='sw_T0.000208_R0.000000_C038.330823', type='mux', t_del=2.076628571424897e-13, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8330822857143235e-11)
 VprSwitch(name='sw_T0.723508_R1.000000_C000.000000', type='mux', t_del=7.235083e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.006560_R0.000000_C129.219400', type='mux', t_del=6.5600999999999555e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=1.292194e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C129.219400', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.292194e-10)
 VprSwitch(name='sw_T0.091826_R0.000000_C129.219400', type='mux', t_del=9.182600000000005e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.292194e-10)
 VprSwitch(name='sw_T0.832035_R1.000000_C000.000000', type='mux', t_del=8.320352600000001e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.033070_R0.000000_C039.652960', type='mux', t_del=3.306954000000009e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.9652959999999983e-11)
 VprSwitch(name='sw_T0.015920_R0.000000_C039.652960', type='mux', t_del=1.5920239999999914e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.9652959999999983e-11)
 VprSwitch(name='sw_T0.047839_R0.000000_C039.652960', type='mux', t_del=4.783924000000004e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.9652959999999983e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C039.652960', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=3.9652959999999983e-11)
 VprSwitch(name='sw_T0.020659_R0.000000_C039.652960', type='mux', t_del=2.0659140000000107e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.9652959999999983e-11)
 VprSwitch(name='sw_T0.715141_R1.000000_C000.000000', type='mux', t_del=7.151405999999998e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.047578_R0.000000_C131.051600', type='mux', t_del=4.7577800000000596e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3105160000000012e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C131.051600', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3105160000000012e-10)
 VprSwitch(name='sw_T0.117842_R0.000000_C131.051600', type='mux', t_del=1.1784190000000017e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3105160000000012e-10)
 VprSwitch(name='sw_T0.780053_R1.000000_C000.000000', type='mux', t_del=7.800534900000002e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.087544_R0.000000_C037.018570', type='mux', t_del=8.754370999999997e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.701857e-11)
 VprSwitch(name='sw_T0.052152_R0.000000_C037.018570', type='mux', t_del=5.2151509999999976e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.701857e-11)
 VprSwitch(name='sw_T0.047631_R0.000000_C037.018570', type='mux', t_del=4.7631189999999893e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.701857e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C037.018570', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=3.701857e-11)
 VprSwitch(name='sw_T0.708985_R1.000000_C000.000000', type='mux', t_del=7.089848e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.022340_R0.000000_C125.638400', type='mux', t_del=2.234010000000008e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2563840000000005e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C125.638400', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2563840000000005e-10)
 VprSwitch(name='sw_T0.080653_R0.000000_C125.638400', type='mux', t_del=8.065309999999988e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2563840000000005e-10)
 VprSwitch(name='sw_T0.833695_R1.000000_C000.000000', type='mux', t_del=8.336945714285715e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.042011_R0.000000_C039.317586', type='mux', t_del=4.201100000000005e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.9317585714285724e-11)
 VprSwitch(name='sw_T0.013379_R0.000000_C039.317586', type='mux', t_del=1.3379428571428842e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.9317585714285724e-11)
 VprSwitch(name='sw_T0.038334_R0.000000_C039.317586', type='mux', t_del=3.833397142857154e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.9317585714285724e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C039.317586', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=3.9317585714285724e-11)
 VprSwitch(name='sw_T0.041990_R0.000000_C039.317586', type='mux', t_del=4.198960000000016e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.9317585714285724e-11)
 VprSwitch(name='sw_T0.021829_R0.000000_C039.317586', type='mux', t_del=2.182857142857127e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.9317585714285724e-11)
 VprSwitch(name='sw_T0.708242_R1.000000_C000.000000', type='mux', t_del=7.082425e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.056783_R0.000000_C128.357650', type='mux', t_del=5.678260000000009e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2835765000000004e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C128.357650', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2835765000000004e-10)
 VprSwitch(name='sw_T0.116258_R0.000000_C128.357650', type='mux', t_del=1.162578000000002e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2835765000000004e-10)
 VprSwitch(name='sw_T0.774016_R1.000000_C000.000000', type='mux', t_del=7.740165e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.113890_R0.000000_C036.182600', type='mux', t_del=1.1388969000000007e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=3.618260000000004e-11)
 VprSwitch(name='sw_T0.049580_R0.000000_C036.182600', type='mux', t_del=4.957988000000003e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.618260000000004e-11)
 VprSwitch(name='sw_T0.097812_R0.000000_C036.182600', type='mux', t_del=9.781150000000016e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.618260000000004e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C036.182600', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=3.618260000000004e-11)
 VprSwitch(name='sw_T0.727041_R1.000000_C000.000000', type='mux', t_del=7.270406999999998e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.069295_R0.000000_C129.361650', type='mux', t_del=6.929510000000026e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2936165000000007e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C129.361650', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2936165000000007e-10)
 VprSwitch(name='sw_T0.077702_R0.000000_C129.361650', type='mux', t_del=7.770220000000034e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2936165000000007e-10)
 VprSwitch(name='sw_T0.843079_R1.000000_C000.000000', type='mux', t_del=8.430789714285715e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.080360_R0.000000_C041.620186', type='mux', t_del=8.036017142857147e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=4.162018571428573e-11)
 VprSwitch(name='sw_T0.005800_R0.000000_C041.620186', type='mux', t_del=5.7996571428570106e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=4.162018571428573e-11)
 VprSwitch(name='sw_T0.079972_R0.000000_C041.620186', type='mux', t_del=7.997214285714284e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=4.162018571428573e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C041.620186', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=4.162018571428573e-11)
 VprSwitch(name='sw_T0.086072_R0.000000_C041.620186', type='mux', t_del=8.607240000000014e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=4.162018571428573e-11)
 VprSwitch(name='sw_T0.023368_R0.000000_C041.620186', type='mux', t_del=2.3368057142857196e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=4.162018571428573e-11)
 VprSwitch(name='sw_T0.726442_R1.000000_C000.000000', type='mux', t_del=7.264424000000001e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.088670_R0.000000_C129.007800', type='mux', t_del=8.867040000000009e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2900780000000002e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C129.007800', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2900780000000002e-10)
 VprSwitch(name='sw_T0.098932_R0.000000_C129.007800', type='mux', t_del=9.893170000000022e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2900780000000002e-10)
 VprSwitch(name='sw_T0.799702_R1.000000_C000.000000', type='mux', t_del=7.99701625e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.085801_R0.000000_C040.256911', type='mux', t_del=8.580140000000009e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=4.02569107142857e-11)
 VprSwitch(name='sw_T0.061757_R0.000000_C040.256911', type='mux', t_del=6.175713928571401e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=4.02569107142857e-11)
 VprSwitch(name='sw_T0.116907_R0.000000_C040.256911', type='mux', t_del=1.1690740357142846e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=4.02569107142857e-11)
 VprSwitch(name='sw_T0.050450_R0.000000_C040.256911', type='mux', t_del=5.044973928571439e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=4.02569107142857e-11)
 VprSwitch(name='sw_T0.089925_R0.000000_C040.256911', type='mux', t_del=8.992453928571413e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=4.02569107142857e-11)
 VprSwitch(name='sw_T0.000894_R0.000000_C040.256911', type='mux', t_del=8.937750000001529e-13, r=0.0, c_in=0.0, c_out=0.0, c_int=4.02569107142857e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C040.256911', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=4.02569107142857e-11)
 VprSwitch(name='sw_T0.721104_R1.000000_C000.000000', type='mux', t_del=7.211036000000001e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.078388_R0.000000_C130.058000', type='mux', t_del=7.838830000000005e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.30058e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C130.058000', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.30058e-10)
 VprSwitch(name='sw_T0.050917_R0.000000_C130.058000', type='mux', t_del=5.0917400000000067e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.30058e-10)
 VprSwitch(name='sw_T0.807881_R1.000000_C000.000000', type='mux', t_del=8.0788058e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.048650_R0.000000_C042.261930', type='mux', t_del=4.865041e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=4.226192999999996e-11)
 VprSwitch(name='sw_T0.022992_R0.000000_C042.261930', type='mux', t_del=2.2992020000000044e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=4.226192999999996e-11)
 VprSwitch(name='sw_T0.035605_R0.000000_C042.261930', type='mux', t_del=3.560462000000007e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=4.226192999999996e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C042.261930', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=4.226192999999996e-11)
 VprSwitch(name='sw_T0.715573_R1.000000_C000.000000', type='mux', t_del=7.155732e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.112431_R0.000000_C131.175600', type='mux', t_del=1.1243080000000025e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.311756e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C131.175600', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.311756e-10)
 VprSwitch(name='sw_T0.077431_R0.000000_C131.175600', type='mux', t_del=7.743130000000001e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.311756e-10)
 VprSwitch(name='sw_T0.763088_R1.000000_C000.000000', type='mux', t_del=7.630880000000003e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.038123_R0.000000_C034.076300', type='mux', t_del=3.812349999999974e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.4076299999999906e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C034.076300', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=3.4076299999999906e-11)
 VprSwitch(name='sw_T0.735685_R1.000000_C000.000000', type='mux', t_del=7.356845000000002e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.069118_R0.000000_C131.251700', type='mux', t_del=6.911799999999974e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.312516999999999e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C131.251700', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.312516999999999e-10)
 VprSwitch(name='sw_T0.045171_R0.000000_C131.251700', type='mux', t_del=4.51711e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.312516999999999e-10)
 VprSwitch(name='sw_T0.821095_R1.000000_C000.000000', type='mux', t_del=8.210955e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.019218_R0.000000_C040.160900', type='mux', t_del=1.9218399999999864e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=4.016090000000002e-11)
 VprSwitch(name='sw_T0.099937_R0.000000_C040.160900', type='mux', t_del=9.993668000000007e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=4.016090000000002e-11)
 VprSwitch(name='sw_T0.026547_R0.000000_C040.160900', type='mux', t_del=2.6547000000000157e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=4.016090000000002e-11)
 VprSwitch(name='sw_T0.095167_R0.000000_C040.160900', type='mux', t_del=9.51666800000002e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=4.016090000000002e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C040.160900', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=4.016090000000002e-11)
 VprSwitch(name='sw_T0.735473_R1.000000_C000.000000', type='mux', t_del=7.354728999999998e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.092898_R0.000000_C128.380250', type='mux', t_del=9.289770000000026e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.283802500000001e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C128.380250', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.283802500000001e-10)
 VprSwitch(name='sw_T0.073210_R0.000000_C128.380250', type='mux', t_del=7.321010000000024e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.283802500000001e-10)
 VprSwitch(name='sw_T0.787277_R1.000000_C000.000000', type='mux', t_del=7.872773999999999e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.117859_R0.000000_C039.227825', type='mux', t_del=1.178593333333335e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=3.922782500000001e-11)
 VprSwitch(name='sw_T0.047725_R0.000000_C039.227825', type='mux', t_del=4.772547500000011e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.922782500000001e-11)
 VprSwitch(name='sw_T0.035518_R0.000000_C039.227825', type='mux', t_del=3.551846666666676e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.922782500000001e-11)
 VprSwitch(name='sw_T0.087598_R0.000000_C039.227825', type='mux', t_del=8.759827500000016e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.922782500000001e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C039.227825', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=3.922782500000001e-11)
 VprSwitch(name='sw_T0.011375_R0.000000_C039.227825', type='mux', t_del=1.137491666666689e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.922782500000001e-11)
 VprSwitch(name='sw_T0.077376_R0.000000_C039.227825', type='mux', t_del=7.737587500000023e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.922782500000001e-11)
 VprSwitch(name='sw_T0.068711_R0.000000_C039.227825', type='mux', t_del=6.871060000000015e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.922782500000001e-11)
 VprSwitch(name='sw_T0.741519_R1.000000_C000.000000', type='mux', t_del=7.415188000000002e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.057798_R0.000000_C127.882800', type='mux', t_del=5.779839999999985e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.278828000000001e-10)
 VprSwitch(name='sw_T0.003405_R0.000000_C127.882800', type='mux', t_del=3.4051999999999088e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=1.278828000000001e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C127.882800', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.278828000000001e-10)
 VprSwitch(name='sw_T0.826849_R1.000000_C000.000000', type='mux', t_del=8.268492285714287e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.059786_R0.000000_C039.175129', type='mux', t_del=5.978628571428561e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.91751285714286e-11)
 VprSwitch(name='sw_T0.017759_R0.000000_C039.175129', type='mux', t_del=1.7758971428571432e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.91751285714286e-11)
 VprSwitch(name='sw_T0.048254_R0.000000_C039.175129', type='mux', t_del=4.825437142857146e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.91751285714286e-11)
 VprSwitch(name='sw_T0.034757_R0.000000_C039.175129', type='mux', t_del=3.475654285714272e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.91751285714286e-11)
 VprSwitch(name='sw_T0.050899_R0.000000_C039.175129', type='mux', t_del=5.0899314285714495e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.91751285714286e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C039.175129', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=3.91751285714286e-11)
 VprSwitch(name='sw_T0.741394_R1.000000_C000.000000', type='mux', t_del=7.413937e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.083421_R0.000000_C134.003150', type='mux', t_del=8.342050000000006e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3400315000000002e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C134.003150', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3400315000000002e-10)
 VprSwitch(name='sw_T0.029714_R0.000000_C134.003150', type='mux', t_del=2.9713700000000036e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3400315000000002e-10)
 VprSwitch(name='sw_T0.769249_R1.000000_C000.000000', type='mux', t_del=7.692487e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.054724_R0.000000_C036.428900', type='mux', t_del=5.472419999999999e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.642890000000001e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C036.428900', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=3.642890000000001e-11)
 VprSwitch(name='sw_T0.068779_R0.000000_C036.428900', type='mux', t_del=6.877930000000013e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.642890000000001e-11)
 VprSwitch(name='sw_T0.848420_R1.000000_C000.000000', type='mux', t_del=8.484200000000002e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.086845_R0.000000_C039.480000', type='mux', t_del=8.684531428571442e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.9479999999999976e-11)
 VprSwitch(name='sw_T0.008366_R0.000000_C039.480000', type='mux', t_del=8.366171428571257e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=3.9479999999999976e-11)
 VprSwitch(name='sw_T0.081054_R0.000000_C039.480000', type='mux', t_del=8.105394285714276e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.9479999999999976e-11)
 VprSwitch(name='sw_T0.023805_R0.000000_C039.480000', type='mux', t_del=2.3804714285714315e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.9479999999999976e-11)
 VprSwitch(name='sw_T0.114980_R0.000000_C039.480000', type='mux', t_del=1.1498000000000005e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=3.9479999999999976e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C039.480000', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=3.9479999999999976e-11)
 VprSwitch(name='sw_T0.809644_R1.000000_C000.000000', type='mux', t_del=8.0964409e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.024827_R0.000000_C040.376670', type='mux', t_del=2.4826510000000073e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=4.0376670000000036e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C040.376670', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=4.0376670000000036e-11)
 VprSwitch(name='sw_T0.105157_R0.000000_C040.376670', type='mux', t_del=1.0515711000000023e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=4.0376670000000036e-11)
 VprSwitch(name='sw_T0.020291_R0.000000_C040.376670', type='mux', t_del=2.0290799999999985e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=4.0376670000000036e-11)
 VprSwitch(name='sw_T0.763606_R1.000000_C000.000000', type='mux', t_del=7.636064000000002e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.050645_R0.000000_C116.455450', type='mux', t_del=5.0645399999999905e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.1645545000000029e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C116.455450', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.1645545000000029e-10)
 VprSwitch(name='sw_T0.001361_R0.000000_C116.455450', type='mux', t_del=1.3608999999997528e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=1.1645545000000029e-10)
 VprSwitch(name='sw_T1.077000_R1.000000_C000.000000', type='mux', t_del=1.0770000000000003e-09, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.077754_R0.000000_C038.700000', type='mux', t_del=7.775402285714262e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8700000000000006e-11)
 VprSwitch(name='sw_T0.045354_R0.000000_C038.700000', type='mux', t_del=4.535402285714281e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8700000000000006e-11)
 VprSwitch(name='sw_T0.042854_R0.000000_C038.700000', type='mux', t_del=4.285402285714246e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8700000000000006e-11)
 VprSwitch(name='sw_T0.038223_R0.000000_C038.700000', type='mux', t_del=3.8223279999999824e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8700000000000006e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C038.700000', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8700000000000006e-11)
 VprSwitch(name='sw_T0.007854_R0.000000_C038.700000', type='mux', t_del=7.854022857142477e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8700000000000006e-11)
 VprSwitch(name='sw_T0.133654_R0.000000_C038.700000', type='mux', t_del=1.336540228571426e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8700000000000006e-11)
 VprSwitch(name='sw_T0.126439_R0.000000_C038.700000', type='mux', t_del=1.2643879999999985e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8700000000000006e-11)
 VprSwitch(name='sw_T0.054154_R0.000000_C038.700000', type='mux', t_del=5.415402285714241e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8700000000000006e-11)
 VprSwitch(name='sw_T0.057962_R0.000000_C038.700000', type='mux', t_del=5.7961685714285383e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8700000000000006e-11)
 VprSwitch(name='sw_T0.108916_R0.000000_C038.700000', type='mux', t_del=1.0891551999999976e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8700000000000006e-11)
 VprSwitch(name='sw_T0.090400_R0.000000_C038.700000', type='mux', t_del=9.039999999999981e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8700000000000006e-11)
 VprSwitch(name='sw_T0.004354_R0.000000_C038.700000', type='mux', t_del=4.354022857142437e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8700000000000006e-11)
 VprSwitch(name='sw_T0.001185_R0.000000_C038.700000', type='mux', t_del=1.1846742857140638e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8700000000000006e-11)
 VprSwitch(name='sw_T0.864394_R1.000000_C000.000000', type='mux', t_del=8.643943000000001e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.002906_R0.000000_C134.594300', type='mux', t_del=2.9056999999996046e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=1.345943000000005e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C134.594300', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.345943000000005e-10)
 VprSwitch(name='sw_T0.004031_R0.000000_C134.594300', type='mux', t_del=4.030800000000085e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=1.345943000000005e-10)
 VprSwitch(name='sw_T1.039447_R1.000000_C000.000000', type='mux', t_del=1.03944656e-09, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.078330_R0.000000_C038.153817', type='mux', t_del=7.833045142857154e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8153817142857154e-11)
 VprSwitch(name='sw_T0.126361_R0.000000_C038.153817', type='mux', t_del=1.2636120000000014e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8153817142857154e-11)
 VprSwitch(name='sw_T0.065023_R0.000000_C038.153817', type='mux', t_del=6.502278857142875e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8153817142857154e-11)
 VprSwitch(name='sw_T0.054784_R0.000000_C038.153817', type='mux', t_del=5.4784479999999785e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8153817142857154e-11)
 VprSwitch(name='sw_T0.056553_R0.000000_C038.153817', type='mux', t_del=5.6553440000000203e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8153817142857154e-11)
 VprSwitch(name='sw_T0.086153_R0.000000_C038.153817', type='mux', t_del=8.615344000000039e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8153817142857154e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C038.153817', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8153817142857154e-11)
 VprSwitch(name='sw_T0.002377_R0.000000_C038.153817', type='mux', t_del=2.376720000000429e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8153817142857154e-11)
 VprSwitch(name='sw_T0.078377_R0.000000_C038.153817', type='mux', t_del=7.837672000000017e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8153817142857154e-11)
 VprSwitch(name='sw_T0.063061_R0.000000_C038.153817', type='mux', t_del=6.306120000000016e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8153817142857154e-11)
 VprSwitch(name='sw_T0.056392_R0.000000_C038.153817', type='mux', t_del=5.63922400000001e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8153817142857154e-11)
 VprSwitch(name='sw_T0.052446_R0.000000_C038.153817', type='mux', t_del=5.2445777142857345e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8153817142857154e-11)
 VprSwitch(name='sw_T0.010730_R0.000000_C038.153817', type='mux', t_del=1.0730451428571484e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8153817142857154e-11)
 VprSwitch(name='sw_T0.002046_R0.000000_C038.153817', type='mux', t_del=2.0457771428571877e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8153817142857154e-11)
 VprSwitch(name='sw_T0.762972_R1.000000_C000.000000', type='mux', t_del=7.629719000000001e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.000000_R0.000000_C139.004500', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3900450000000013e-10)
 VprSwitch(name='sw_T0.028155_R0.000000_C139.004500', type='mux', t_del=2.815499999999989e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3900450000000013e-10)
 VprSwitch(name='sw_T0.000340_R0.000000_C139.004500', type='mux', t_del=3.3969999999992594e-13, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3900450000000013e-10)
 VprSwitch(name='sw_T0.749848_R1.000000_C000.000000', type='mux', t_del=7.498483000000001e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.076768_R0.000000_C041.592750', type='mux', t_del=7.676769999999992e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=4.1592750000000006e-11)
 VprSwitch(name='sw_T0.068447_R0.000000_C041.592750', type='mux', t_del=6.844659999999996e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=4.1592750000000006e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C041.592750', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=4.1592750000000006e-11)
 VprSwitch(name='sw_T0.775434_R1.000000_C000.000000', type='mux', t_del=7.754335999999999e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.024307_R0.000000_C140.833200', type='mux', t_del=2.43071000000001e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.4083320000000006e-10)
 VprSwitch(name='sw_T0.053252_R0.000000_C140.833200', type='mux', t_del=5.325220000000018e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.4083320000000006e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C140.833200', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.4083320000000006e-10)
 VprSwitch(name='sw_T0.800114_R1.000000_C000.000000', type='mux', t_del=8.001141714285714e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.083389_R0.000000_C039.480986', type='mux', t_del=8.338902857142877e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.94809857142857e-11)
 VprSwitch(name='sw_T0.008989_R0.000000_C039.480986', type='mux', t_del=8.988657142857277e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=3.94809857142857e-11)
 VprSwitch(name='sw_T0.121649_R0.000000_C039.480986', type='mux', t_del=1.2164894285714286e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=3.94809857142857e-11)
 VprSwitch(name='sw_T0.052071_R0.000000_C039.480986', type='mux', t_del=5.207117142857147e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.94809857142857e-11)
 VprSwitch(name='sw_T0.112191_R0.000000_C039.480986', type='mux', t_del=1.1219059999999988e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=3.94809857142857e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C039.480986', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=3.94809857142857e-11)
 VprSwitch(name='sw_T0.751512_R1.000000_C000.000000', type='mux', t_del=7.5151165e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.010109_R0.000000_C134.429450', type='mux', t_del=1.010854999999993e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3442945000000005e-10)
 VprSwitch(name='sw_T0.022320_R0.000000_C134.429450', type='mux', t_del=2.232004999999979e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3442945000000005e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C134.429450', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3442945000000005e-10)
 VprSwitch(name='sw_T0.807932_R1.000000_C000.000000', type='mux', t_del=8.079324285714287e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.071868_R0.000000_C037.727929', type='mux', t_del=7.186788571428573e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.772792857142856e-11)
 VprSwitch(name='sw_T0.058620_R0.000000_C037.727929', type='mux', t_del=5.862011428571429e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.772792857142856e-11)
 VprSwitch(name='sw_T0.037024_R0.000000_C037.727929', type='mux', t_del=3.7023571428571444e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.772792857142856e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C037.727929', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=3.772792857142856e-11)
 VprSwitch(name='sw_T0.045973_R0.000000_C037.727929', type='mux', t_del=4.597259999999979e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.772792857142856e-11)
 VprSwitch(name='sw_T0.000306_R0.000000_C037.727929', type='mux', t_del=3.061142857142736e-13, r=0.0, c_in=0.0, c_out=0.0, c_int=3.772792857142856e-11)
 VprSwitch(name='sw_T0.767376_R1.000000_C000.000000', type='mux', t_del=7.673756500000002e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.034381_R0.000000_C134.941450', type='mux', t_del=3.438145000000009e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3494144999999995e-10)
 VprSwitch(name='sw_T0.048509_R0.000000_C134.941450', type='mux', t_del=4.850875000000009e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3494144999999995e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C134.941450', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3494144999999995e-10)
 VprSwitch(name='sw_T0.812494_R1.000000_C000.000000', type='mux', t_del=8.124936285714285e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.049982_R0.000000_C034.158079', type='mux', t_del=4.998197142857158e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.415807857142859e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C034.158079', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=3.415807857142859e-11)
 VprSwitch(name='sw_T0.128350_R0.000000_C034.158079', type='mux', t_del=1.2834979642857162e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=3.415807857142859e-11)
 VprSwitch(name='sw_T0.049894_R0.000000_C034.158079', type='mux', t_del=4.989392142857153e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.415807857142859e-11)
 VprSwitch(name='sw_T0.066401_R0.000000_C034.158079', type='mux', t_del=6.640102142857162e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.415807857142859e-11)
 VprSwitch(name='sw_T0.098144_R0.000000_C034.158079', type='mux', t_del=9.814422142857175e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.415807857142859e-11)
 VprSwitch(name='sw_T0.002172_R0.000000_C034.158079', type='mux', t_del=2.1720357142859387e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=3.415807857142859e-11)
 VprSwitch(name='sw_T0.760037_R1.000000_C000.000000', type='mux', t_del=7.600374500000002e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.062606_R0.000000_C137.420850', type='mux', t_del=6.260614999999986e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3742084999999994e-10)
 VprSwitch(name='sw_T0.027671_R0.000000_C137.420850', type='mux', t_del=2.7670849999999618e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3742084999999994e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C137.420850', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3742084999999994e-10)
 VprSwitch(name='sw_T0.769942_R1.000000_C000.000000', type='mux', t_del=7.699422000000001e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.043783_R0.000000_C039.769100', type='mux', t_del=4.378318999999987e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.976910000000001e-11)
 VprSwitch(name='sw_T0.001220_R0.000000_C039.769100', type='mux', t_del=1.2196799999999413e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=3.976910000000001e-11)
 VprSwitch(name='sw_T0.092606_R0.000000_C039.769100', type='mux', t_del=9.260567999999994e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.976910000000001e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C039.769100', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=3.976910000000001e-11)
 VprSwitch(name='sw_T0.776154_R1.000000_C000.000000', type='mux', t_del=7.7615355e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.091430_R0.000000_C138.982150', type='mux', t_del=9.143045e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3898215000000003e-10)
 VprSwitch(name='sw_T0.054087_R0.000000_C138.982150', type='mux', t_del=5.408665000000024e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3898215000000003e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C138.982150', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3898215000000003e-10)
 VprSwitch(name='sw_T0.753951_R1.000000_C000.000000', type='mux', t_del=7.539512000000001e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.038382_R0.000000_C036.141900', type='mux', t_del=3.838199999999994e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.614189999999999e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C036.141900', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=3.614189999999999e-11)
 VprSwitch(name='sw_T0.081931_R0.000000_C036.141900', type='mux', t_del=8.193109999999998e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.614189999999999e-11)
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 VprSwitch(name='sw_T0.075304_R0.000000_C038.887620', type='mux', t_del=7.530360000000015e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8887620000000016e-11)
 VprSwitch(name='sw_T0.060291_R0.000000_C038.887620', type='mux', t_del=6.029137999999995e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8887620000000016e-11)
 VprSwitch(name='sw_T0.055242_R0.000000_C038.887620', type='mux', t_del=5.524209999999985e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8887620000000016e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C038.887620', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8887620000000016e-11)
 VprSwitch(name='sw_T0.000329_R0.000000_C038.887620', type='mux', t_del=3.2917999999979847e-13, r=0.0, c_in=0.0, c_out=0.0, c_int=3.8887620000000016e-11)
 VprSwitch(name='sw_T0.735541_R1.000000_C000.000000', type='mux', t_del=7.3554105e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.127123_R0.000000_C132.119650', type='mux', t_del=1.271233499999999e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3211965e-10)
 VprSwitch(name='sw_T0.088353_R0.000000_C132.119650', type='mux', t_del=8.835344999999987e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3211965e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C132.119650', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3211965e-10)
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 VprSwitch(name='sw_T0.119960_R0.000000_C035.792000', type='mux', t_del=1.1996039999999989e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=3.579199999999999e-11)
 VprSwitch(name='sw_T0.054362_R0.000000_C035.792000', type='mux', t_del=5.43616e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.579199999999999e-11)
 VprSwitch(name='sw_T0.100900_R0.000000_C035.792000', type='mux', t_del=1.0090018999999995e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=3.579199999999999e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C035.792000', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=3.579199999999999e-11)
 VprSwitch(name='sw_T0.736945_R1.000000_C000.000000', type='mux', t_del=7.369450999999999e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.109188_R0.000000_C131.677450', type='mux', t_del=1.0918759999999997e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3167745000000002e-10)
 VprSwitch(name='sw_T0.069619_R0.000000_C131.677450', type='mux', t_del=6.961890000000018e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3167745000000002e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C131.677450', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3167745000000002e-10)
 VprSwitch(name='sw_T0.792997_R1.000000_C000.000000', type='mux', t_del=7.929973000000001e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.000000_R0.000000_C035.499720', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=3.5499719999999994e-11)
 VprSwitch(name='sw_T0.138093_R0.000000_C035.499720', type='mux', t_del=1.3809337999999995e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=3.5499719999999994e-11)
 VprSwitch(name='sw_T0.046123_R0.000000_C035.499720', type='mux', t_del=4.6123199999999926e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.5499719999999994e-11)
 VprSwitch(name='sw_T0.090258_R0.000000_C035.499720', type='mux', t_del=9.025760000000002e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.5499719999999994e-11)
 VprSwitch(name='sw_T0.001854_R0.000000_C035.499720', type='mux', t_del=1.854499999999934e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=3.5499719999999994e-11)
 VprSwitch(name='sw_T0.749287_R1.000000_C000.000000', type='mux', t_del=7.492871000000001e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.129764_R0.000000_C132.504300', type='mux', t_del=1.2976370000000012e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3250429999999998e-10)
 VprSwitch(name='sw_T0.090257_R0.000000_C132.504300', type='mux', t_del=9.025679999999987e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3250429999999998e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C132.504300', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.3250429999999998e-10)
 VprSwitch(name='sw_T0.752002_R1.000000_C000.000000', type='mux', t_del=7.520021e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.064494_R0.000000_C037.567700', type='mux', t_del=6.449380000000013e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.7567699999999996e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C037.567700', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=3.7567699999999996e-11)
 VprSwitch(name='sw_T0.730981_R1.000000_C000.000000', type='mux', t_del=7.309813999999999e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.027863_R0.000000_C120.260350', type='mux', t_del=2.7862900000000247e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2026035000000007e-10)
 VprSwitch(name='sw_T0.039485_R0.000000_C120.260350', type='mux', t_del=3.948510000000013e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2026035000000007e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C120.260350', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2026035000000007e-10)
 VprSwitch(name='sw_T0.801504_R1.000000_C000.000000', type='mux', t_del=8.015037142857143e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.037799_R0.000000_C036.632714', type='mux', t_del=3.779868571428581e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.6632714285714307e-11)
 VprSwitch(name='sw_T0.004101_R0.000000_C036.632714', type='mux', t_del=4.101285714285816e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=3.6632714285714307e-11)
 VprSwitch(name='sw_T0.073990_R0.000000_C036.632714', type='mux', t_del=7.399000000000007e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.6632714285714307e-11)
 VprSwitch(name='sw_T0.062294_R0.000000_C036.632714', type='mux', t_del=6.229385714285719e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.6632714285714307e-11)
 VprSwitch(name='sw_T0.049505_R0.000000_C036.632714', type='mux', t_del=4.9504885714285794e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.6632714285714307e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C036.632714', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=3.6632714285714307e-11)
 VprSwitch(name='sw_T0.705269_R1.000000_C000.000000', type='mux', t_del=7.05269e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.123542_R0.000000_C123.455700', type='mux', t_del=1.235424e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2345570000000003e-10)
 VprSwitch(name='sw_T0.102232_R0.000000_C123.455700', type='mux', t_del=1.0223240000000001e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2345570000000003e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C123.455700', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2345570000000003e-10)
 VprSwitch(name='sw_T0.782077_R1.000000_C000.000000', type='mux', t_del=7.8207718e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.062987_R0.000000_C036.423230', type='mux', t_del=6.298690000000016e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.642323000000002e-11)
 VprSwitch(name='sw_T0.011709_R0.000000_C036.423230', type='mux', t_del=1.1709220000000097e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.642323000000002e-11)
 VprSwitch(name='sw_T0.066580_R0.000000_C036.423230', type='mux', t_del=6.657980999999997e-11, r=0.0, c_in=0.0, c_out=0.0, c_int=3.642323000000002e-11)
 VprSwitch(name='sw_T0.000000_R0.000000_C036.423230', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=3.642323000000002e-11)
 VprSwitch(name='sw_T0.715345_R1.000000_C000.000000', type='mux', t_del=7.153446e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
 VprSwitch(name='sw_T0.148114_R0.000000_C124.651800', type='mux', t_del=1.481144000000004e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2465179999999998e-10)
 VprSwitch(name='sw_T0.126375_R0.000000_C124.651800', type='mux', t_del=1.2637450000000004e-10, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2465179999999998e-10)
 VprSwitch(name='sw_T0.000000_R0.000000_C124.651800', type='mux', t_del=0.0, r=0.0, c_in=0.0, c_out=0.0, c_int=1.2465179999999998e-10)
 VprSwitch(name='sw_T0.823449_R1.000000_C000.000000', type='mux', t_del=8.234487333333335e-10, r=1.0, c_in=0.0, c_out=0.0, c_int=0.0)
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 VprSwitch(name='sw_T0.006833_R0.000000_C038.206386', type='mux', t_del=6.832771428571627e-12, r=0.0, c_in=0.0, c_out=0.0, c_int=3.820638571428573e-11)
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make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
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make -f quicklogic/CMakeFiles/file_quicklogic_chilkat_pinmap.csv.dir/build.make quicklogic/CMakeFiles/file_quicklogic_chilkat_pinmap.csv.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/CMakeFiles/file_quicklogic_chilkat_pinmap.csv.dir/DependInfo.cmake --color=
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cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic && /opt/openfpga/vtr/_pyenv/bin/python3 /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/create_pinmap_csv.py -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/chilkat_pinmap.csv --package WR42 --db /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/db_vpr.pickle
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make -f quicklogic/CMakeFiles/PINMAP_INSTALL_chilkat_ql-eos-s3_wlcsp_chilkat_pinmap.csv.dir/build.make quicklogic/CMakeFiles/PINMAP_INSTALL_chilkat_ql-eos-s3_wlcsp_chilkat_pinmap.csv.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/CMakeFiles/PINMAP_INSTALL_chilkat_ql-eos-s3_wlcsp_chilkat_pinmap.csv.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/CMakeFiles/PINMAP_INSTALL_chilkat_ql-eos-s3_wlcsp_chilkat_pinmap.csv.dir/build.make quicklogic/CMakeFiles/PINMAP_INSTALL_chilkat_ql-eos-s3_wlcsp_chilkat_pinmap.csv.dir/build
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make -f quicklogic/CMakeFiles/file_quicklogic_qomu_pinmap.csv.dir/build.make quicklogic/CMakeFiles/file_quicklogic_qomu_pinmap.csv.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/CMakeFiles/file_quicklogic_qomu_pinmap.csv.dir/DependInfo.cmake --color=
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make -f quicklogic/CMakeFiles/file_quicklogic_qomu_pinmap.csv.dir/build.make quicklogic/CMakeFiles/file_quicklogic_qomu_pinmap.csv.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating qomu_pinmap.csv
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic && /opt/openfpga/vtr/_pyenv/bin/python3 /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/create_pinmap_csv.py -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/qomu_pinmap.csv --package WR42 --db /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/db_vpr.pickle
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
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make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/CMakeFiles/PINMAP_INSTALL_qomu_ql-eos-s3_wlcsp_qomu_pinmap.csv.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
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make -f quicklogic/CMakeFiles/file_quicklogic_chandalar_pinmap.csv.dir/build.make quicklogic/CMakeFiles/file_quicklogic_chandalar_pinmap.csv.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/CMakeFiles/file_quicklogic_chandalar_pinmap.csv.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
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make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
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cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic && /opt/openfpga/vtr/_pyenv/bin/python3 /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/create_pinmap_csv.py -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/chandalar_pinmap.csv --package PD64 --db /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/db_vpr.pickle
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
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make -f quicklogic/CMakeFiles/PINMAP_INSTALL_chandalar_ql-eos-s3_wlcsp_chandalar_pinmap.csv.dir/build.make quicklogic/CMakeFiles/PINMAP_INSTALL_chandalar_ql-eos-s3_wlcsp_chandalar_pinmap.csv.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/CMakeFiles/PINMAP_INSTALL_chandalar_ql-eos-s3_wlcsp_chandalar_pinmap.csv.dir/DependInfo.cmake --color=
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make -f quicklogic/CMakeFiles/PINMAP_INSTALL_chandalar_ql-eos-s3_wlcsp_chandalar_pinmap.csv.dir/build.make quicklogic/CMakeFiles/PINMAP_INSTALL_chandalar_ql-eos-s3_wlcsp_chandalar_pinmap.csv.dir/build
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make -f quicklogic/CMakeFiles/file_quicklogic_quickfeather_pinmap.csv.dir/build.make quicklogic/CMakeFiles/file_quicklogic_quickfeather_pinmap.csv.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/CMakeFiles/file_quicklogic_quickfeather_pinmap.csv.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/CMakeFiles/file_quicklogic_quickfeather_pinmap.csv.dir/build.make quicklogic/CMakeFiles/file_quicklogic_quickfeather_pinmap.csv.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating quickfeather_pinmap.csv
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic && /opt/openfpga/vtr/_pyenv/bin/python3 /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/create_pinmap_csv.py -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/quickfeather_pinmap.csv --package PU64 --db /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/db_vpr.pickle
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
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make -f quicklogic/CMakeFiles/PINMAP_INSTALL_quickfeather_ql-eos-s3_wlcsp_quickfeather_pinmap.csv.dir/build.make quicklogic/CMakeFiles/PINMAP_INSTALL_quickfeather_ql-eos-s3_wlcsp_quickfeather_pinmap.csv.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/CMakeFiles/PINMAP_INSTALL_quickfeather_ql-eos-s3_wlcsp_quickfeather_pinmap.csv.dir/DependInfo.cmake --color=
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make -f quicklogic/primitives/mult/CMakeFiles/file_quicklogic_primitives_mult_mult.sim.v.dir/build.make quicklogic/primitives/mult/CMakeFiles/file_quicklogic_primitives_mult_mult.sim.v.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/mult /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/CMakeFiles/file_quicklogic_primitives_mult_mult.sim.v.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/mult/CMakeFiles/file_quicklogic_primitives_mult_mult.sim.v.dir/build.make quicklogic/primitives/mult/CMakeFiles/file_quicklogic_primitives_mult_mult.sim.v.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating mult.sim.v
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult && /usr/bin/cmake -E create_symlink /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/mult/mult.sim.v /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_mult_mult.sim.v
make -f CMakeFiles/v2x.dir/build.make CMakeFiles/v2x.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/CMakeFiles/v2x.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f CMakeFiles/v2x.dir/build.make CMakeFiles/v2x.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make[2]: Nothing to be done for 'CMakeFiles/v2x.dir/build'.
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target v2x
make -f quicklogic/primitives/mult/CMakeFiles/file_quicklogic_primitives_mult_mult.pb_type.xml.dir/build.make quicklogic/primitives/mult/CMakeFiles/file_quicklogic_primitives_mult_mult.pb_type.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/mult /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/CMakeFiles/file_quicklogic_primitives_mult_mult.pb_type.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/mult/CMakeFiles/file_quicklogic_primitives_mult_mult.pb_type.xml.dir/build.make quicklogic/primitives/mult/CMakeFiles/file_quicklogic_primitives_mult_mult.pb_type.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating mult.pb_type.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=pb_type -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.pb_type.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v; prep ; write_json ']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
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      },
      "ports": {
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        "Bmult": {
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        },
        "Valid_mult": {
          "direction": "input",
          "bits": [ 66, 67 ]
        },
        "Cmult": {
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        },
        "sel_mul_32x32": {
          "direction": "input",
          "bits": [ 132 ]
        }
      },
      "cells": {
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:21$2": {
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        "$mul$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:23$4": {
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        "$mul$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:27$6": {
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{iopath_Amult1_Cmult60} {iopath_Amult1_Cmult61} {iopath_Amult1_Cmult62} {iopath_Amult1_Cmult63} 0 0 {iopath_Amult2_Cmult2} {iopath_Amult2_Cmult3} {iopath_Amult2_Cmult4} {iopath_Amult2_Cmult5} {iopath_Amult2_Cmult6} {iopath_Amult2_Cmult7} {iopath_Amult2_Cmult8} {iopath_Amult2_Cmult9} {iopath_Amult2_Cmult10} {iopath_Amult2_Cmult11} {iopath_Amult2_Cmult12} {iopath_Amult2_Cmult13} {iopath_Amult2_Cmult14} {iopath_Amult2_Cmult15} {iopath_Amult2_Cmult16} {iopath_Amult2_Cmult17} {iopath_Amult2_Cmult18} {iopath_Amult2_Cmult19} {iopath_Amult2_Cmult20} {iopath_Amult2_Cmult21} {iopath_Amult2_Cmult22} {iopath_Amult2_Cmult23} {iopath_Amult2_Cmult24} {iopath_Amult2_Cmult25} {iopath_Amult2_Cmult26} {iopath_Amult2_Cmult27} {iopath_Amult2_Cmult28} {iopath_Amult2_Cmult29} {iopath_Amult2_Cmult30} {iopath_Amult2_Cmult31} {iopath_Amult2_Cmult32} {iopath_Amult2_Cmult33} {iopath_Amult2_Cmult34} {iopath_Amult2_Cmult35} {iopath_Amult2_Cmult36} {iopath_Amult2_Cmult37} {iopath_Amult2_Cmult38} {iopath_Amult2_Cmult39} {iopath_Amult2_Cmult40} {iopath_Amult2_Cmult41} {iopath_Amult2_Cmult42} {iopath_Amult2_Cmult43} {iopath_Amult2_Cmult44} {iopath_Amult2_Cmult45} {iopath_Amult2_Cmult46} {iopath_Amult2_Cmult47} {iopath_Amult2_Cmult48} {iopath_Amult2_Cmult49} {iopath_Amult2_Cmult50} {iopath_Amult2_Cmult51} {iopath_Amult2_Cmult52} {iopath_Amult2_Cmult53} {iopath_Amult2_Cmult54} {iopath_Amult2_Cmult55} {iopath_Amult2_Cmult56} {iopath_Amult2_Cmult57} {iopath_Amult2_Cmult58} {iopath_Amult2_Cmult59} {iopath_Amult2_Cmult60} {iopath_Amult2_Cmult61} {iopath_Amult2_Cmult62} {iopath_Amult2_Cmult63} 0 0 0 {iopath_Amult3_Cmult3} {iopath_Amult3_Cmult4} {iopath_Amult3_Cmult5} {iopath_Amult3_Cmult6} {iopath_Amult3_Cmult7} {iopath_Amult3_Cmult8} {iopath_Amult3_Cmult9} {iopath_Amult3_Cmult10} {iopath_Amult3_Cmult11} {iopath_Amult3_Cmult12} {iopath_Amult3_Cmult13} {iopath_Amult3_Cmult14} {iopath_Amult3_Cmult15} {iopath_Amult3_Cmult16} {iopath_Amult3_Cmult17} {iopath_Amult3_Cmult18} {iopath_Amult3_Cmult19} {iopath_Amult3_Cmult20} {iopath_Amult3_Cmult21} {iopath_Amult3_Cmult22} {iopath_Amult3_Cmult23} {iopath_Amult3_Cmult24} {iopath_Amult3_Cmult25} {iopath_Amult3_Cmult26} {iopath_Amult3_Cmult27} {iopath_Amult3_Cmult28} {iopath_Amult3_Cmult29} {iopath_Amult3_Cmult30} {iopath_Amult3_Cmult31} {iopath_Amult3_Cmult32} {iopath_Amult3_Cmult33} {iopath_Amult3_Cmult34} {iopath_Amult3_Cmult35} {iopath_Amult3_Cmult36} {iopath_Amult3_Cmult37} {iopath_Amult3_Cmult38} {iopath_Amult3_Cmult39} {iopath_Amult3_Cmult40} {iopath_Amult3_Cmult41} {iopath_Amult3_Cmult42} {iopath_Amult3_Cmult43} {iopath_Amult3_Cmult44} {iopath_Amult3_Cmult45} {iopath_Amult3_Cmult46} {iopath_Amult3_Cmult47} {iopath_Amult3_Cmult48} {iopath_Amult3_Cmult49} {iopath_Amult3_Cmult50} {iopath_Amult3_Cmult51} {iopath_Amult3_Cmult52} {iopath_Amult3_Cmult53} {iopath_Amult3_Cmult54} {iopath_Amult3_Cmult55} {iopath_Amult3_Cmult56} {iopath_Amult3_Cmult57} {iopath_Amult3_Cmult58} {iopath_Amult3_Cmult59} {iopath_Amult3_Cmult60} {iopath_Amult3_Cmult61} {iopath_Amult3_Cmult62} {iopath_Amult3_Cmult63} 0 0 0 0 {iopath_Amult4_Cmult4} {iopath_Amult4_Cmult5} {iopath_Amult4_Cmult6} {iopath_Amult4_Cmult7} {iopath_Amult4_Cmult8} {iopath_Amult4_Cmult9} {iopath_Amult4_Cmult10} {iopath_Amult4_Cmult11} {iopath_Amult4_Cmult12} {iopath_Amult4_Cmult13} {iopath_Amult4_Cmult14} {iopath_Amult4_Cmult15} {iopath_Amult4_Cmult16} {iopath_Amult4_Cmult17} {iopath_Amult4_Cmult18} {iopath_Amult4_Cmult19} {iopath_Amult4_Cmult20} {iopath_Amult4_Cmult21} {iopath_Amult4_Cmult22} {iopath_Amult4_Cmult23} {iopath_Amult4_Cmult24} {iopath_Amult4_Cmult25} {iopath_Amult4_Cmult26} {iopath_Amult4_Cmult27} {iopath_Amult4_Cmult28} {iopath_Amult4_Cmult29} {iopath_Amult4_Cmult30} {iopath_Amult4_Cmult31} {iopath_Amult4_Cmult32} {iopath_Amult4_Cmult33} {iopath_Amult4_Cmult34} {iopath_Amult4_Cmult35} {iopath_Amult4_Cmult36} {iopath_Amult4_Cmult37} {iopath_Amult4_Cmult38} {iopath_Amult4_Cmult39} {iopath_Amult4_Cmult40} {iopath_Amult4_Cmult41} {iopath_Amult4_Cmult42} {iopath_Amult4_Cmult43} {iopath_Amult4_Cmult44} {iopath_Amult4_Cmult45} {iopath_Amult4_Cmult46} {iopath_Amult4_Cmult47} {iopath_Amult4_Cmult48} {iopath_Amult4_Cmult49} {iopath_Amult4_Cmult50} {iopath_Amult4_Cmult51} {iopath_Amult4_Cmult52} {iopath_Amult4_Cmult53} {iopath_Amult4_Cmult54} {iopath_Amult4_Cmult55} {iopath_Amult4_Cmult56} {iopath_Amult4_Cmult57} {iopath_Amult4_Cmult58} {iopath_Amult4_Cmult59} {iopath_Amult4_Cmult60} {iopath_Amult4_Cmult61} {iopath_Amult4_Cmult62} {iopath_Amult4_Cmult63} 0 0 0 0 0 {iopath_Amult5_Cmult5} {iopath_Amult5_Cmult6} {iopath_Amult5_Cmult7} {iopath_Amult5_Cmult8} {iopath_Amult5_Cmult9} {iopath_Amult5_Cmult10} {iopath_Amult5_Cmult11} {iopath_Amult5_Cmult12} {iopath_Amult5_Cmult13} {iopath_Amult5_Cmult14} {iopath_Amult5_Cmult15} {iopath_Amult5_Cmult16} {iopath_Amult5_Cmult17} {iopath_Amult5_Cmult18} {iopath_Amult5_Cmult19} {iopath_Amult5_Cmult20} {iopath_Amult5_Cmult21} {iopath_Amult5_Cmult22} {iopath_Amult5_Cmult23} {iopath_Amult5_Cmult24} {iopath_Amult5_Cmult25} {iopath_Amult5_Cmult26} {iopath_Amult5_Cmult27} {iopath_Amult5_Cmult28} {iopath_Amult5_Cmult29} {iopath_Amult5_Cmult30} {iopath_Amult5_Cmult31} {iopath_Amult5_Cmult32} {iopath_Amult5_Cmult33} {iopath_Amult5_Cmult34} {iopath_Amult5_Cmult35} {iopath_Amult5_Cmult36} {iopath_Amult5_Cmult37} {iopath_Amult5_Cmult38} {iopath_Amult5_Cmult39} {iopath_Amult5_Cmult40} {iopath_Amult5_Cmult41} {iopath_Amult5_Cmult42} {iopath_Amult5_Cmult43} {iopath_Amult5_Cmult44} {iopath_Amult5_Cmult45} {iopath_Amult5_Cmult46} {iopath_Amult5_Cmult47} {iopath_Amult5_Cmult48} {iopath_Amult5_Cmult49} {iopath_Amult5_Cmult50} {iopath_Amult5_Cmult51} {iopath_Amult5_Cmult52} {iopath_Amult5_Cmult53} {iopath_Amult5_Cmult54} {iopath_Amult5_Cmult55} {iopath_Amult5_Cmult56} {iopath_Amult5_Cmult57} {iopath_Amult5_Cmult58} {iopath_Amult5_Cmult59} {iopath_Amult5_Cmult60} {iopath_Amult5_Cmult61} {iopath_Amult5_Cmult62} {iopath_Amult5_Cmult63} 0 0 0 0 0 0 {iopath_Amult6_Cmult6} {iopath_Amult6_Cmult7} {iopath_Amult6_Cmult8} {iopath_Amult6_Cmult9} {iopath_Amult6_Cmult10} {iopath_Amult6_Cmult11} {iopath_Amult6_Cmult12} {iopath_Amult6_Cmult13} {iopath_Amult6_Cmult14} {iopath_Amult6_Cmult15} {iopath_Amult6_Cmult16} {iopath_Amult6_Cmult17} {iopath_Amult6_Cmult18} {iopath_Amult6_Cmult19} {iopath_Amult6_Cmult20} {iopath_Amult6_Cmult21} {iopath_Amult6_Cmult22} {iopath_Amult6_Cmult23} {iopath_Amult6_Cmult24} {iopath_Amult6_Cmult25} {iopath_Amult6_Cmult26} {iopath_Amult6_Cmult27} {iopath_Amult6_Cmult28} {iopath_Amult6_Cmult29} {iopath_Amult6_Cmult30} {iopath_Amult6_Cmult31} {iopath_Amult6_Cmult32} {iopath_Amult6_Cmult33} {iopath_Amult6_Cmult34} {iopath_Amult6_Cmult35} {iopath_Amult6_Cmult36} {iopath_Amult6_Cmult37} {iopath_Amult6_Cmult38} {iopath_Amult6_Cmult39} {iopath_Amult6_Cmult40} {iopath_Amult6_Cmult41} {iopath_Amult6_Cmult42} {iopath_Amult6_Cmult43} {iopath_Amult6_Cmult44} {iopath_Amult6_Cmult45} {iopath_Amult6_Cmult46} {iopath_Amult6_Cmult47} {iopath_Amult6_Cmult48} {iopath_Amult6_Cmult49} {iopath_Amult6_Cmult50} {iopath_Amult6_Cmult51} {iopath_Amult6_Cmult52} {iopath_Amult6_Cmult53} {iopath_Amult6_Cmult54} {iopath_Amult6_Cmult55} {iopath_Amult6_Cmult56} {iopath_Amult6_Cmult57} {iopath_Amult6_Cmult58} {iopath_Amult6_Cmult59} {iopath_Amult6_Cmult60} {iopath_Amult6_Cmult61} {iopath_Amult6_Cmult62} {iopath_Amult6_Cmult63} 0 0 0 0 0 0 0 {iopath_Amult7_Cmult7} {iopath_Amult7_Cmult8} {iopath_Amult7_Cmult9} {iopath_Amult7_Cmult10} {iopath_Amult7_Cmult11} {iopath_Amult7_Cmult12} {iopath_Amult7_Cmult13} {iopath_Amult7_Cmult14} {iopath_Amult7_Cmult15} {iopath_Amult7_Cmult16} {iopath_Amult7_Cmult17} {iopath_Amult7_Cmult18} {iopath_Amult7_Cmult19} {iopath_Amult7_Cmult20} {iopath_Amult7_Cmult21} {iopath_Amult7_Cmult22} {iopath_Amult7_Cmult23} {iopath_Amult7_Cmult24} {iopath_Amult7_Cmult25} {iopath_Amult7_Cmult26} {iopath_Amult7_Cmult27} {iopath_Amult7_Cmult28} {iopath_Amult7_Cmult29} {iopath_Amult7_Cmult30} {iopath_Amult7_Cmult31} {iopath_Amult7_Cmult32} {iopath_Amult7_Cmult33} {iopath_Amult7_Cmult34} {iopath_Amult7_Cmult35} {iopath_Amult7_Cmult36} {iopath_Amult7_Cmult37} {iopath_Amult7_Cmult38} {iopath_Amult7_Cmult39} {iopath_Amult7_Cmult40} {iopath_Amult7_Cmult41} {iopath_Amult7_Cmult42} {iopath_Amult7_Cmult43} {iopath_Amult7_Cmult44} {iopath_Amult7_Cmult45} {iopath_Amult7_Cmult46} {iopath_Amult7_Cmult47} {iopath_Amult7_Cmult48} {iopath_Amult7_Cmult49} {iopath_Amult7_Cmult50} {iopath_Amult7_Cmult51} {iopath_Amult7_Cmult52} {iopath_Amult7_Cmult53} {iopath_Amult7_Cmult54} {iopath_Amult7_Cmult55} {iopath_Amult7_Cmult56} {iopath_Amult7_Cmult57} {iopath_Amult7_Cmult58} {iopath_Amult7_Cmult59} {iopath_Amult7_Cmult60} {iopath_Amult7_Cmult61} {iopath_Amult7_Cmult62} {iopath_Amult7_Cmult63} 0 0 0 0 0 0 0 0 {iopath_Amult8_Cmult8} {iopath_Amult8_Cmult9} {iopath_Amult8_Cmult10} {iopath_Amult8_Cmult11} {iopath_Amult8_Cmult12} {iopath_Amult8_Cmult13} {iopath_Amult8_Cmult14} {iopath_Amult8_Cmult15} {iopath_Amult8_Cmult16} {iopath_Amult8_Cmult17} {iopath_Amult8_Cmult18} {iopath_Amult8_Cmult19} {iopath_Amult8_Cmult20} {iopath_Amult8_Cmult21} {iopath_Amult8_Cmult22} {iopath_Amult8_Cmult23} {iopath_Amult8_Cmult24} {iopath_Amult8_Cmult25} {iopath_Amult8_Cmult26} {iopath_Amult8_Cmult27} {iopath_Amult8_Cmult28} {iopath_Amult8_Cmult29} {iopath_Amult8_Cmult30} {iopath_Amult8_Cmult31} {iopath_Amult8_Cmult32} {iopath_Amult8_Cmult33} {iopath_Amult8_Cmult34} {iopath_Amult8_Cmult35} {iopath_Amult8_Cmult36} {iopath_Amult8_Cmult37} {iopath_Amult8_Cmult38} {iopath_Amult8_Cmult39} {iopath_Amult8_Cmult40} {iopath_Amult8_Cmult41} {iopath_Amult8_Cmult42} {iopath_Amult8_Cmult43} {iopath_Amult8_Cmult44} {iopath_Amult8_Cmult45} {iopath_Amult8_Cmult46} {iopath_Amult8_Cmult47} {iopath_Amult8_Cmult48} {iopath_Amult8_Cmult49} {iopath_Amult8_Cmult50} {iopath_Amult8_Cmult51} {iopath_Amult8_Cmult52} {iopath_Amult8_Cmult53} {iopath_Amult8_Cmult54} {iopath_Amult8_Cmult55} {iopath_Amult8_Cmult56} {iopath_Amult8_Cmult57} {iopath_Amult8_Cmult58} {iopath_Amult8_Cmult59} {iopath_Amult8_Cmult60} {iopath_Amult8_Cmult61} {iopath_Amult8_Cmult62} {iopath_Amult8_Cmult63} 0 0 0 0 0 0 0 0 0 {iopath_Amult9_Cmult9} {iopath_Amult9_Cmult10} {iopath_Amult9_Cmult11} {iopath_Amult9_Cmult12} {iopath_Amult9_Cmult13} {iopath_Amult9_Cmult14} {iopath_Amult9_Cmult15} {iopath_Amult9_Cmult16} {iopath_Amult9_Cmult17} {iopath_Amult9_Cmult18} {iopath_Amult9_Cmult19} {iopath_Amult9_Cmult20} {iopath_Amult9_Cmult21} {iopath_Amult9_Cmult22} {iopath_Amult9_Cmult23} {iopath_Amult9_Cmult24} {iopath_Amult9_Cmult25} {iopath_Amult9_Cmult26} {iopath_Amult9_Cmult27} {iopath_Amult9_Cmult28} {iopath_Amult9_Cmult29} {iopath_Amult9_Cmult30} {iopath_Amult9_Cmult31} {iopath_Amult9_Cmult32} {iopath_Amult9_Cmult33} {iopath_Amult9_Cmult34} {iopath_Amult9_Cmult35} {iopath_Amult9_Cmult36} {iopath_Amult9_Cmult37} {iopath_Amult9_Cmult38} {iopath_Amult9_Cmult39} {iopath_Amult9_Cmult40} {iopath_Amult9_Cmult41} {iopath_Amult9_Cmult42} {iopath_Amult9_Cmult43} {iopath_Amult9_Cmult44} {iopath_Amult9_Cmult45} {iopath_Amult9_Cmult46} {iopath_Amult9_Cmult47} {iopath_Amult9_Cmult48} {iopath_Amult9_Cmult49} {iopath_Amult9_Cmult50} {iopath_Amult9_Cmult51} {iopath_Amult9_Cmult52} {iopath_Amult9_Cmult53} {iopath_Amult9_Cmult54} {iopath_Amult9_Cmult55} {iopath_Amult9_Cmult56} {iopath_Amult9_Cmult57} {iopath_Amult9_Cmult58} {iopath_Amult9_Cmult59} {iopath_Amult9_Cmult60} {iopath_Amult9_Cmult61} {iopath_Amult9_Cmult62} {iopath_Amult9_Cmult63} 0 0 0 0 0 0 0 0 0 0 {iopath_Amult10_Cmult10} {iopath_Amult10_Cmult11} {iopath_Amult10_Cmult12} {iopath_Amult10_Cmult13} {iopath_Amult10_Cmult14} {iopath_Amult10_Cmult15} {iopath_Amult10_Cmult16} {iopath_Amult10_Cmult17} {iopath_Amult10_Cmult18} {iopath_Amult10_Cmult19} {iopath_Amult10_Cmult20} {iopath_Amult10_Cmult21} {iopath_Amult10_Cmult22} {iopath_Amult10_Cmult23} {iopath_Amult10_Cmult24} {iopath_Amult10_Cmult25} {iopath_Amult10_Cmult26} {iopath_Amult10_Cmult27} {iopath_Amult10_Cmult28} {iopath_Amult10_Cmult29} {iopath_Amult10_Cmult30} {iopath_Amult10_Cmult31} {iopath_Amult10_Cmult32} {iopath_Amult10_Cmult33} {iopath_Amult10_Cmult34} {iopath_Amult10_Cmult35} {iopath_Amult10_Cmult36} {iopath_Amult10_Cmult37} {iopath_Amult10_Cmult38} {iopath_Amult10_Cmult39} {iopath_Amult10_Cmult40} {iopath_Amult10_Cmult41} {iopath_Amult10_Cmult42} {iopath_Amult10_Cmult43} {iopath_Amult10_Cmult44} {iopath_Amult10_Cmult45} {iopath_Amult10_Cmult46} {iopath_Amult10_Cmult47} {iopath_Amult10_Cmult48} {iopath_Amult10_Cmult49} {iopath_Amult10_Cmult50} {iopath_Amult10_Cmult51} {iopath_Amult10_Cmult52} {iopath_Amult10_Cmult53} {iopath_Amult10_Cmult54} {iopath_Amult10_Cmult55} {iopath_Amult10_Cmult56} {iopath_Amult10_Cmult57} {iopath_Amult10_Cmult58} {iopath_Amult10_Cmult59} {iopath_Amult10_Cmult60} {iopath_Amult10_Cmult61} {iopath_Amult10_Cmult62} {iopath_Amult10_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult11_Cmult11} {iopath_Amult11_Cmult12} {iopath_Amult11_Cmult13} {iopath_Amult11_Cmult14} {iopath_Amult11_Cmult15} {iopath_Amult11_Cmult16} {iopath_Amult11_Cmult17} {iopath_Amult11_Cmult18} {iopath_Amult11_Cmult19} {iopath_Amult11_Cmult20} {iopath_Amult11_Cmult21} {iopath_Amult11_Cmult22} {iopath_Amult11_Cmult23} {iopath_Amult11_Cmult24} {iopath_Amult11_Cmult25} {iopath_Amult11_Cmult26} {iopath_Amult11_Cmult27} {iopath_Amult11_Cmult28} {iopath_Amult11_Cmult29} {iopath_Amult11_Cmult30} {iopath_Amult11_Cmult31} {iopath_Amult11_Cmult32} {iopath_Amult11_Cmult33} {iopath_Amult11_Cmult34} {iopath_Amult11_Cmult35} {iopath_Amult11_Cmult36} {iopath_Amult11_Cmult37} {iopath_Amult11_Cmult38} {iopath_Amult11_Cmult39} {iopath_Amult11_Cmult40} {iopath_Amult11_Cmult41} {iopath_Amult11_Cmult42} {iopath_Amult11_Cmult43} {iopath_Amult11_Cmult44} {iopath_Amult11_Cmult45} {iopath_Amult11_Cmult46} {iopath_Amult11_Cmult47} {iopath_Amult11_Cmult48} {iopath_Amult11_Cmult49} {iopath_Amult11_Cmult50} {iopath_Amult11_Cmult51} {iopath_Amult11_Cmult52} {iopath_Amult11_Cmult53} {iopath_Amult11_Cmult54} {iopath_Amult11_Cmult55} {iopath_Amult11_Cmult56} {iopath_Amult11_Cmult57} {iopath_Amult11_Cmult58} {iopath_Amult11_Cmult59} {iopath_Amult11_Cmult60} {iopath_Amult11_Cmult61} {iopath_Amult11_Cmult62} {iopath_Amult11_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult12_Cmult12} {iopath_Amult12_Cmult13} {iopath_Amult12_Cmult14} {iopath_Amult12_Cmult15} {iopath_Amult12_Cmult16} {iopath_Amult12_Cmult17} {iopath_Amult12_Cmult18} {iopath_Amult12_Cmult19} {iopath_Amult12_Cmult20} {iopath_Amult12_Cmult21} {iopath_Amult12_Cmult22} {iopath_Amult12_Cmult23} {iopath_Amult12_Cmult24} {iopath_Amult12_Cmult25} {iopath_Amult12_Cmult26} {iopath_Amult12_Cmult27} {iopath_Amult12_Cmult28} {iopath_Amult12_Cmult29} {iopath_Amult12_Cmult30} {iopath_Amult12_Cmult31} {iopath_Amult12_Cmult32} {iopath_Amult12_Cmult33} {iopath_Amult12_Cmult34} {iopath_Amult12_Cmult35} {iopath_Amult12_Cmult36} {iopath_Amult12_Cmult37} {iopath_Amult12_Cmult38} {iopath_Amult12_Cmult39} {iopath_Amult12_Cmult40} {iopath_Amult12_Cmult41} {iopath_Amult12_Cmult42} {iopath_Amult12_Cmult43} {iopath_Amult12_Cmult44} {iopath_Amult12_Cmult45} {iopath_Amult12_Cmult46} {iopath_Amult12_Cmult47} {iopath_Amult12_Cmult48} {iopath_Amult12_Cmult49} {iopath_Amult12_Cmult50} {iopath_Amult12_Cmult51} {iopath_Amult12_Cmult52} {iopath_Amult12_Cmult53} {iopath_Amult12_Cmult54} {iopath_Amult12_Cmult55} {iopath_Amult12_Cmult56} {iopath_Amult12_Cmult57} {iopath_Amult12_Cmult58} {iopath_Amult12_Cmult59} {iopath_Amult12_Cmult60} {iopath_Amult12_Cmult61} {iopath_Amult12_Cmult62} {iopath_Amult12_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult13_Cmult13} {iopath_Amult13_Cmult14} {iopath_Amult13_Cmult15} {iopath_Amult13_Cmult16} {iopath_Amult13_Cmult17} {iopath_Amult13_Cmult18} {iopath_Amult13_Cmult19} {iopath_Amult13_Cmult20} {iopath_Amult13_Cmult21} {iopath_Amult13_Cmult22} {iopath_Amult13_Cmult23} {iopath_Amult13_Cmult24} {iopath_Amult13_Cmult25} {iopath_Amult13_Cmult26} {iopath_Amult13_Cmult27} {iopath_Amult13_Cmult28} {iopath_Amult13_Cmult29} {iopath_Amult13_Cmult30} {iopath_Amult13_Cmult31} {iopath_Amult13_Cmult32} {iopath_Amult13_Cmult33} {iopath_Amult13_Cmult34} {iopath_Amult13_Cmult35} {iopath_Amult13_Cmult36} {iopath_Amult13_Cmult37} {iopath_Amult13_Cmult38} {iopath_Amult13_Cmult39} {iopath_Amult13_Cmult40} {iopath_Amult13_Cmult41} {iopath_Amult13_Cmult42} {iopath_Amult13_Cmult43} {iopath_Amult13_Cmult44} {iopath_Amult13_Cmult45} {iopath_Amult13_Cmult46} {iopath_Amult13_Cmult47} {iopath_Amult13_Cmult48} {iopath_Amult13_Cmult49} {iopath_Amult13_Cmult50} {iopath_Amult13_Cmult51} {iopath_Amult13_Cmult52} {iopath_Amult13_Cmult53} {iopath_Amult13_Cmult54} {iopath_Amult13_Cmult55} {iopath_Amult13_Cmult56} {iopath_Amult13_Cmult57} {iopath_Amult13_Cmult58} {iopath_Amult13_Cmult59} {iopath_Amult13_Cmult60} {iopath_Amult13_Cmult61} {iopath_Amult13_Cmult62} {iopath_Amult13_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult14_Cmult14} {iopath_Amult14_Cmult15} {iopath_Amult14_Cmult16} {iopath_Amult14_Cmult17} {iopath_Amult14_Cmult18} {iopath_Amult14_Cmult19} {iopath_Amult14_Cmult20} {iopath_Amult14_Cmult21} {iopath_Amult14_Cmult22} {iopath_Amult14_Cmult23} {iopath_Amult14_Cmult24} {iopath_Amult14_Cmult25} {iopath_Amult14_Cmult26} {iopath_Amult14_Cmult27} {iopath_Amult14_Cmult28} {iopath_Amult14_Cmult29} {iopath_Amult14_Cmult30} {iopath_Amult14_Cmult31} {iopath_Amult14_Cmult32} {iopath_Amult14_Cmult33} {iopath_Amult14_Cmult34} {iopath_Amult14_Cmult35} {iopath_Amult14_Cmult36} {iopath_Amult14_Cmult37} {iopath_Amult14_Cmult38} {iopath_Amult14_Cmult39} {iopath_Amult14_Cmult40} {iopath_Amult14_Cmult41} {iopath_Amult14_Cmult42} {iopath_Amult14_Cmult43} {iopath_Amult14_Cmult44} {iopath_Amult14_Cmult45} {iopath_Amult14_Cmult46} {iopath_Amult14_Cmult47} {iopath_Amult14_Cmult48} {iopath_Amult14_Cmult49} {iopath_Amult14_Cmult50} {iopath_Amult14_Cmult51} {iopath_Amult14_Cmult52} {iopath_Amult14_Cmult53} {iopath_Amult14_Cmult54} {iopath_Amult14_Cmult55} {iopath_Amult14_Cmult56} {iopath_Amult14_Cmult57} {iopath_Amult14_Cmult58} {iopath_Amult14_Cmult59} {iopath_Amult14_Cmult60} {iopath_Amult14_Cmult61} {iopath_Amult14_Cmult62} {iopath_Amult14_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult15_Cmult15} {iopath_Amult15_Cmult16} {iopath_Amult15_Cmult17} {iopath_Amult15_Cmult18} {iopath_Amult15_Cmult19} {iopath_Amult15_Cmult20} {iopath_Amult15_Cmult21} {iopath_Amult15_Cmult22} {iopath_Amult15_Cmult23} {iopath_Amult15_Cmult24} {iopath_Amult15_Cmult25} {iopath_Amult15_Cmult26} {iopath_Amult15_Cmult27} {iopath_Amult15_Cmult28} {iopath_Amult15_Cmult29} {iopath_Amult15_Cmult30} {iopath_Amult15_Cmult31} {iopath_Amult15_Cmult32} {iopath_Amult15_Cmult33} {iopath_Amult15_Cmult34} {iopath_Amult15_Cmult35} {iopath_Amult15_Cmult36} {iopath_Amult15_Cmult37} {iopath_Amult15_Cmult38} {iopath_Amult15_Cmult39} {iopath_Amult15_Cmult40} {iopath_Amult15_Cmult41} {iopath_Amult15_Cmult42} {iopath_Amult15_Cmult43} {iopath_Amult15_Cmult44} {iopath_Amult15_Cmult45} {iopath_Amult15_Cmult46} {iopath_Amult15_Cmult47} {iopath_Amult15_Cmult48} {iopath_Amult15_Cmult49} {iopath_Amult15_Cmult50} {iopath_Amult15_Cmult51} {iopath_Amult15_Cmult52} {iopath_Amult15_Cmult53} {iopath_Amult15_Cmult54} {iopath_Amult15_Cmult55} {iopath_Amult15_Cmult56} {iopath_Amult15_Cmult57} {iopath_Amult15_Cmult58} {iopath_Amult15_Cmult59} {iopath_Amult15_Cmult60} {iopath_Amult15_Cmult61} {iopath_Amult15_Cmult62} {iopath_Amult15_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult16_Cmult16} {iopath_Amult16_Cmult17} {iopath_Amult16_Cmult18} {iopath_Amult16_Cmult19} {iopath_Amult16_Cmult20} {iopath_Amult16_Cmult21} {iopath_Amult16_Cmult22} {iopath_Amult16_Cmult23} {iopath_Amult16_Cmult24} {iopath_Amult16_Cmult25} {iopath_Amult16_Cmult26} {iopath_Amult16_Cmult27} {iopath_Amult16_Cmult28} {iopath_Amult16_Cmult29} {iopath_Amult16_Cmult30} {iopath_Amult16_Cmult31} {iopath_Amult16_Cmult32} {iopath_Amult16_Cmult33} {iopath_Amult16_Cmult34} {iopath_Amult16_Cmult35} {iopath_Amult16_Cmult36} {iopath_Amult16_Cmult37} {iopath_Amult16_Cmult38} {iopath_Amult16_Cmult39} {iopath_Amult16_Cmult40} {iopath_Amult16_Cmult41} {iopath_Amult16_Cmult42} {iopath_Amult16_Cmult43} {iopath_Amult16_Cmult44} {iopath_Amult16_Cmult45} {iopath_Amult16_Cmult46} {iopath_Amult16_Cmult47} {iopath_Amult16_Cmult48} {iopath_Amult16_Cmult49} {iopath_Amult16_Cmult50} {iopath_Amult16_Cmult51} {iopath_Amult16_Cmult52} {iopath_Amult16_Cmult53} {iopath_Amult16_Cmult54} {iopath_Amult16_Cmult55} {iopath_Amult16_Cmult56} {iopath_Amult16_Cmult57} {iopath_Amult16_Cmult58} {iopath_Amult16_Cmult59} {iopath_Amult16_Cmult60} {iopath_Amult16_Cmult61} {iopath_Amult16_Cmult62} {iopath_Amult16_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult17_Cmult17} {iopath_Amult17_Cmult18} {iopath_Amult17_Cmult19} {iopath_Amult17_Cmult20} {iopath_Amult17_Cmult21} {iopath_Amult17_Cmult22} {iopath_Amult17_Cmult23} {iopath_Amult17_Cmult24} {iopath_Amult17_Cmult25} {iopath_Amult17_Cmult26} {iopath_Amult17_Cmult27} {iopath_Amult17_Cmult28} {iopath_Amult17_Cmult29} {iopath_Amult17_Cmult30} {iopath_Amult17_Cmult31} {iopath_Amult17_Cmult32} {iopath_Amult17_Cmult33} {iopath_Amult17_Cmult34} {iopath_Amult17_Cmult35} {iopath_Amult17_Cmult36} {iopath_Amult17_Cmult37} {iopath_Amult17_Cmult38} {iopath_Amult17_Cmult39} {iopath_Amult17_Cmult40} {iopath_Amult17_Cmult41} {iopath_Amult17_Cmult42} {iopath_Amult17_Cmult43} {iopath_Amult17_Cmult44} {iopath_Amult17_Cmult45} {iopath_Amult17_Cmult46} {iopath_Amult17_Cmult47} {iopath_Amult17_Cmult48} {iopath_Amult17_Cmult49} {iopath_Amult17_Cmult50} {iopath_Amult17_Cmult51} {iopath_Amult17_Cmult52} {iopath_Amult17_Cmult53} {iopath_Amult17_Cmult54} {iopath_Amult17_Cmult55} {iopath_Amult17_Cmult56} {iopath_Amult17_Cmult57} {iopath_Amult17_Cmult58} {iopath_Amult17_Cmult59} {iopath_Amult17_Cmult60} {iopath_Amult17_Cmult61} {iopath_Amult17_Cmult62} {iopath_Amult17_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult18_Cmult18} {iopath_Amult18_Cmult19} {iopath_Amult18_Cmult20} {iopath_Amult18_Cmult21} {iopath_Amult18_Cmult22} {iopath_Amult18_Cmult23} {iopath_Amult18_Cmult24} {iopath_Amult18_Cmult25} {iopath_Amult18_Cmult26} {iopath_Amult18_Cmult27} {iopath_Amult18_Cmult28} {iopath_Amult18_Cmult29} {iopath_Amult18_Cmult30} {iopath_Amult18_Cmult31} {iopath_Amult18_Cmult32} {iopath_Amult18_Cmult33} {iopath_Amult18_Cmult34} {iopath_Amult18_Cmult35} {iopath_Amult18_Cmult36} {iopath_Amult18_Cmult37} {iopath_Amult18_Cmult38} {iopath_Amult18_Cmult39} {iopath_Amult18_Cmult40} {iopath_Amult18_Cmult41} {iopath_Amult18_Cmult42} {iopath_Amult18_Cmult43} {iopath_Amult18_Cmult44} {iopath_Amult18_Cmult45} {iopath_Amult18_Cmult46} {iopath_Amult18_Cmult47} {iopath_Amult18_Cmult48} {iopath_Amult18_Cmult49} {iopath_Amult18_Cmult50} {iopath_Amult18_Cmult51} {iopath_Amult18_Cmult52} {iopath_Amult18_Cmult53} {iopath_Amult18_Cmult54} {iopath_Amult18_Cmult55} {iopath_Amult18_Cmult56} {iopath_Amult18_Cmult57} {iopath_Amult18_Cmult58} {iopath_Amult18_Cmult59} {iopath_Amult18_Cmult60} {iopath_Amult18_Cmult61} {iopath_Amult18_Cmult62} {iopath_Amult18_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult19_Cmult19} {iopath_Amult19_Cmult20} {iopath_Amult19_Cmult21} {iopath_Amult19_Cmult22} {iopath_Amult19_Cmult23} {iopath_Amult19_Cmult24} {iopath_Amult19_Cmult25} {iopath_Amult19_Cmult26} {iopath_Amult19_Cmult27} {iopath_Amult19_Cmult28} {iopath_Amult19_Cmult29} {iopath_Amult19_Cmult30} {iopath_Amult19_Cmult31} {iopath_Amult19_Cmult32} {iopath_Amult19_Cmult33} {iopath_Amult19_Cmult34} {iopath_Amult19_Cmult35} {iopath_Amult19_Cmult36} {iopath_Amult19_Cmult37} {iopath_Amult19_Cmult38} {iopath_Amult19_Cmult39} {iopath_Amult19_Cmult40} {iopath_Amult19_Cmult41} {iopath_Amult19_Cmult42} {iopath_Amult19_Cmult43} {iopath_Amult19_Cmult44} {iopath_Amult19_Cmult45} {iopath_Amult19_Cmult46} {iopath_Amult19_Cmult47} {iopath_Amult19_Cmult48} {iopath_Amult19_Cmult49} {iopath_Amult19_Cmult50} {iopath_Amult19_Cmult51} {iopath_Amult19_Cmult52} {iopath_Amult19_Cmult53} {iopath_Amult19_Cmult54} {iopath_Amult19_Cmult55} {iopath_Amult19_Cmult56} {iopath_Amult19_Cmult57} {iopath_Amult19_Cmult58} {iopath_Amult19_Cmult59} {iopath_Amult19_Cmult60} {iopath_Amult19_Cmult61} {iopath_Amult19_Cmult62} {iopath_Amult19_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult20_Cmult20} {iopath_Amult20_Cmult21} {iopath_Amult20_Cmult22} {iopath_Amult20_Cmult23} {iopath_Amult20_Cmult24} {iopath_Amult20_Cmult25} {iopath_Amult20_Cmult26} {iopath_Amult20_Cmult27} {iopath_Amult20_Cmult28} {iopath_Amult20_Cmult29} {iopath_Amult20_Cmult30} {iopath_Amult20_Cmult31} {iopath_Amult20_Cmult32} {iopath_Amult20_Cmult33} {iopath_Amult20_Cmult34} {iopath_Amult20_Cmult35} {iopath_Amult20_Cmult36} {iopath_Amult20_Cmult37} {iopath_Amult20_Cmult38} {iopath_Amult20_Cmult39} {iopath_Amult20_Cmult40} {iopath_Amult20_Cmult41} {iopath_Amult20_Cmult42} {iopath_Amult20_Cmult43} {iopath_Amult20_Cmult44} {iopath_Amult20_Cmult45} {iopath_Amult20_Cmult46} {iopath_Amult20_Cmult47} {iopath_Amult20_Cmult48} {iopath_Amult20_Cmult49} {iopath_Amult20_Cmult50} {iopath_Amult20_Cmult51} {iopath_Amult20_Cmult52} {iopath_Amult20_Cmult53} {iopath_Amult20_Cmult54} {iopath_Amult20_Cmult55} {iopath_Amult20_Cmult56} {iopath_Amult20_Cmult57} {iopath_Amult20_Cmult58} {iopath_Amult20_Cmult59} {iopath_Amult20_Cmult60} {iopath_Amult20_Cmult61} {iopath_Amult20_Cmult62} {iopath_Amult20_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult21_Cmult21} {iopath_Amult21_Cmult22} {iopath_Amult21_Cmult23} {iopath_Amult21_Cmult24} {iopath_Amult21_Cmult25} {iopath_Amult21_Cmult26} {iopath_Amult21_Cmult27} {iopath_Amult21_Cmult28} {iopath_Amult21_Cmult29} {iopath_Amult21_Cmult30} {iopath_Amult21_Cmult31} {iopath_Amult21_Cmult32} {iopath_Amult21_Cmult33} {iopath_Amult21_Cmult34} {iopath_Amult21_Cmult35} {iopath_Amult21_Cmult36} {iopath_Amult21_Cmult37} {iopath_Amult21_Cmult38} {iopath_Amult21_Cmult39} {iopath_Amult21_Cmult40} {iopath_Amult21_Cmult41} {iopath_Amult21_Cmult42} {iopath_Amult21_Cmult43} {iopath_Amult21_Cmult44} {iopath_Amult21_Cmult45} {iopath_Amult21_Cmult46} {iopath_Amult21_Cmult47} {iopath_Amult21_Cmult48} {iopath_Amult21_Cmult49} {iopath_Amult21_Cmult50} {iopath_Amult21_Cmult51} {iopath_Amult21_Cmult52} {iopath_Amult21_Cmult53} {iopath_Amult21_Cmult54} {iopath_Amult21_Cmult55} {iopath_Amult21_Cmult56} {iopath_Amult21_Cmult57} {iopath_Amult21_Cmult58} {iopath_Amult21_Cmult59} {iopath_Amult21_Cmult60} {iopath_Amult21_Cmult61} {iopath_Amult21_Cmult62} {iopath_Amult21_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult22_Cmult22} {iopath_Amult22_Cmult23} {iopath_Amult22_Cmult24} {iopath_Amult22_Cmult25} {iopath_Amult22_Cmult26} {iopath_Amult22_Cmult27} {iopath_Amult22_Cmult28} {iopath_Amult22_Cmult29} {iopath_Amult22_Cmult30} {iopath_Amult22_Cmult31} {iopath_Amult22_Cmult32} {iopath_Amult22_Cmult33} {iopath_Amult22_Cmult34} {iopath_Amult22_Cmult35} {iopath_Amult22_Cmult36} {iopath_Amult22_Cmult37} {iopath_Amult22_Cmult38} {iopath_Amult22_Cmult39} {iopath_Amult22_Cmult40} {iopath_Amult22_Cmult41} {iopath_Amult22_Cmult42} {iopath_Amult22_Cmult43} {iopath_Amult22_Cmult44} {iopath_Amult22_Cmult45} {iopath_Amult22_Cmult46} {iopath_Amult22_Cmult47} {iopath_Amult22_Cmult48} {iopath_Amult22_Cmult49} {iopath_Amult22_Cmult50} {iopath_Amult22_Cmult51} {iopath_Amult22_Cmult52} {iopath_Amult22_Cmult53} {iopath_Amult22_Cmult54} {iopath_Amult22_Cmult55} {iopath_Amult22_Cmult56} {iopath_Amult22_Cmult57} {iopath_Amult22_Cmult58} {iopath_Amult22_Cmult59} {iopath_Amult22_Cmult60} {iopath_Amult22_Cmult61} {iopath_Amult22_Cmult62} {iopath_Amult22_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult23_Cmult23} {iopath_Amult23_Cmult24} {iopath_Amult23_Cmult25} {iopath_Amult23_Cmult26} {iopath_Amult23_Cmult27} {iopath_Amult23_Cmult28} {iopath_Amult23_Cmult29} {iopath_Amult23_Cmult30} {iopath_Amult23_Cmult31} {iopath_Amult23_Cmult32} {iopath_Amult23_Cmult33} {iopath_Amult23_Cmult34} {iopath_Amult23_Cmult35} {iopath_Amult23_Cmult36} {iopath_Amult23_Cmult37} {iopath_Amult23_Cmult38} {iopath_Amult23_Cmult39} {iopath_Amult23_Cmult40} {iopath_Amult23_Cmult41} {iopath_Amult23_Cmult42} {iopath_Amult23_Cmult43} {iopath_Amult23_Cmult44} {iopath_Amult23_Cmult45} {iopath_Amult23_Cmult46} {iopath_Amult23_Cmult47} {iopath_Amult23_Cmult48} {iopath_Amult23_Cmult49} {iopath_Amult23_Cmult50} {iopath_Amult23_Cmult51} {iopath_Amult23_Cmult52} {iopath_Amult23_Cmult53} {iopath_Amult23_Cmult54} {iopath_Amult23_Cmult55} {iopath_Amult23_Cmult56} {iopath_Amult23_Cmult57} {iopath_Amult23_Cmult58} {iopath_Amult23_Cmult59} {iopath_Amult23_Cmult60} {iopath_Amult23_Cmult61} {iopath_Amult23_Cmult62} {iopath_Amult23_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult24_Cmult24} {iopath_Amult24_Cmult25} {iopath_Amult24_Cmult26} {iopath_Amult24_Cmult27} {iopath_Amult24_Cmult28} {iopath_Amult24_Cmult29} {iopath_Amult24_Cmult30} {iopath_Amult24_Cmult31} {iopath_Amult24_Cmult32} {iopath_Amult24_Cmult33} {iopath_Amult24_Cmult34} {iopath_Amult24_Cmult35} {iopath_Amult24_Cmult36} {iopath_Amult24_Cmult37} {iopath_Amult24_Cmult38} {iopath_Amult24_Cmult39} {iopath_Amult24_Cmult40} {iopath_Amult24_Cmult41} {iopath_Amult24_Cmult42} {iopath_Amult24_Cmult43} {iopath_Amult24_Cmult44} {iopath_Amult24_Cmult45} {iopath_Amult24_Cmult46} {iopath_Amult24_Cmult47} {iopath_Amult24_Cmult48} {iopath_Amult24_Cmult49} {iopath_Amult24_Cmult50} {iopath_Amult24_Cmult51} {iopath_Amult24_Cmult52} {iopath_Amult24_Cmult53} {iopath_Amult24_Cmult54} {iopath_Amult24_Cmult55} {iopath_Amult24_Cmult56} {iopath_Amult24_Cmult57} {iopath_Amult24_Cmult58} {iopath_Amult24_Cmult59} {iopath_Amult24_Cmult60} {iopath_Amult24_Cmult61} {iopath_Amult24_Cmult62} {iopath_Amult24_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult25_Cmult25} {iopath_Amult25_Cmult26} {iopath_Amult25_Cmult27} {iopath_Amult25_Cmult28} {iopath_Amult25_Cmult29} {iopath_Amult25_Cmult30} {iopath_Amult25_Cmult31} {iopath_Amult25_Cmult32} {iopath_Amult25_Cmult33} {iopath_Amult25_Cmult34} {iopath_Amult25_Cmult35} {iopath_Amult25_Cmult36} {iopath_Amult25_Cmult37} {iopath_Amult25_Cmult38} {iopath_Amult25_Cmult39} {iopath_Amult25_Cmult40} {iopath_Amult25_Cmult41} {iopath_Amult25_Cmult42} {iopath_Amult25_Cmult43} {iopath_Amult25_Cmult44} {iopath_Amult25_Cmult45} {iopath_Amult25_Cmult46} {iopath_Amult25_Cmult47} {iopath_Amult25_Cmult48} {iopath_Amult25_Cmult49} {iopath_Amult25_Cmult50} {iopath_Amult25_Cmult51} {iopath_Amult25_Cmult52} {iopath_Amult25_Cmult53} {iopath_Amult25_Cmult54} {iopath_Amult25_Cmult55} {iopath_Amult25_Cmult56} {iopath_Amult25_Cmult57} {iopath_Amult25_Cmult58} {iopath_Amult25_Cmult59} {iopath_Amult25_Cmult60} {iopath_Amult25_Cmult61} {iopath_Amult25_Cmult62} {iopath_Amult25_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult26_Cmult26} {iopath_Amult26_Cmult27} {iopath_Amult26_Cmult28} {iopath_Amult26_Cmult29} {iopath_Amult26_Cmult30} {iopath_Amult26_Cmult31} {iopath_Amult26_Cmult32} {iopath_Amult26_Cmult33} {iopath_Amult26_Cmult34} {iopath_Amult26_Cmult35} {iopath_Amult26_Cmult36} {iopath_Amult26_Cmult37} {iopath_Amult26_Cmult38} {iopath_Amult26_Cmult39} {iopath_Amult26_Cmult40} {iopath_Amult26_Cmult41} {iopath_Amult26_Cmult42} {iopath_Amult26_Cmult43} {iopath_Amult26_Cmult44} {iopath_Amult26_Cmult45} {iopath_Amult26_Cmult46} {iopath_Amult26_Cmult47} {iopath_Amult26_Cmult48} {iopath_Amult26_Cmult49} {iopath_Amult26_Cmult50} {iopath_Amult26_Cmult51} {iopath_Amult26_Cmult52} {iopath_Amult26_Cmult53} {iopath_Amult26_Cmult54} {iopath_Amult26_Cmult55} {iopath_Amult26_Cmult56} {iopath_Amult26_Cmult57} {iopath_Amult26_Cmult58} {iopath_Amult26_Cmult59} {iopath_Amult26_Cmult60} {iopath_Amult26_Cmult61} {iopath_Amult26_Cmult62} {iopath_Amult26_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult27_Cmult27} {iopath_Amult27_Cmult28} {iopath_Amult27_Cmult29} {iopath_Amult27_Cmult30} {iopath_Amult27_Cmult31} {iopath_Amult27_Cmult32} {iopath_Amult27_Cmult33} {iopath_Amult27_Cmult34} {iopath_Amult27_Cmult35} {iopath_Amult27_Cmult36} {iopath_Amult27_Cmult37} {iopath_Amult27_Cmult38} {iopath_Amult27_Cmult39} {iopath_Amult27_Cmult40} {iopath_Amult27_Cmult41} {iopath_Amult27_Cmult42} {iopath_Amult27_Cmult43} {iopath_Amult27_Cmult44} {iopath_Amult27_Cmult45} {iopath_Amult27_Cmult46} {iopath_Amult27_Cmult47} {iopath_Amult27_Cmult48} {iopath_Amult27_Cmult49} {iopath_Amult27_Cmult50} {iopath_Amult27_Cmult51} {iopath_Amult27_Cmult52} {iopath_Amult27_Cmult53} {iopath_Amult27_Cmult54} {iopath_Amult27_Cmult55} {iopath_Amult27_Cmult56} {iopath_Amult27_Cmult57} {iopath_Amult27_Cmult58} {iopath_Amult27_Cmult59} {iopath_Amult27_Cmult60} {iopath_Amult27_Cmult61} {iopath_Amult27_Cmult62} {iopath_Amult27_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult28_Cmult28} {iopath_Amult28_Cmult29} {iopath_Amult28_Cmult30} {iopath_Amult28_Cmult31} {iopath_Amult28_Cmult32} {iopath_Amult28_Cmult33} {iopath_Amult28_Cmult34} {iopath_Amult28_Cmult35} {iopath_Amult28_Cmult36} {iopath_Amult28_Cmult37} {iopath_Amult28_Cmult38} {iopath_Amult28_Cmult39} {iopath_Amult28_Cmult40} {iopath_Amult28_Cmult41} {iopath_Amult28_Cmult42} {iopath_Amult28_Cmult43} {iopath_Amult28_Cmult44} {iopath_Amult28_Cmult45} {iopath_Amult28_Cmult46} {iopath_Amult28_Cmult47} {iopath_Amult28_Cmult48} {iopath_Amult28_Cmult49} {iopath_Amult28_Cmult50} {iopath_Amult28_Cmult51} {iopath_Amult28_Cmult52} {iopath_Amult28_Cmult53} {iopath_Amult28_Cmult54} {iopath_Amult28_Cmult55} {iopath_Amult28_Cmult56} {iopath_Amult28_Cmult57} {iopath_Amult28_Cmult58} {iopath_Amult28_Cmult59} {iopath_Amult28_Cmult60} {iopath_Amult28_Cmult61} {iopath_Amult28_Cmult62} {iopath_Amult28_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult29_Cmult29} {iopath_Amult29_Cmult30} {iopath_Amult29_Cmult31} {iopath_Amult29_Cmult32} {iopath_Amult29_Cmult33} {iopath_Amult29_Cmult34} {iopath_Amult29_Cmult35} {iopath_Amult29_Cmult36} {iopath_Amult29_Cmult37} {iopath_Amult29_Cmult38} {iopath_Amult29_Cmult39} {iopath_Amult29_Cmult40} {iopath_Amult29_Cmult41} {iopath_Amult29_Cmult42} {iopath_Amult29_Cmult43} {iopath_Amult29_Cmult44} {iopath_Amult29_Cmult45} {iopath_Amult29_Cmult46} {iopath_Amult29_Cmult47} {iopath_Amult29_Cmult48} {iopath_Amult29_Cmult49} {iopath_Amult29_Cmult50} {iopath_Amult29_Cmult51} {iopath_Amult29_Cmult52} {iopath_Amult29_Cmult53} {iopath_Amult29_Cmult54} {iopath_Amult29_Cmult55} {iopath_Amult29_Cmult56} {iopath_Amult29_Cmult57} {iopath_Amult29_Cmult58} {iopath_Amult29_Cmult59} {iopath_Amult29_Cmult60} {iopath_Amult29_Cmult61} {iopath_Amult29_Cmult62} {iopath_Amult29_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult30_Cmult30} {iopath_Amult30_Cmult31} {iopath_Amult30_Cmult32} {iopath_Amult30_Cmult33} {iopath_Amult30_Cmult34} {iopath_Amult30_Cmult35} {iopath_Amult30_Cmult36} {iopath_Amult30_Cmult37} {iopath_Amult30_Cmult38} {iopath_Amult30_Cmult39} {iopath_Amult30_Cmult40} {iopath_Amult30_Cmult41} {iopath_Amult30_Cmult42} {iopath_Amult30_Cmult43} {iopath_Amult30_Cmult44} {iopath_Amult30_Cmult45} {iopath_Amult30_Cmult46} {iopath_Amult30_Cmult47} {iopath_Amult30_Cmult48} {iopath_Amult30_Cmult49} {iopath_Amult30_Cmult50} {iopath_Amult30_Cmult51} {iopath_Amult30_Cmult52} {iopath_Amult30_Cmult53} {iopath_Amult30_Cmult54} {iopath_Amult30_Cmult55} {iopath_Amult30_Cmult56} {iopath_Amult30_Cmult57} {iopath_Amult30_Cmult58} {iopath_Amult30_Cmult59} {iopath_Amult30_Cmult60} {iopath_Amult30_Cmult61} {iopath_Amult30_Cmult62} {iopath_Amult30_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult31_Cmult31} {iopath_Amult31_Cmult32} {iopath_Amult31_Cmult33} {iopath_Amult31_Cmult34} {iopath_Amult31_Cmult35} {iopath_Amult31_Cmult36} {iopath_Amult31_Cmult37} {iopath_Amult31_Cmult38} {iopath_Amult31_Cmult39} {iopath_Amult31_Cmult40} {iopath_Amult31_Cmult41} {iopath_Amult31_Cmult42} {iopath_Amult31_Cmult43} {iopath_Amult31_Cmult44} {iopath_Amult31_Cmult45} {iopath_Amult31_Cmult46} {iopath_Amult31_Cmult47} {iopath_Amult31_Cmult48} {iopath_Amult31_Cmult49} {iopath_Amult31_Cmult50} {iopath_Amult31_Cmult51} {iopath_Amult31_Cmult52} {iopath_Amult31_Cmult53} {iopath_Amult31_Cmult54} {iopath_Amult31_Cmult55} {iopath_Amult31_Cmult56} {iopath_Amult31_Cmult57} {iopath_Amult31_Cmult58} {iopath_Amult31_Cmult59} {iopath_Amult31_Cmult60} {iopath_Amult31_Cmult61} {iopath_Amult31_Cmult62} {iopath_Amult31_Cmult63} ",
            "DELAY_MATRIX_Bmult": "{iopath_Amult0_Cmult0} {iopath_Amult0_Cmult1} {iopath_Amult0_Cmult2} {iopath_Amult0_Cmult3} {iopath_Amult0_Cmult4} {iopath_Amult0_Cmult5} {iopath_Amult0_Cmult6} {iopath_Amult0_Cmult7} {iopath_Amult0_Cmult8} {iopath_Amult0_Cmult9} {iopath_Amult0_Cmult10} {iopath_Amult0_Cmult11} {iopath_Amult0_Cmult12} {iopath_Amult0_Cmult13} {iopath_Amult0_Cmult14} {iopath_Amult0_Cmult15} {iopath_Amult0_Cmult16} {iopath_Amult0_Cmult17} {iopath_Amult0_Cmult18} {iopath_Amult0_Cmult19} {iopath_Amult0_Cmult20} {iopath_Amult0_Cmult21} {iopath_Amult0_Cmult22} {iopath_Amult0_Cmult23} {iopath_Amult0_Cmult24} {iopath_Amult0_Cmult25} {iopath_Amult0_Cmult26} {iopath_Amult0_Cmult27} {iopath_Amult0_Cmult28} {iopath_Amult0_Cmult29} {iopath_Amult0_Cmult30} {iopath_Amult0_Cmult31} {iopath_Amult0_Cmult32} {iopath_Amult0_Cmult33} {iopath_Amult0_Cmult34} {iopath_Amult0_Cmult35} {iopath_Amult0_Cmult36} {iopath_Amult0_Cmult37} {iopath_Amult0_Cmult38} {iopath_Amult0_Cmult39} {iopath_Amult0_Cmult40} {iopath_Amult0_Cmult41} {iopath_Amult0_Cmult42} {iopath_Amult0_Cmult43} {iopath_Amult0_Cmult44} {iopath_Amult0_Cmult45} {iopath_Amult0_Cmult46} {iopath_Amult0_Cmult47} {iopath_Amult0_Cmult48} {iopath_Amult0_Cmult49} {iopath_Amult0_Cmult50} {iopath_Amult0_Cmult51} {iopath_Amult0_Cmult52} {iopath_Amult0_Cmult53} {iopath_Amult0_Cmult54} {iopath_Amult0_Cmult55} {iopath_Amult0_Cmult56} {iopath_Amult0_Cmult57} {iopath_Amult0_Cmult58} {iopath_Amult0_Cmult59} {iopath_Amult0_Cmult60} {iopath_Amult0_Cmult61} {iopath_Amult0_Cmult62} {iopath_Amult0_Cmult63} 0 {iopath_Amult1_Cmult1} {iopath_Amult1_Cmult2} {iopath_Amult1_Cmult3} {iopath_Amult1_Cmult4} {iopath_Amult1_Cmult5} {iopath_Amult1_Cmult6} {iopath_Amult1_Cmult7} {iopath_Amult1_Cmult8} {iopath_Amult1_Cmult9} {iopath_Amult1_Cmult10} {iopath_Amult1_Cmult11} {iopath_Amult1_Cmult12} {iopath_Amult1_Cmult13} {iopath_Amult1_Cmult14} {iopath_Amult1_Cmult15} {iopath_Amult1_Cmult16} {iopath_Amult1_Cmult17} {iopath_Amult1_Cmult18} {iopath_Amult1_Cmult19} {iopath_Amult1_Cmult20} {iopath_Amult1_Cmult21} {iopath_Amult1_Cmult22} {iopath_Amult1_Cmult23} {iopath_Amult1_Cmult24} {iopath_Amult1_Cmult25} {iopath_Amult1_Cmult26} {iopath_Amult1_Cmult27} {iopath_Amult1_Cmult28} {iopath_Amult1_Cmult29} {iopath_Amult1_Cmult30} {iopath_Amult1_Cmult31} {iopath_Amult1_Cmult32} {iopath_Amult1_Cmult33} {iopath_Amult1_Cmult34} {iopath_Amult1_Cmult35} {iopath_Amult1_Cmult36} {iopath_Amult1_Cmult37} {iopath_Amult1_Cmult38} {iopath_Amult1_Cmult39} {iopath_Amult1_Cmult40} {iopath_Amult1_Cmult41} {iopath_Amult1_Cmult42} {iopath_Amult1_Cmult43} {iopath_Amult1_Cmult44} {iopath_Amult1_Cmult45} {iopath_Amult1_Cmult46} {iopath_Amult1_Cmult47} {iopath_Amult1_Cmult48} {iopath_Amult1_Cmult49} {iopath_Amult1_Cmult50} {iopath_Amult1_Cmult51} {iopath_Amult1_Cmult52} {iopath_Amult1_Cmult53} {iopath_Amult1_Cmult54} {iopath_Amult1_Cmult55} {iopath_Amult1_Cmult56} {iopath_Amult1_Cmult57} {iopath_Amult1_Cmult58} {iopath_Amult1_Cmult59} {iopath_Amult1_Cmult60} {iopath_Amult1_Cmult61} {iopath_Amult1_Cmult62} {iopath_Amult1_Cmult63} 0 0 {iopath_Amult2_Cmult2} {iopath_Amult2_Cmult3} {iopath_Amult2_Cmult4} {iopath_Amult2_Cmult5} {iopath_Amult2_Cmult6} {iopath_Amult2_Cmult7} {iopath_Amult2_Cmult8} {iopath_Amult2_Cmult9} {iopath_Amult2_Cmult10} {iopath_Amult2_Cmult11} {iopath_Amult2_Cmult12} {iopath_Amult2_Cmult13} {iopath_Amult2_Cmult14} {iopath_Amult2_Cmult15} {iopath_Amult2_Cmult16} {iopath_Amult2_Cmult17} {iopath_Amult2_Cmult18} {iopath_Amult2_Cmult19} {iopath_Amult2_Cmult20} {iopath_Amult2_Cmult21} {iopath_Amult2_Cmult22} {iopath_Amult2_Cmult23} {iopath_Amult2_Cmult24} {iopath_Amult2_Cmult25} {iopath_Amult2_Cmult26} {iopath_Amult2_Cmult27} {iopath_Amult2_Cmult28} {iopath_Amult2_Cmult29} {iopath_Amult2_Cmult30} {iopath_Amult2_Cmult31} {iopath_Amult2_Cmult32} {iopath_Amult2_Cmult33} {iopath_Amult2_Cmult34} {iopath_Amult2_Cmult35} {iopath_Amult2_Cmult36} {iopath_Amult2_Cmult37} {iopath_Amult2_Cmult38} {iopath_Amult2_Cmult39} {iopath_Amult2_Cmult40} {iopath_Amult2_Cmult41} {iopath_Amult2_Cmult42} {iopath_Amult2_Cmult43} {iopath_Amult2_Cmult44} {iopath_Amult2_Cmult45} {iopath_Amult2_Cmult46} {iopath_Amult2_Cmult47} {iopath_Amult2_Cmult48} {iopath_Amult2_Cmult49} {iopath_Amult2_Cmult50} {iopath_Amult2_Cmult51} {iopath_Amult2_Cmult52} {iopath_Amult2_Cmult53} {iopath_Amult2_Cmult54} {iopath_Amult2_Cmult55} {iopath_Amult2_Cmult56} {iopath_Amult2_Cmult57} {iopath_Amult2_Cmult58} {iopath_Amult2_Cmult59} {iopath_Amult2_Cmult60} {iopath_Amult2_Cmult61} {iopath_Amult2_Cmult62} {iopath_Amult2_Cmult63} 0 0 0 {iopath_Amult3_Cmult3} {iopath_Amult3_Cmult4} {iopath_Amult3_Cmult5} {iopath_Amult3_Cmult6} {iopath_Amult3_Cmult7} {iopath_Amult3_Cmult8} {iopath_Amult3_Cmult9} {iopath_Amult3_Cmult10} {iopath_Amult3_Cmult11} {iopath_Amult3_Cmult12} {iopath_Amult3_Cmult13} {iopath_Amult3_Cmult14} {iopath_Amult3_Cmult15} {iopath_Amult3_Cmult16} {iopath_Amult3_Cmult17} {iopath_Amult3_Cmult18} {iopath_Amult3_Cmult19} {iopath_Amult3_Cmult20} {iopath_Amult3_Cmult21} {iopath_Amult3_Cmult22} {iopath_Amult3_Cmult23} {iopath_Amult3_Cmult24} {iopath_Amult3_Cmult25} {iopath_Amult3_Cmult26} {iopath_Amult3_Cmult27} {iopath_Amult3_Cmult28} {iopath_Amult3_Cmult29} {iopath_Amult3_Cmult30} {iopath_Amult3_Cmult31} {iopath_Amult3_Cmult32} {iopath_Amult3_Cmult33} {iopath_Amult3_Cmult34} {iopath_Amult3_Cmult35} {iopath_Amult3_Cmult36} {iopath_Amult3_Cmult37} {iopath_Amult3_Cmult38} {iopath_Amult3_Cmult39} {iopath_Amult3_Cmult40} {iopath_Amult3_Cmult41} {iopath_Amult3_Cmult42} {iopath_Amult3_Cmult43} {iopath_Amult3_Cmult44} {iopath_Amult3_Cmult45} {iopath_Amult3_Cmult46} {iopath_Amult3_Cmult47} {iopath_Amult3_Cmult48} {iopath_Amult3_Cmult49} {iopath_Amult3_Cmult50} {iopath_Amult3_Cmult51} {iopath_Amult3_Cmult52} {iopath_Amult3_Cmult53} {iopath_Amult3_Cmult54} {iopath_Amult3_Cmult55} {iopath_Amult3_Cmult56} {iopath_Amult3_Cmult57} {iopath_Amult3_Cmult58} {iopath_Amult3_Cmult59} {iopath_Amult3_Cmult60} {iopath_Amult3_Cmult61} {iopath_Amult3_Cmult62} {iopath_Amult3_Cmult63} 0 0 0 0 {iopath_Amult4_Cmult4} {iopath_Amult4_Cmult5} {iopath_Amult4_Cmult6} {iopath_Amult4_Cmult7} {iopath_Amult4_Cmult8} {iopath_Amult4_Cmult9} {iopath_Amult4_Cmult10} {iopath_Amult4_Cmult11} {iopath_Amult4_Cmult12} {iopath_Amult4_Cmult13} {iopath_Amult4_Cmult14} {iopath_Amult4_Cmult15} {iopath_Amult4_Cmult16} {iopath_Amult4_Cmult17} {iopath_Amult4_Cmult18} {iopath_Amult4_Cmult19} {iopath_Amult4_Cmult20} {iopath_Amult4_Cmult21} {iopath_Amult4_Cmult22} {iopath_Amult4_Cmult23} {iopath_Amult4_Cmult24} {iopath_Amult4_Cmult25} {iopath_Amult4_Cmult26} {iopath_Amult4_Cmult27} {iopath_Amult4_Cmult28} {iopath_Amult4_Cmult29} {iopath_Amult4_Cmult30} {iopath_Amult4_Cmult31} {iopath_Amult4_Cmult32} {iopath_Amult4_Cmult33} {iopath_Amult4_Cmult34} {iopath_Amult4_Cmult35} {iopath_Amult4_Cmult36} {iopath_Amult4_Cmult37} {iopath_Amult4_Cmult38} {iopath_Amult4_Cmult39} {iopath_Amult4_Cmult40} {iopath_Amult4_Cmult41} {iopath_Amult4_Cmult42} {iopath_Amult4_Cmult43} {iopath_Amult4_Cmult44} {iopath_Amult4_Cmult45} {iopath_Amult4_Cmult46} {iopath_Amult4_Cmult47} {iopath_Amult4_Cmult48} {iopath_Amult4_Cmult49} {iopath_Amult4_Cmult50} {iopath_Amult4_Cmult51} {iopath_Amult4_Cmult52} {iopath_Amult4_Cmult53} {iopath_Amult4_Cmult54} {iopath_Amult4_Cmult55} {iopath_Amult4_Cmult56} {iopath_Amult4_Cmult57} {iopath_Amult4_Cmult58} {iopath_Amult4_Cmult59} {iopath_Amult4_Cmult60} {iopath_Amult4_Cmult61} {iopath_Amult4_Cmult62} {iopath_Amult4_Cmult63} 0 0 0 0 0 {iopath_Amult5_Cmult5} {iopath_Amult5_Cmult6} {iopath_Amult5_Cmult7} {iopath_Amult5_Cmult8} {iopath_Amult5_Cmult9} {iopath_Amult5_Cmult10} {iopath_Amult5_Cmult11} {iopath_Amult5_Cmult12} {iopath_Amult5_Cmult13} {iopath_Amult5_Cmult14} {iopath_Amult5_Cmult15} {iopath_Amult5_Cmult16} {iopath_Amult5_Cmult17} {iopath_Amult5_Cmult18} {iopath_Amult5_Cmult19} {iopath_Amult5_Cmult20} {iopath_Amult5_Cmult21} {iopath_Amult5_Cmult22} {iopath_Amult5_Cmult23} {iopath_Amult5_Cmult24} {iopath_Amult5_Cmult25} {iopath_Amult5_Cmult26} {iopath_Amult5_Cmult27} {iopath_Amult5_Cmult28} {iopath_Amult5_Cmult29} {iopath_Amult5_Cmult30} {iopath_Amult5_Cmult31} {iopath_Amult5_Cmult32} {iopath_Amult5_Cmult33} {iopath_Amult5_Cmult34} {iopath_Amult5_Cmult35} {iopath_Amult5_Cmult36} {iopath_Amult5_Cmult37} {iopath_Amult5_Cmult38} {iopath_Amult5_Cmult39} {iopath_Amult5_Cmult40} {iopath_Amult5_Cmult41} {iopath_Amult5_Cmult42} {iopath_Amult5_Cmult43} {iopath_Amult5_Cmult44} {iopath_Amult5_Cmult45} {iopath_Amult5_Cmult46} {iopath_Amult5_Cmult47} {iopath_Amult5_Cmult48} {iopath_Amult5_Cmult49} {iopath_Amult5_Cmult50} {iopath_Amult5_Cmult51} {iopath_Amult5_Cmult52} {iopath_Amult5_Cmult53} {iopath_Amult5_Cmult54} {iopath_Amult5_Cmult55} {iopath_Amult5_Cmult56} {iopath_Amult5_Cmult57} {iopath_Amult5_Cmult58} {iopath_Amult5_Cmult59} {iopath_Amult5_Cmult60} {iopath_Amult5_Cmult61} {iopath_Amult5_Cmult62} {iopath_Amult5_Cmult63} 0 0 0 0 0 0 {iopath_Amult6_Cmult6} {iopath_Amult6_Cmult7} {iopath_Amult6_Cmult8} {iopath_Amult6_Cmult9} {iopath_Amult6_Cmult10} {iopath_Amult6_Cmult11} {iopath_Amult6_Cmult12} {iopath_Amult6_Cmult13} {iopath_Amult6_Cmult14} {iopath_Amult6_Cmult15} {iopath_Amult6_Cmult16} {iopath_Amult6_Cmult17} {iopath_Amult6_Cmult18} {iopath_Amult6_Cmult19} {iopath_Amult6_Cmult20} {iopath_Amult6_Cmult21} {iopath_Amult6_Cmult22} {iopath_Amult6_Cmult23} {iopath_Amult6_Cmult24} {iopath_Amult6_Cmult25} {iopath_Amult6_Cmult26} {iopath_Amult6_Cmult27} {iopath_Amult6_Cmult28} {iopath_Amult6_Cmult29} {iopath_Amult6_Cmult30} {iopath_Amult6_Cmult31} {iopath_Amult6_Cmult32} {iopath_Amult6_Cmult33} {iopath_Amult6_Cmult34} {iopath_Amult6_Cmult35} {iopath_Amult6_Cmult36} {iopath_Amult6_Cmult37} {iopath_Amult6_Cmult38} {iopath_Amult6_Cmult39} {iopath_Amult6_Cmult40} {iopath_Amult6_Cmult41} {iopath_Amult6_Cmult42} {iopath_Amult6_Cmult43} {iopath_Amult6_Cmult44} {iopath_Amult6_Cmult45} {iopath_Amult6_Cmult46} {iopath_Amult6_Cmult47} {iopath_Amult6_Cmult48} {iopath_Amult6_Cmult49} {iopath_Amult6_Cmult50} {iopath_Amult6_Cmult51} {iopath_Amult6_Cmult52} {iopath_Amult6_Cmult53} {iopath_Amult6_Cmult54} {iopath_Amult6_Cmult55} {iopath_Amult6_Cmult56} {iopath_Amult6_Cmult57} {iopath_Amult6_Cmult58} {iopath_Amult6_Cmult59} {iopath_Amult6_Cmult60} {iopath_Amult6_Cmult61} {iopath_Amult6_Cmult62} {iopath_Amult6_Cmult63} 0 0 0 0 0 0 0 {iopath_Amult7_Cmult7} {iopath_Amult7_Cmult8} {iopath_Amult7_Cmult9} {iopath_Amult7_Cmult10} {iopath_Amult7_Cmult11} {iopath_Amult7_Cmult12} {iopath_Amult7_Cmult13} {iopath_Amult7_Cmult14} {iopath_Amult7_Cmult15} {iopath_Amult7_Cmult16} {iopath_Amult7_Cmult17} {iopath_Amult7_Cmult18} {iopath_Amult7_Cmult19} {iopath_Amult7_Cmult20} {iopath_Amult7_Cmult21} {iopath_Amult7_Cmult22} {iopath_Amult7_Cmult23} {iopath_Amult7_Cmult24} {iopath_Amult7_Cmult25} {iopath_Amult7_Cmult26} {iopath_Amult7_Cmult27} {iopath_Amult7_Cmult28} {iopath_Amult7_Cmult29} {iopath_Amult7_Cmult30} {iopath_Amult7_Cmult31} {iopath_Amult7_Cmult32} {iopath_Amult7_Cmult33} {iopath_Amult7_Cmult34} {iopath_Amult7_Cmult35} {iopath_Amult7_Cmult36} {iopath_Amult7_Cmult37} {iopath_Amult7_Cmult38} {iopath_Amult7_Cmult39} {iopath_Amult7_Cmult40} {iopath_Amult7_Cmult41} {iopath_Amult7_Cmult42} {iopath_Amult7_Cmult43} {iopath_Amult7_Cmult44} {iopath_Amult7_Cmult45} {iopath_Amult7_Cmult46} {iopath_Amult7_Cmult47} {iopath_Amult7_Cmult48} {iopath_Amult7_Cmult49} {iopath_Amult7_Cmult50} {iopath_Amult7_Cmult51} {iopath_Amult7_Cmult52} {iopath_Amult7_Cmult53} {iopath_Amult7_Cmult54} {iopath_Amult7_Cmult55} {iopath_Amult7_Cmult56} {iopath_Amult7_Cmult57} {iopath_Amult7_Cmult58} {iopath_Amult7_Cmult59} {iopath_Amult7_Cmult60} {iopath_Amult7_Cmult61} {iopath_Amult7_Cmult62} {iopath_Amult7_Cmult63} 0 0 0 0 0 0 0 0 {iopath_Amult8_Cmult8} {iopath_Amult8_Cmult9} {iopath_Amult8_Cmult10} {iopath_Amult8_Cmult11} {iopath_Amult8_Cmult12} {iopath_Amult8_Cmult13} {iopath_Amult8_Cmult14} {iopath_Amult8_Cmult15} {iopath_Amult8_Cmult16} {iopath_Amult8_Cmult17} {iopath_Amult8_Cmult18} {iopath_Amult8_Cmult19} {iopath_Amult8_Cmult20} {iopath_Amult8_Cmult21} {iopath_Amult8_Cmult22} {iopath_Amult8_Cmult23} {iopath_Amult8_Cmult24} {iopath_Amult8_Cmult25} {iopath_Amult8_Cmult26} {iopath_Amult8_Cmult27} {iopath_Amult8_Cmult28} {iopath_Amult8_Cmult29} {iopath_Amult8_Cmult30} {iopath_Amult8_Cmult31} {iopath_Amult8_Cmult32} {iopath_Amult8_Cmult33} {iopath_Amult8_Cmult34} {iopath_Amult8_Cmult35} {iopath_Amult8_Cmult36} {iopath_Amult8_Cmult37} {iopath_Amult8_Cmult38} {iopath_Amult8_Cmult39} {iopath_Amult8_Cmult40} {iopath_Amult8_Cmult41} {iopath_Amult8_Cmult42} {iopath_Amult8_Cmult43} {iopath_Amult8_Cmult44} {iopath_Amult8_Cmult45} {iopath_Amult8_Cmult46} {iopath_Amult8_Cmult47} {iopath_Amult8_Cmult48} {iopath_Amult8_Cmult49} {iopath_Amult8_Cmult50} {iopath_Amult8_Cmult51} {iopath_Amult8_Cmult52} {iopath_Amult8_Cmult53} {iopath_Amult8_Cmult54} {iopath_Amult8_Cmult55} {iopath_Amult8_Cmult56} {iopath_Amult8_Cmult57} {iopath_Amult8_Cmult58} {iopath_Amult8_Cmult59} {iopath_Amult8_Cmult60} {iopath_Amult8_Cmult61} {iopath_Amult8_Cmult62} {iopath_Amult8_Cmult63} 0 0 0 0 0 0 0 0 0 {iopath_Amult9_Cmult9} {iopath_Amult9_Cmult10} {iopath_Amult9_Cmult11} {iopath_Amult9_Cmult12} {iopath_Amult9_Cmult13} {iopath_Amult9_Cmult14} {iopath_Amult9_Cmult15} {iopath_Amult9_Cmult16} {iopath_Amult9_Cmult17} {iopath_Amult9_Cmult18} {iopath_Amult9_Cmult19} {iopath_Amult9_Cmult20} {iopath_Amult9_Cmult21} {iopath_Amult9_Cmult22} {iopath_Amult9_Cmult23} {iopath_Amult9_Cmult24} {iopath_Amult9_Cmult25} {iopath_Amult9_Cmult26} {iopath_Amult9_Cmult27} {iopath_Amult9_Cmult28} {iopath_Amult9_Cmult29} {iopath_Amult9_Cmult30} {iopath_Amult9_Cmult31} {iopath_Amult9_Cmult32} {iopath_Amult9_Cmult33} {iopath_Amult9_Cmult34} {iopath_Amult9_Cmult35} {iopath_Amult9_Cmult36} {iopath_Amult9_Cmult37} {iopath_Amult9_Cmult38} {iopath_Amult9_Cmult39} {iopath_Amult9_Cmult40} {iopath_Amult9_Cmult41} {iopath_Amult9_Cmult42} {iopath_Amult9_Cmult43} {iopath_Amult9_Cmult44} {iopath_Amult9_Cmult45} {iopath_Amult9_Cmult46} {iopath_Amult9_Cmult47} {iopath_Amult9_Cmult48} {iopath_Amult9_Cmult49} {iopath_Amult9_Cmult50} {iopath_Amult9_Cmult51} {iopath_Amult9_Cmult52} {iopath_Amult9_Cmult53} {iopath_Amult9_Cmult54} {iopath_Amult9_Cmult55} {iopath_Amult9_Cmult56} {iopath_Amult9_Cmult57} {iopath_Amult9_Cmult58} {iopath_Amult9_Cmult59} {iopath_Amult9_Cmult60} {iopath_Amult9_Cmult61} {iopath_Amult9_Cmult62} {iopath_Amult9_Cmult63} 0 0 0 0 0 0 0 0 0 0 {iopath_Amult10_Cmult10} {iopath_Amult10_Cmult11} {iopath_Amult10_Cmult12} {iopath_Amult10_Cmult13} {iopath_Amult10_Cmult14} {iopath_Amult10_Cmult15} {iopath_Amult10_Cmult16} {iopath_Amult10_Cmult17} {iopath_Amult10_Cmult18} {iopath_Amult10_Cmult19} {iopath_Amult10_Cmult20} {iopath_Amult10_Cmult21} {iopath_Amult10_Cmult22} {iopath_Amult10_Cmult23} {iopath_Amult10_Cmult24} {iopath_Amult10_Cmult25} {iopath_Amult10_Cmult26} {iopath_Amult10_Cmult27} {iopath_Amult10_Cmult28} {iopath_Amult10_Cmult29} {iopath_Amult10_Cmult30} {iopath_Amult10_Cmult31} {iopath_Amult10_Cmult32} {iopath_Amult10_Cmult33} {iopath_Amult10_Cmult34} {iopath_Amult10_Cmult35} {iopath_Amult10_Cmult36} {iopath_Amult10_Cmult37} {iopath_Amult10_Cmult38} {iopath_Amult10_Cmult39} {iopath_Amult10_Cmult40} {iopath_Amult10_Cmult41} {iopath_Amult10_Cmult42} {iopath_Amult10_Cmult43} {iopath_Amult10_Cmult44} {iopath_Amult10_Cmult45} {iopath_Amult10_Cmult46} {iopath_Amult10_Cmult47} {iopath_Amult10_Cmult48} {iopath_Amult10_Cmult49} {iopath_Amult10_Cmult50} {iopath_Amult10_Cmult51} {iopath_Amult10_Cmult52} {iopath_Amult10_Cmult53} {iopath_Amult10_Cmult54} {iopath_Amult10_Cmult55} {iopath_Amult10_Cmult56} {iopath_Amult10_Cmult57} {iopath_Amult10_Cmult58} {iopath_Amult10_Cmult59} {iopath_Amult10_Cmult60} {iopath_Amult10_Cmult61} {iopath_Amult10_Cmult62} {iopath_Amult10_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult11_Cmult11} {iopath_Amult11_Cmult12} {iopath_Amult11_Cmult13} {iopath_Amult11_Cmult14} {iopath_Amult11_Cmult15} {iopath_Amult11_Cmult16} {iopath_Amult11_Cmult17} {iopath_Amult11_Cmult18} {iopath_Amult11_Cmult19} {iopath_Amult11_Cmult20} {iopath_Amult11_Cmult21} {iopath_Amult11_Cmult22} {iopath_Amult11_Cmult23} {iopath_Amult11_Cmult24} {iopath_Amult11_Cmult25} {iopath_Amult11_Cmult26} {iopath_Amult11_Cmult27} {iopath_Amult11_Cmult28} {iopath_Amult11_Cmult29} {iopath_Amult11_Cmult30} {iopath_Amult11_Cmult31} {iopath_Amult11_Cmult32} {iopath_Amult11_Cmult33} {iopath_Amult11_Cmult34} {iopath_Amult11_Cmult35} {iopath_Amult11_Cmult36} {iopath_Amult11_Cmult37} {iopath_Amult11_Cmult38} {iopath_Amult11_Cmult39} {iopath_Amult11_Cmult40} {iopath_Amult11_Cmult41} {iopath_Amult11_Cmult42} {iopath_Amult11_Cmult43} {iopath_Amult11_Cmult44} {iopath_Amult11_Cmult45} {iopath_Amult11_Cmult46} {iopath_Amult11_Cmult47} {iopath_Amult11_Cmult48} {iopath_Amult11_Cmult49} {iopath_Amult11_Cmult50} {iopath_Amult11_Cmult51} {iopath_Amult11_Cmult52} {iopath_Amult11_Cmult53} {iopath_Amult11_Cmult54} {iopath_Amult11_Cmult55} {iopath_Amult11_Cmult56} {iopath_Amult11_Cmult57} {iopath_Amult11_Cmult58} {iopath_Amult11_Cmult59} {iopath_Amult11_Cmult60} {iopath_Amult11_Cmult61} {iopath_Amult11_Cmult62} {iopath_Amult11_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult12_Cmult12} {iopath_Amult12_Cmult13} {iopath_Amult12_Cmult14} {iopath_Amult12_Cmult15} {iopath_Amult12_Cmult16} {iopath_Amult12_Cmult17} {iopath_Amult12_Cmult18} {iopath_Amult12_Cmult19} {iopath_Amult12_Cmult20} {iopath_Amult12_Cmult21} {iopath_Amult12_Cmult22} {iopath_Amult12_Cmult23} {iopath_Amult12_Cmult24} {iopath_Amult12_Cmult25} {iopath_Amult12_Cmult26} {iopath_Amult12_Cmult27} {iopath_Amult12_Cmult28} {iopath_Amult12_Cmult29} {iopath_Amult12_Cmult30} {iopath_Amult12_Cmult31} {iopath_Amult12_Cmult32} {iopath_Amult12_Cmult33} {iopath_Amult12_Cmult34} {iopath_Amult12_Cmult35} {iopath_Amult12_Cmult36} {iopath_Amult12_Cmult37} {iopath_Amult12_Cmult38} {iopath_Amult12_Cmult39} {iopath_Amult12_Cmult40} {iopath_Amult12_Cmult41} {iopath_Amult12_Cmult42} {iopath_Amult12_Cmult43} {iopath_Amult12_Cmult44} {iopath_Amult12_Cmult45} {iopath_Amult12_Cmult46} {iopath_Amult12_Cmult47} {iopath_Amult12_Cmult48} {iopath_Amult12_Cmult49} {iopath_Amult12_Cmult50} {iopath_Amult12_Cmult51} {iopath_Amult12_Cmult52} {iopath_Amult12_Cmult53} {iopath_Amult12_Cmult54} {iopath_Amult12_Cmult55} {iopath_Amult12_Cmult56} {iopath_Amult12_Cmult57} {iopath_Amult12_Cmult58} {iopath_Amult12_Cmult59} {iopath_Amult12_Cmult60} {iopath_Amult12_Cmult61} {iopath_Amult12_Cmult62} {iopath_Amult12_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult13_Cmult13} {iopath_Amult13_Cmult14} {iopath_Amult13_Cmult15} {iopath_Amult13_Cmult16} {iopath_Amult13_Cmult17} {iopath_Amult13_Cmult18} {iopath_Amult13_Cmult19} {iopath_Amult13_Cmult20} {iopath_Amult13_Cmult21} {iopath_Amult13_Cmult22} {iopath_Amult13_Cmult23} {iopath_Amult13_Cmult24} {iopath_Amult13_Cmult25} {iopath_Amult13_Cmult26} {iopath_Amult13_Cmult27} {iopath_Amult13_Cmult28} {iopath_Amult13_Cmult29} {iopath_Amult13_Cmult30} {iopath_Amult13_Cmult31} {iopath_Amult13_Cmult32} {iopath_Amult13_Cmult33} {iopath_Amult13_Cmult34} {iopath_Amult13_Cmult35} {iopath_Amult13_Cmult36} {iopath_Amult13_Cmult37} {iopath_Amult13_Cmult38} {iopath_Amult13_Cmult39} {iopath_Amult13_Cmult40} {iopath_Amult13_Cmult41} {iopath_Amult13_Cmult42} {iopath_Amult13_Cmult43} {iopath_Amult13_Cmult44} {iopath_Amult13_Cmult45} {iopath_Amult13_Cmult46} {iopath_Amult13_Cmult47} {iopath_Amult13_Cmult48} {iopath_Amult13_Cmult49} {iopath_Amult13_Cmult50} {iopath_Amult13_Cmult51} {iopath_Amult13_Cmult52} {iopath_Amult13_Cmult53} {iopath_Amult13_Cmult54} {iopath_Amult13_Cmult55} {iopath_Amult13_Cmult56} {iopath_Amult13_Cmult57} {iopath_Amult13_Cmult58} {iopath_Amult13_Cmult59} {iopath_Amult13_Cmult60} {iopath_Amult13_Cmult61} {iopath_Amult13_Cmult62} {iopath_Amult13_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult14_Cmult14} {iopath_Amult14_Cmult15} {iopath_Amult14_Cmult16} {iopath_Amult14_Cmult17} {iopath_Amult14_Cmult18} {iopath_Amult14_Cmult19} {iopath_Amult14_Cmult20} {iopath_Amult14_Cmult21} {iopath_Amult14_Cmult22} {iopath_Amult14_Cmult23} {iopath_Amult14_Cmult24} {iopath_Amult14_Cmult25} {iopath_Amult14_Cmult26} {iopath_Amult14_Cmult27} {iopath_Amult14_Cmult28} {iopath_Amult14_Cmult29} {iopath_Amult14_Cmult30} {iopath_Amult14_Cmult31} {iopath_Amult14_Cmult32} {iopath_Amult14_Cmult33} {iopath_Amult14_Cmult34} {iopath_Amult14_Cmult35} {iopath_Amult14_Cmult36} {iopath_Amult14_Cmult37} {iopath_Amult14_Cmult38} {iopath_Amult14_Cmult39} {iopath_Amult14_Cmult40} {iopath_Amult14_Cmult41} {iopath_Amult14_Cmult42} {iopath_Amult14_Cmult43} {iopath_Amult14_Cmult44} {iopath_Amult14_Cmult45} {iopath_Amult14_Cmult46} {iopath_Amult14_Cmult47} {iopath_Amult14_Cmult48} {iopath_Amult14_Cmult49} {iopath_Amult14_Cmult50} {iopath_Amult14_Cmult51} {iopath_Amult14_Cmult52} {iopath_Amult14_Cmult53} {iopath_Amult14_Cmult54} {iopath_Amult14_Cmult55} {iopath_Amult14_Cmult56} {iopath_Amult14_Cmult57} {iopath_Amult14_Cmult58} {iopath_Amult14_Cmult59} {iopath_Amult14_Cmult60} {iopath_Amult14_Cmult61} {iopath_Amult14_Cmult62} {iopath_Amult14_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult15_Cmult15} {iopath_Amult15_Cmult16} {iopath_Amult15_Cmult17} {iopath_Amult15_Cmult18} {iopath_Amult15_Cmult19} {iopath_Amult15_Cmult20} {iopath_Amult15_Cmult21} {iopath_Amult15_Cmult22} {iopath_Amult15_Cmult23} {iopath_Amult15_Cmult24} {iopath_Amult15_Cmult25} {iopath_Amult15_Cmult26} {iopath_Amult15_Cmult27} {iopath_Amult15_Cmult28} {iopath_Amult15_Cmult29} {iopath_Amult15_Cmult30} {iopath_Amult15_Cmult31} {iopath_Amult15_Cmult32} {iopath_Amult15_Cmult33} {iopath_Amult15_Cmult34} {iopath_Amult15_Cmult35} {iopath_Amult15_Cmult36} {iopath_Amult15_Cmult37} {iopath_Amult15_Cmult38} {iopath_Amult15_Cmult39} {iopath_Amult15_Cmult40} {iopath_Amult15_Cmult41} {iopath_Amult15_Cmult42} {iopath_Amult15_Cmult43} {iopath_Amult15_Cmult44} {iopath_Amult15_Cmult45} {iopath_Amult15_Cmult46} {iopath_Amult15_Cmult47} {iopath_Amult15_Cmult48} {iopath_Amult15_Cmult49} {iopath_Amult15_Cmult50} {iopath_Amult15_Cmult51} {iopath_Amult15_Cmult52} {iopath_Amult15_Cmult53} {iopath_Amult15_Cmult54} {iopath_Amult15_Cmult55} {iopath_Amult15_Cmult56} {iopath_Amult15_Cmult57} {iopath_Amult15_Cmult58} {iopath_Amult15_Cmult59} {iopath_Amult15_Cmult60} {iopath_Amult15_Cmult61} {iopath_Amult15_Cmult62} {iopath_Amult15_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult16_Cmult16} {iopath_Amult16_Cmult17} {iopath_Amult16_Cmult18} {iopath_Amult16_Cmult19} {iopath_Amult16_Cmult20} {iopath_Amult16_Cmult21} {iopath_Amult16_Cmult22} {iopath_Amult16_Cmult23} {iopath_Amult16_Cmult24} {iopath_Amult16_Cmult25} {iopath_Amult16_Cmult26} {iopath_Amult16_Cmult27} {iopath_Amult16_Cmult28} {iopath_Amult16_Cmult29} {iopath_Amult16_Cmult30} {iopath_Amult16_Cmult31} {iopath_Amult16_Cmult32} {iopath_Amult16_Cmult33} {iopath_Amult16_Cmult34} {iopath_Amult16_Cmult35} {iopath_Amult16_Cmult36} {iopath_Amult16_Cmult37} {iopath_Amult16_Cmult38} {iopath_Amult16_Cmult39} {iopath_Amult16_Cmult40} {iopath_Amult16_Cmult41} {iopath_Amult16_Cmult42} {iopath_Amult16_Cmult43} {iopath_Amult16_Cmult44} {iopath_Amult16_Cmult45} {iopath_Amult16_Cmult46} {iopath_Amult16_Cmult47} {iopath_Amult16_Cmult48} {iopath_Amult16_Cmult49} {iopath_Amult16_Cmult50} {iopath_Amult16_Cmult51} {iopath_Amult16_Cmult52} {iopath_Amult16_Cmult53} {iopath_Amult16_Cmult54} {iopath_Amult16_Cmult55} {iopath_Amult16_Cmult56} {iopath_Amult16_Cmult57} {iopath_Amult16_Cmult58} {iopath_Amult16_Cmult59} {iopath_Amult16_Cmult60} {iopath_Amult16_Cmult61} {iopath_Amult16_Cmult62} {iopath_Amult16_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult17_Cmult17} {iopath_Amult17_Cmult18} {iopath_Amult17_Cmult19} {iopath_Amult17_Cmult20} {iopath_Amult17_Cmult21} {iopath_Amult17_Cmult22} {iopath_Amult17_Cmult23} {iopath_Amult17_Cmult24} {iopath_Amult17_Cmult25} {iopath_Amult17_Cmult26} {iopath_Amult17_Cmult27} {iopath_Amult17_Cmult28} {iopath_Amult17_Cmult29} {iopath_Amult17_Cmult30} {iopath_Amult17_Cmult31} {iopath_Amult17_Cmult32} {iopath_Amult17_Cmult33} {iopath_Amult17_Cmult34} {iopath_Amult17_Cmult35} {iopath_Amult17_Cmult36} {iopath_Amult17_Cmult37} {iopath_Amult17_Cmult38} {iopath_Amult17_Cmult39} {iopath_Amult17_Cmult40} {iopath_Amult17_Cmult41} {iopath_Amult17_Cmult42} {iopath_Amult17_Cmult43} {iopath_Amult17_Cmult44} {iopath_Amult17_Cmult45} {iopath_Amult17_Cmult46} {iopath_Amult17_Cmult47} {iopath_Amult17_Cmult48} {iopath_Amult17_Cmult49} {iopath_Amult17_Cmult50} {iopath_Amult17_Cmult51} {iopath_Amult17_Cmult52} {iopath_Amult17_Cmult53} {iopath_Amult17_Cmult54} {iopath_Amult17_Cmult55} {iopath_Amult17_Cmult56} {iopath_Amult17_Cmult57} {iopath_Amult17_Cmult58} {iopath_Amult17_Cmult59} {iopath_Amult17_Cmult60} {iopath_Amult17_Cmult61} {iopath_Amult17_Cmult62} {iopath_Amult17_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult18_Cmult18} {iopath_Amult18_Cmult19} {iopath_Amult18_Cmult20} {iopath_Amult18_Cmult21} {iopath_Amult18_Cmult22} {iopath_Amult18_Cmult23} {iopath_Amult18_Cmult24} {iopath_Amult18_Cmult25} {iopath_Amult18_Cmult26} {iopath_Amult18_Cmult27} {iopath_Amult18_Cmult28} {iopath_Amult18_Cmult29} {iopath_Amult18_Cmult30} {iopath_Amult18_Cmult31} {iopath_Amult18_Cmult32} {iopath_Amult18_Cmult33} {iopath_Amult18_Cmult34} {iopath_Amult18_Cmult35} {iopath_Amult18_Cmult36} {iopath_Amult18_Cmult37} {iopath_Amult18_Cmult38} {iopath_Amult18_Cmult39} {iopath_Amult18_Cmult40} {iopath_Amult18_Cmult41} {iopath_Amult18_Cmult42} {iopath_Amult18_Cmult43} {iopath_Amult18_Cmult44} {iopath_Amult18_Cmult45} {iopath_Amult18_Cmult46} {iopath_Amult18_Cmult47} {iopath_Amult18_Cmult48} {iopath_Amult18_Cmult49} {iopath_Amult18_Cmult50} {iopath_Amult18_Cmult51} {iopath_Amult18_Cmult52} {iopath_Amult18_Cmult53} {iopath_Amult18_Cmult54} {iopath_Amult18_Cmult55} {iopath_Amult18_Cmult56} {iopath_Amult18_Cmult57} {iopath_Amult18_Cmult58} {iopath_Amult18_Cmult59} {iopath_Amult18_Cmult60} {iopath_Amult18_Cmult61} {iopath_Amult18_Cmult62} {iopath_Amult18_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult19_Cmult19} {iopath_Amult19_Cmult20} {iopath_Amult19_Cmult21} {iopath_Amult19_Cmult22} {iopath_Amult19_Cmult23} {iopath_Amult19_Cmult24} {iopath_Amult19_Cmult25} {iopath_Amult19_Cmult26} {iopath_Amult19_Cmult27} {iopath_Amult19_Cmult28} {iopath_Amult19_Cmult29} {iopath_Amult19_Cmult30} {iopath_Amult19_Cmult31} {iopath_Amult19_Cmult32} {iopath_Amult19_Cmult33} {iopath_Amult19_Cmult34} {iopath_Amult19_Cmult35} {iopath_Amult19_Cmult36} {iopath_Amult19_Cmult37} {iopath_Amult19_Cmult38} {iopath_Amult19_Cmult39} {iopath_Amult19_Cmult40} {iopath_Amult19_Cmult41} {iopath_Amult19_Cmult42} {iopath_Amult19_Cmult43} {iopath_Amult19_Cmult44} {iopath_Amult19_Cmult45} {iopath_Amult19_Cmult46} {iopath_Amult19_Cmult47} {iopath_Amult19_Cmult48} {iopath_Amult19_Cmult49} {iopath_Amult19_Cmult50} {iopath_Amult19_Cmult51} {iopath_Amult19_Cmult52} {iopath_Amult19_Cmult53} {iopath_Amult19_Cmult54} {iopath_Amult19_Cmult55} {iopath_Amult19_Cmult56} {iopath_Amult19_Cmult57} {iopath_Amult19_Cmult58} {iopath_Amult19_Cmult59} {iopath_Amult19_Cmult60} {iopath_Amult19_Cmult61} {iopath_Amult19_Cmult62} {iopath_Amult19_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult20_Cmult20} {iopath_Amult20_Cmult21} {iopath_Amult20_Cmult22} {iopath_Amult20_Cmult23} {iopath_Amult20_Cmult24} {iopath_Amult20_Cmult25} {iopath_Amult20_Cmult26} {iopath_Amult20_Cmult27} {iopath_Amult20_Cmult28} {iopath_Amult20_Cmult29} {iopath_Amult20_Cmult30} {iopath_Amult20_Cmult31} {iopath_Amult20_Cmult32} {iopath_Amult20_Cmult33} {iopath_Amult20_Cmult34} {iopath_Amult20_Cmult35} {iopath_Amult20_Cmult36} {iopath_Amult20_Cmult37} {iopath_Amult20_Cmult38} {iopath_Amult20_Cmult39} {iopath_Amult20_Cmult40} {iopath_Amult20_Cmult41} {iopath_Amult20_Cmult42} {iopath_Amult20_Cmult43} {iopath_Amult20_Cmult44} {iopath_Amult20_Cmult45} {iopath_Amult20_Cmult46} {iopath_Amult20_Cmult47} {iopath_Amult20_Cmult48} {iopath_Amult20_Cmult49} {iopath_Amult20_Cmult50} {iopath_Amult20_Cmult51} {iopath_Amult20_Cmult52} {iopath_Amult20_Cmult53} {iopath_Amult20_Cmult54} {iopath_Amult20_Cmult55} {iopath_Amult20_Cmult56} {iopath_Amult20_Cmult57} {iopath_Amult20_Cmult58} {iopath_Amult20_Cmult59} {iopath_Amult20_Cmult60} {iopath_Amult20_Cmult61} {iopath_Amult20_Cmult62} {iopath_Amult20_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult21_Cmult21} {iopath_Amult21_Cmult22} {iopath_Amult21_Cmult23} {iopath_Amult21_Cmult24} {iopath_Amult21_Cmult25} {iopath_Amult21_Cmult26} {iopath_Amult21_Cmult27} {iopath_Amult21_Cmult28} {iopath_Amult21_Cmult29} {iopath_Amult21_Cmult30} {iopath_Amult21_Cmult31} {iopath_Amult21_Cmult32} {iopath_Amult21_Cmult33} {iopath_Amult21_Cmult34} {iopath_Amult21_Cmult35} {iopath_Amult21_Cmult36} {iopath_Amult21_Cmult37} {iopath_Amult21_Cmult38} {iopath_Amult21_Cmult39} {iopath_Amult21_Cmult40} {iopath_Amult21_Cmult41} {iopath_Amult21_Cmult42} {iopath_Amult21_Cmult43} {iopath_Amult21_Cmult44} {iopath_Amult21_Cmult45} {iopath_Amult21_Cmult46} {iopath_Amult21_Cmult47} {iopath_Amult21_Cmult48} {iopath_Amult21_Cmult49} {iopath_Amult21_Cmult50} {iopath_Amult21_Cmult51} {iopath_Amult21_Cmult52} {iopath_Amult21_Cmult53} {iopath_Amult21_Cmult54} {iopath_Amult21_Cmult55} {iopath_Amult21_Cmult56} {iopath_Amult21_Cmult57} {iopath_Amult21_Cmult58} {iopath_Amult21_Cmult59} {iopath_Amult21_Cmult60} {iopath_Amult21_Cmult61} {iopath_Amult21_Cmult62} {iopath_Amult21_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult22_Cmult22} {iopath_Amult22_Cmult23} {iopath_Amult22_Cmult24} {iopath_Amult22_Cmult25} {iopath_Amult22_Cmult26} {iopath_Amult22_Cmult27} {iopath_Amult22_Cmult28} {iopath_Amult22_Cmult29} {iopath_Amult22_Cmult30} {iopath_Amult22_Cmult31} {iopath_Amult22_Cmult32} {iopath_Amult22_Cmult33} {iopath_Amult22_Cmult34} {iopath_Amult22_Cmult35} {iopath_Amult22_Cmult36} {iopath_Amult22_Cmult37} {iopath_Amult22_Cmult38} {iopath_Amult22_Cmult39} {iopath_Amult22_Cmult40} {iopath_Amult22_Cmult41} {iopath_Amult22_Cmult42} {iopath_Amult22_Cmult43} {iopath_Amult22_Cmult44} {iopath_Amult22_Cmult45} {iopath_Amult22_Cmult46} {iopath_Amult22_Cmult47} {iopath_Amult22_Cmult48} {iopath_Amult22_Cmult49} {iopath_Amult22_Cmult50} {iopath_Amult22_Cmult51} {iopath_Amult22_Cmult52} {iopath_Amult22_Cmult53} {iopath_Amult22_Cmult54} {iopath_Amult22_Cmult55} {iopath_Amult22_Cmult56} {iopath_Amult22_Cmult57} {iopath_Amult22_Cmult58} {iopath_Amult22_Cmult59} {iopath_Amult22_Cmult60} {iopath_Amult22_Cmult61} {iopath_Amult22_Cmult62} {iopath_Amult22_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult23_Cmult23} {iopath_Amult23_Cmult24} {iopath_Amult23_Cmult25} {iopath_Amult23_Cmult26} {iopath_Amult23_Cmult27} {iopath_Amult23_Cmult28} {iopath_Amult23_Cmult29} {iopath_Amult23_Cmult30} {iopath_Amult23_Cmult31} {iopath_Amult23_Cmult32} {iopath_Amult23_Cmult33} {iopath_Amult23_Cmult34} {iopath_Amult23_Cmult35} {iopath_Amult23_Cmult36} {iopath_Amult23_Cmult37} {iopath_Amult23_Cmult38} {iopath_Amult23_Cmult39} {iopath_Amult23_Cmult40} {iopath_Amult23_Cmult41} {iopath_Amult23_Cmult42} {iopath_Amult23_Cmult43} {iopath_Amult23_Cmult44} {iopath_Amult23_Cmult45} {iopath_Amult23_Cmult46} {iopath_Amult23_Cmult47} {iopath_Amult23_Cmult48} {iopath_Amult23_Cmult49} {iopath_Amult23_Cmult50} {iopath_Amult23_Cmult51} {iopath_Amult23_Cmult52} {iopath_Amult23_Cmult53} {iopath_Amult23_Cmult54} {iopath_Amult23_Cmult55} {iopath_Amult23_Cmult56} {iopath_Amult23_Cmult57} {iopath_Amult23_Cmult58} {iopath_Amult23_Cmult59} {iopath_Amult23_Cmult60} {iopath_Amult23_Cmult61} {iopath_Amult23_Cmult62} {iopath_Amult23_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult24_Cmult24} {iopath_Amult24_Cmult25} {iopath_Amult24_Cmult26} {iopath_Amult24_Cmult27} {iopath_Amult24_Cmult28} {iopath_Amult24_Cmult29} {iopath_Amult24_Cmult30} {iopath_Amult24_Cmult31} {iopath_Amult24_Cmult32} {iopath_Amult24_Cmult33} {iopath_Amult24_Cmult34} {iopath_Amult24_Cmult35} {iopath_Amult24_Cmult36} {iopath_Amult24_Cmult37} {iopath_Amult24_Cmult38} {iopath_Amult24_Cmult39} {iopath_Amult24_Cmult40} {iopath_Amult24_Cmult41} {iopath_Amult24_Cmult42} {iopath_Amult24_Cmult43} {iopath_Amult24_Cmult44} {iopath_Amult24_Cmult45} {iopath_Amult24_Cmult46} {iopath_Amult24_Cmult47} {iopath_Amult24_Cmult48} {iopath_Amult24_Cmult49} {iopath_Amult24_Cmult50} {iopath_Amult24_Cmult51} {iopath_Amult24_Cmult52} {iopath_Amult24_Cmult53} {iopath_Amult24_Cmult54} {iopath_Amult24_Cmult55} {iopath_Amult24_Cmult56} {iopath_Amult24_Cmult57} {iopath_Amult24_Cmult58} {iopath_Amult24_Cmult59} {iopath_Amult24_Cmult60} {iopath_Amult24_Cmult61} {iopath_Amult24_Cmult62} {iopath_Amult24_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult25_Cmult25} {iopath_Amult25_Cmult26} {iopath_Amult25_Cmult27} {iopath_Amult25_Cmult28} {iopath_Amult25_Cmult29} {iopath_Amult25_Cmult30} {iopath_Amult25_Cmult31} {iopath_Amult25_Cmult32} {iopath_Amult25_Cmult33} {iopath_Amult25_Cmult34} {iopath_Amult25_Cmult35} {iopath_Amult25_Cmult36} {iopath_Amult25_Cmult37} {iopath_Amult25_Cmult38} {iopath_Amult25_Cmult39} {iopath_Amult25_Cmult40} {iopath_Amult25_Cmult41} {iopath_Amult25_Cmult42} {iopath_Amult25_Cmult43} {iopath_Amult25_Cmult44} {iopath_Amult25_Cmult45} {iopath_Amult25_Cmult46} {iopath_Amult25_Cmult47} {iopath_Amult25_Cmult48} {iopath_Amult25_Cmult49} {iopath_Amult25_Cmult50} {iopath_Amult25_Cmult51} {iopath_Amult25_Cmult52} {iopath_Amult25_Cmult53} {iopath_Amult25_Cmult54} {iopath_Amult25_Cmult55} {iopath_Amult25_Cmult56} {iopath_Amult25_Cmult57} {iopath_Amult25_Cmult58} {iopath_Amult25_Cmult59} {iopath_Amult25_Cmult60} {iopath_Amult25_Cmult61} {iopath_Amult25_Cmult62} {iopath_Amult25_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult26_Cmult26} {iopath_Amult26_Cmult27} {iopath_Amult26_Cmult28} {iopath_Amult26_Cmult29} {iopath_Amult26_Cmult30} {iopath_Amult26_Cmult31} {iopath_Amult26_Cmult32} {iopath_Amult26_Cmult33} {iopath_Amult26_Cmult34} {iopath_Amult26_Cmult35} {iopath_Amult26_Cmult36} {iopath_Amult26_Cmult37} {iopath_Amult26_Cmult38} {iopath_Amult26_Cmult39} {iopath_Amult26_Cmult40} {iopath_Amult26_Cmult41} {iopath_Amult26_Cmult42} {iopath_Amult26_Cmult43} {iopath_Amult26_Cmult44} {iopath_Amult26_Cmult45} {iopath_Amult26_Cmult46} {iopath_Amult26_Cmult47} {iopath_Amult26_Cmult48} {iopath_Amult26_Cmult49} {iopath_Amult26_Cmult50} {iopath_Amult26_Cmult51} {iopath_Amult26_Cmult52} {iopath_Amult26_Cmult53} {iopath_Amult26_Cmult54} {iopath_Amult26_Cmult55} {iopath_Amult26_Cmult56} {iopath_Amult26_Cmult57} {iopath_Amult26_Cmult58} {iopath_Amult26_Cmult59} {iopath_Amult26_Cmult60} {iopath_Amult26_Cmult61} {iopath_Amult26_Cmult62} {iopath_Amult26_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult27_Cmult27} {iopath_Amult27_Cmult28} {iopath_Amult27_Cmult29} {iopath_Amult27_Cmult30} {iopath_Amult27_Cmult31} {iopath_Amult27_Cmult32} {iopath_Amult27_Cmult33} {iopath_Amult27_Cmult34} {iopath_Amult27_Cmult35} {iopath_Amult27_Cmult36} {iopath_Amult27_Cmult37} {iopath_Amult27_Cmult38} {iopath_Amult27_Cmult39} {iopath_Amult27_Cmult40} {iopath_Amult27_Cmult41} {iopath_Amult27_Cmult42} {iopath_Amult27_Cmult43} {iopath_Amult27_Cmult44} {iopath_Amult27_Cmult45} {iopath_Amult27_Cmult46} {iopath_Amult27_Cmult47} {iopath_Amult27_Cmult48} {iopath_Amult27_Cmult49} {iopath_Amult27_Cmult50} {iopath_Amult27_Cmult51} {iopath_Amult27_Cmult52} {iopath_Amult27_Cmult53} {iopath_Amult27_Cmult54} {iopath_Amult27_Cmult55} {iopath_Amult27_Cmult56} {iopath_Amult27_Cmult57} {iopath_Amult27_Cmult58} {iopath_Amult27_Cmult59} {iopath_Amult27_Cmult60} {iopath_Amult27_Cmult61} {iopath_Amult27_Cmult62} {iopath_Amult27_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult28_Cmult28} {iopath_Amult28_Cmult29} {iopath_Amult28_Cmult30} {iopath_Amult28_Cmult31} {iopath_Amult28_Cmult32} {iopath_Amult28_Cmult33} {iopath_Amult28_Cmult34} {iopath_Amult28_Cmult35} {iopath_Amult28_Cmult36} {iopath_Amult28_Cmult37} {iopath_Amult28_Cmult38} {iopath_Amult28_Cmult39} {iopath_Amult28_Cmult40} {iopath_Amult28_Cmult41} {iopath_Amult28_Cmult42} {iopath_Amult28_Cmult43} {iopath_Amult28_Cmult44} {iopath_Amult28_Cmult45} {iopath_Amult28_Cmult46} {iopath_Amult28_Cmult47} {iopath_Amult28_Cmult48} {iopath_Amult28_Cmult49} {iopath_Amult28_Cmult50} {iopath_Amult28_Cmult51} {iopath_Amult28_Cmult52} {iopath_Amult28_Cmult53} {iopath_Amult28_Cmult54} {iopath_Amult28_Cmult55} {iopath_Amult28_Cmult56} {iopath_Amult28_Cmult57} {iopath_Amult28_Cmult58} {iopath_Amult28_Cmult59} {iopath_Amult28_Cmult60} {iopath_Amult28_Cmult61} {iopath_Amult28_Cmult62} {iopath_Amult28_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult29_Cmult29} {iopath_Amult29_Cmult30} {iopath_Amult29_Cmult31} {iopath_Amult29_Cmult32} {iopath_Amult29_Cmult33} {iopath_Amult29_Cmult34} {iopath_Amult29_Cmult35} {iopath_Amult29_Cmult36} {iopath_Amult29_Cmult37} {iopath_Amult29_Cmult38} {iopath_Amult29_Cmult39} {iopath_Amult29_Cmult40} {iopath_Amult29_Cmult41} {iopath_Amult29_Cmult42} {iopath_Amult29_Cmult43} {iopath_Amult29_Cmult44} {iopath_Amult29_Cmult45} {iopath_Amult29_Cmult46} {iopath_Amult29_Cmult47} {iopath_Amult29_Cmult48} {iopath_Amult29_Cmult49} {iopath_Amult29_Cmult50} {iopath_Amult29_Cmult51} {iopath_Amult29_Cmult52} {iopath_Amult29_Cmult53} {iopath_Amult29_Cmult54} {iopath_Amult29_Cmult55} {iopath_Amult29_Cmult56} {iopath_Amult29_Cmult57} {iopath_Amult29_Cmult58} {iopath_Amult29_Cmult59} {iopath_Amult29_Cmult60} {iopath_Amult29_Cmult61} {iopath_Amult29_Cmult62} {iopath_Amult29_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult30_Cmult30} {iopath_Amult30_Cmult31} {iopath_Amult30_Cmult32} {iopath_Amult30_Cmult33} {iopath_Amult30_Cmult34} {iopath_Amult30_Cmult35} {iopath_Amult30_Cmult36} {iopath_Amult30_Cmult37} {iopath_Amult30_Cmult38} {iopath_Amult30_Cmult39} {iopath_Amult30_Cmult40} {iopath_Amult30_Cmult41} {iopath_Amult30_Cmult42} {iopath_Amult30_Cmult43} {iopath_Amult30_Cmult44} {iopath_Amult30_Cmult45} {iopath_Amult30_Cmult46} {iopath_Amult30_Cmult47} {iopath_Amult30_Cmult48} {iopath_Amult30_Cmult49} {iopath_Amult30_Cmult50} {iopath_Amult30_Cmult51} {iopath_Amult30_Cmult52} {iopath_Amult30_Cmult53} {iopath_Amult30_Cmult54} {iopath_Amult30_Cmult55} {iopath_Amult30_Cmult56} {iopath_Amult30_Cmult57} {iopath_Amult30_Cmult58} {iopath_Amult30_Cmult59} {iopath_Amult30_Cmult60} {iopath_Amult30_Cmult61} {iopath_Amult30_Cmult62} {iopath_Amult30_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult31_Cmult31} {iopath_Amult31_Cmult32} {iopath_Amult31_Cmult33} {iopath_Amult31_Cmult34} {iopath_Amult31_Cmult35} {iopath_Amult31_Cmult36} {iopath_Amult31_Cmult37} {iopath_Amult31_Cmult38} {iopath_Amult31_Cmult39} {iopath_Amult31_Cmult40} {iopath_Amult31_Cmult41} {iopath_Amult31_Cmult42} {iopath_Amult31_Cmult43} {iopath_Amult31_Cmult44} {iopath_Amult31_Cmult45} {iopath_Amult31_Cmult46} {iopath_Amult31_Cmult47} {iopath_Amult31_Cmult48} {iopath_Amult31_Cmult49} {iopath_Amult31_Cmult50} {iopath_Amult31_Cmult51} {iopath_Amult31_Cmult52} {iopath_Amult31_Cmult53} {iopath_Amult31_Cmult54} {iopath_Amult31_Cmult55} {iopath_Amult31_Cmult56} {iopath_Amult31_Cmult57} {iopath_Amult31_Cmult58} {iopath_Amult31_Cmult59} {iopath_Amult31_Cmult60} {iopath_Amult31_Cmult61} {iopath_Amult31_Cmult62} {iopath_Amult31_Cmult63} ",
            "DELAY_MATRIX_Valid_mult": "1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 ",
            "DELAY_MATRIX_sel_mul_32x32": "1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 ",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:6.16-6.21"
          }
        },
        "Valid_mult": {
          "hide_name": 0,
          "bits": [ 66, 67 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:5.14-5.24"
          }
        },
        "sel_mul_32x32": {
          "hide_name": 0,
          "bits": [ 132 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:7.8-7.21"
          }
        }
      }
    }
  }
}
exitcode =======================================================================
0
================================================================================

is_blackbox True has_modes? False
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v; proc; cd MULT; select -write /tmp/tmprnt2rdgf c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_mult_mult.pb_type.xml
make -f quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_ipad.sim.v.dir/build.make quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_ipad.sim.v.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/vpr_pad /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_ipad.sim.v.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_ipad.sim.v.dir/build.make quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_ipad.sim.v.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating vpr_ipad.sim.v
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad && /usr/bin/cmake -E create_symlink /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/vpr_pad/vpr_ipad.sim.v /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/vpr_ipad.sim.v
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_vpr_pad_vpr_ipad.sim.v
make -f quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_ipad.model.xml.dir/build.make quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_ipad.model.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/vpr_pad /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_ipad.model.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_ipad.model.xml.dir/build.make quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_ipad.model.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating vpr_ipad.model.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=model -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/vpr_ipad.model.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/vpr_ipad.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/vpr_ipad.sim.v; prep -flatten; write_json -aig']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "VPR_IPAD": {
      "attributes": {
        "blackbox": "00000000000000000000000000000001",
        "CLASS": "input",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/vpr_ipad.sim.v:2.1-5.10"
      },
      "ports": {
        "inpad": {
          "direction": "output",
          "bits": [ 2 ]
        }
      },
      "cells": {
      },
      "netnames": {
        "inpad": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/vpr_ipad.sim.v:3.17-3.22"
          }
        }
      }
    }
  }
}
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_vpr_pad_vpr_ipad.model.xml
make -f quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_ipad.pb_type.xml.dir/build.make quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_ipad.pb_type.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/vpr_pad /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_ipad.pb_type.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_ipad.pb_type.xml.dir/build.make quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_ipad.pb_type.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating vpr_ipad.pb_type.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=pb_type -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/vpr_ipad.pb_type.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/vpr_ipad.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/vpr_ipad.sim.v; prep ; write_json ']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "VPR_IPAD": {
      "attributes": {
        "blackbox": "00000000000000000000000000000001",
        "CLASS": "input",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/vpr_ipad.sim.v:2.1-5.10"
      },
      "ports": {
        "inpad": {
          "direction": "output",
          "bits": [ 2 ]
        }
      },
      "cells": {
      },
      "netnames": {
        "inpad": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/vpr_ipad.sim.v:3.17-3.22"
          }
        }
      }
    }
  }
}
exitcode =======================================================================
0
================================================================================

is_blackbox True has_modes? False
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/vpr_ipad.sim.v; proc; cd VPR_IPAD; select -write /tmp/tmpjsr76xqs c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_vpr_pad_vpr_ipad.pb_type.xml
make -f quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_opad.sim.v.dir/build.make quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_opad.sim.v.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/vpr_pad /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_opad.sim.v.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_opad.sim.v.dir/build.make quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_opad.sim.v.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating vpr_opad.sim.v
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad && /usr/bin/cmake -E create_symlink /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/vpr_pad/vpr_opad.sim.v /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/vpr_opad.sim.v
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_vpr_pad_vpr_opad.sim.v
make -f quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_opad.pb_type.xml.dir/build.make quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_opad.pb_type.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/vpr_pad /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_opad.pb_type.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_opad.pb_type.xml.dir/build.make quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_opad.pb_type.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating vpr_opad.pb_type.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=pb_type -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/vpr_opad.pb_type.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/vpr_opad.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/vpr_opad.sim.v; prep ; write_json ']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "VPR_OPAD": {
      "attributes": {
        "blackbox": "00000000000000000000000000000001",
        "CLASS": "output",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/vpr_opad.sim.v:2.1-5.10"
      },
      "ports": {
        "outpad": {
          "direction": "input",
          "bits": [ 2 ]
        }
      },
      "cells": {
      },
      "netnames": {
        "outpad": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/vpr_opad.sim.v:3.17-3.23"
          }
        }
      }
    }
  }
}
exitcode =======================================================================
0
================================================================================

is_blackbox True has_modes? False
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/vpr_opad.sim.v; proc; cd VPR_OPAD; select -write /tmp/tmpyyxumnkt c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_vpr_pad_vpr_opad.pb_type.xml
make -f quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_opad.model.xml.dir/build.make quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_opad.model.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/vpr_pad /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_opad.model.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_opad.model.xml.dir/build.make quicklogic/primitives/vpr_pad/CMakeFiles/file_quicklogic_primitives_vpr_pad_vpr_opad.model.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating vpr_opad.model.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=model -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/vpr_opad.model.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/vpr_opad.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/vpr_opad.sim.v; prep -flatten; write_json -aig']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "VPR_OPAD": {
      "attributes": {
        "blackbox": "00000000000000000000000000000001",
        "CLASS": "output",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/vpr_opad.sim.v:2.1-5.10"
      },
      "ports": {
        "outpad": {
          "direction": "input",
          "bits": [ 2 ]
        }
      },
      "cells": {
      },
      "netnames": {
        "outpad": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vpr_pad/vpr_opad.sim.v:3.17-3.23"
          }
        }
      }
    }
  }
}
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_vpr_pad_vpr_opad.model.xml
make -f quicklogic/primitives/vcc/CMakeFiles/file_quicklogic_primitives_vcc_vcc.sim.v.dir/build.make quicklogic/primitives/vcc/CMakeFiles/file_quicklogic_primitives_vcc_vcc.sim.v.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/vcc /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vcc /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vcc/CMakeFiles/file_quicklogic_primitives_vcc_vcc.sim.v.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/vcc/CMakeFiles/file_quicklogic_primitives_vcc_vcc.sim.v.dir/build.make quicklogic/primitives/vcc/CMakeFiles/file_quicklogic_primitives_vcc_vcc.sim.v.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating vcc.sim.v
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vcc && /usr/bin/cmake -E create_symlink /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/vcc/vcc.sim.v /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vcc/vcc.sim.v
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_vcc_vcc.sim.v
make -f quicklogic/primitives/vcc/CMakeFiles/file_quicklogic_primitives_vcc_vcc.pb_type.xml.dir/build.make quicklogic/primitives/vcc/CMakeFiles/file_quicklogic_primitives_vcc_vcc.pb_type.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/vcc /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vcc /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vcc/CMakeFiles/file_quicklogic_primitives_vcc_vcc.pb_type.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/vcc/CMakeFiles/file_quicklogic_primitives_vcc_vcc.pb_type.xml.dir/build.make quicklogic/primitives/vcc/CMakeFiles/file_quicklogic_primitives_vcc_vcc.pb_type.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating vcc.pb_type.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=pb_type -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vcc/vcc.pb_type.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vcc/vcc.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vcc/vcc.sim.v; prep ; write_json ']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "VCC": {
      "attributes": {
        "whitebox": "00000000000000000000000000000001",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vcc/vcc.sim.v:2.1-8.10"
      },
      "ports": {
        "VCC": {
          "direction": "output",
          "bits": [ "1" ]
        }
      },
      "cells": {
      },
      "netnames": {
        "VCC": {
          "hide_name": 0,
          "bits": [ "1" ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vcc/vcc.sim.v:3.17-3.20"
          }
        }
      }
    }
  }
}
exitcode =======================================================================
0
================================================================================

is_blackbox True has_modes? False
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vcc/vcc.sim.v; proc; cd VCC; select -write /tmp/tmp4a4ju1oo c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_vcc_vcc.pb_type.xml
make -f quicklogic/primitives/vcc/CMakeFiles/file_quicklogic_primitives_vcc_vcc.model.xml.dir/build.make quicklogic/primitives/vcc/CMakeFiles/file_quicklogic_primitives_vcc_vcc.model.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/vcc /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vcc /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vcc/CMakeFiles/file_quicklogic_primitives_vcc_vcc.model.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/vcc/CMakeFiles/file_quicklogic_primitives_vcc_vcc.model.xml.dir/build.make quicklogic/primitives/vcc/CMakeFiles/file_quicklogic_primitives_vcc_vcc.model.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating vcc.model.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=model -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vcc/vcc.model.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vcc/vcc.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vcc/vcc.sim.v; prep -flatten; write_json -aig']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "VCC": {
      "attributes": {
        "whitebox": "00000000000000000000000000000001",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vcc/vcc.sim.v:2.1-8.10"
      },
      "ports": {
        "VCC": {
          "direction": "output",
          "bits": [ "1" ]
        }
      },
      "cells": {
      },
      "netnames": {
        "VCC": {
          "hide_name": 0,
          "bits": [ "1" ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vcc/vcc.sim.v:3.17-3.20"
          }
        }
      }
    }
  }
}
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vcc/vcc.sim.v; proc; cd VCC; select -write /tmp/tmp0oc9scvu c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/vcc/vcc.sim.v; proc; cd VCC; select -write /tmp/tmpia_gs71z VCC %co* o:* %i VCC %d']
stderr   =======================================================================
Warning: Selection "VCC" did not match any object.
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_vcc_vcc.model.xml
make -f quicklogic/primitives/gnd/CMakeFiles/file_quicklogic_primitives_gnd_gnd.sim.v.dir/build.make quicklogic/primitives/gnd/CMakeFiles/file_quicklogic_primitives_gnd_gnd.sim.v.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/gnd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/gnd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/gnd/CMakeFiles/file_quicklogic_primitives_gnd_gnd.sim.v.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/gnd/CMakeFiles/file_quicklogic_primitives_gnd_gnd.sim.v.dir/build.make quicklogic/primitives/gnd/CMakeFiles/file_quicklogic_primitives_gnd_gnd.sim.v.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating gnd.sim.v
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/gnd && /usr/bin/cmake -E create_symlink /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/gnd/gnd.sim.v /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/gnd/gnd.sim.v
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_gnd_gnd.sim.v
make -f quicklogic/primitives/gnd/CMakeFiles/file_quicklogic_primitives_gnd_gnd.pb_type.xml.dir/build.make quicklogic/primitives/gnd/CMakeFiles/file_quicklogic_primitives_gnd_gnd.pb_type.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/gnd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/gnd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/gnd/CMakeFiles/file_quicklogic_primitives_gnd_gnd.pb_type.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/gnd/CMakeFiles/file_quicklogic_primitives_gnd_gnd.pb_type.xml.dir/build.make quicklogic/primitives/gnd/CMakeFiles/file_quicklogic_primitives_gnd_gnd.pb_type.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating gnd.pb_type.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=pb_type -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/gnd/gnd.pb_type.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/gnd/gnd.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/gnd/gnd.sim.v; prep ; write_json ']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "GND": {
      "attributes": {
        "whitebox": "00000000000000000000000000000001",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/gnd/gnd.sim.v:2.1-8.10"
      },
      "ports": {
        "GND": {
          "direction": "output",
          "bits": [ "0" ]
        }
      },
      "cells": {
      },
      "netnames": {
        "GND": {
          "hide_name": 0,
          "bits": [ "0" ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/gnd/gnd.sim.v:3.17-3.20"
          }
        }
      }
    }
  }
}
exitcode =======================================================================
0
================================================================================

is_blackbox True has_modes? False
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/gnd/gnd.sim.v; proc; cd GND; select -write /tmp/tmp24bup1s9 c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_gnd_gnd.pb_type.xml
make -f quicklogic/primitives/gnd/CMakeFiles/file_quicklogic_primitives_gnd_gnd.model.xml.dir/build.make quicklogic/primitives/gnd/CMakeFiles/file_quicklogic_primitives_gnd_gnd.model.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/gnd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/gnd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/gnd/CMakeFiles/file_quicklogic_primitives_gnd_gnd.model.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/gnd/CMakeFiles/file_quicklogic_primitives_gnd_gnd.model.xml.dir/build.make quicklogic/primitives/gnd/CMakeFiles/file_quicklogic_primitives_gnd_gnd.model.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating gnd.model.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=model -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/gnd/gnd.model.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/gnd/gnd.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/gnd/gnd.sim.v; prep -flatten; write_json -aig']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "GND": {
      "attributes": {
        "whitebox": "00000000000000000000000000000001",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/gnd/gnd.sim.v:2.1-8.10"
      },
      "ports": {
        "GND": {
          "direction": "output",
          "bits": [ "0" ]
        }
      },
      "cells": {
      },
      "netnames": {
        "GND": {
          "hide_name": 0,
          "bits": [ "0" ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/gnd/gnd.sim.v:3.17-3.20"
          }
        }
      }
    }
  }
}
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/gnd/gnd.sim.v; proc; cd GND; select -write /tmp/tmpo3j_djpn c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/gnd/gnd.sim.v; proc; cd GND; select -write /tmp/tmp3jn6v127 GND %co* o:* %i GND %d']
stderr   =======================================================================
Warning: Selection "GND" did not match any object.
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_gnd_gnd.model.xml
make -f quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir_cell.sim.v.dir/build.make quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir_cell.sim.v.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/bidir /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir_cell.sim.v.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir_cell.sim.v.dir/build.make quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir_cell.sim.v.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating bidir_cell.sim.v
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir && /usr/bin/cmake -E create_symlink /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/bidir/bidir_cell.sim.v /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_bidir_bidir_cell.sim.v
make -f quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir_cell.model.xml.dir/build.make quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir_cell.model.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/bidir /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir_cell.model.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir_cell.model.xml.dir/build.make quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir_cell.model.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating bidir_cell.model.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=model -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.model.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v; prep -flatten; write_json -aig']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "BIDIR_CELL": {
      "attributes": {
        "whitebox": "00000000000000000000000000000001",
        "FASM_PARAMS": "INV.ESEL=ESEL;INV.OSEL=OSEL;INV.FIXHOLD=FIXHOLD;INV.WPD=WPD;INV.DS=DS",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:3.1-32.10"
      },
      "parameter_default_values": {
        "DS": "0",
        "ESEL": "0",
        "FIXHOLD": "0",
        "OSEL": "0",
        "WPD": "0"
      },
      "ports": {
        "I_PAD_$inp": {
          "direction": "input",
          "bits": [ 2 ]
        },
        "I_DAT": {
          "direction": "output",
          "bits": [ 3 ]
        },
        "I_EN": {
          "direction": "input",
          "bits": [ 4 ]
        },
        "O_PAD_$out": {
          "direction": "output",
          "bits": [ 5 ]
        },
        "O_DAT": {
          "direction": "input",
          "bits": [ 6 ]
        },
        "O_EN": {
          "direction": "input",
          "bits": [ 7 ]
        }
      },
      "cells": {
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:29$1": {
          "hide_name": 1,
          "type": "$eq",
          "model": "$eq:1U:1U:1",
          "parameters": {
            "A_SIGNED": "00000000000000000000000000000000",
            "A_WIDTH": "00000000000000000000000000000001",
            "B_SIGNED": "00000000000000000000000000000000",
            "B_WIDTH": "00000000000000000000000000000001",
            "Y_WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:29.21-29.33"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 4 ],
            "B": [ "1" ],
            "Y": [ 8 ]
          }
        },
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:30$3": {
          "hide_name": 1,
          "type": "$eq",
          "model": "$eq:1U:1U:1",
          "parameters": {
            "A_SIGNED": "00000000000000000000000000000000",
            "A_WIDTH": "00000000000000000000000000000001",
            "B_SIGNED": "00000000000000000000000000000000",
            "B_WIDTH": "00000000000000000000000000000001",
            "Y_WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:30.26-30.38"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 7 ],
            "B": [ "1" ],
            "Y": [ 9 ]
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:29$2": {
          "hide_name": 1,
          "type": "$mux",
          "model": "$mux:1",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:29.20-29.54"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ "0" ],
            "B": [ 2 ],
            "S": [ 8 ],
            "Y": [ 3 ]
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:30$4": {
          "hide_name": 1,
          "type": "$mux",
          "model": "$mux:1",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:30.25-30.54"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ "0" ],
            "B": [ 6 ],
            "S": [ 9 ],
            "Y": [ 5 ]
          }
        }
      },
      "netnames": {
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:29$1_Y": {
          "hide_name": 1,
          "bits": [ 8 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:29.21-29.33"
          }
        },
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:30$3_Y": {
          "hide_name": 1,
          "bits": [ 9 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:30.26-30.38"
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:29$2_Y": {
          "hide_name": 1,
          "bits": [ 3 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:29.20-29.54"
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:30$4_Y": {
          "hide_name": 1,
          "bits": [ 5 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:30.25-30.54"
          }
        },
        "I_DAT": {
          "hide_name": 0,
          "bits": [ 3 ],
          "attributes": {
            "DELAY_CONST_I_EN": "1e-10",
            "DELAY_CONST_I_PAD_$inp": "{iopath_IP_IZ}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:15.17-15.22"
          }
        },
        "I_EN": {
          "hide_name": 0,
          "bits": [ 4 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:8.17-8.21"
          }
        },
        "I_PAD_$inp": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:7.17-7.27"
          }
        },
        "O_DAT": {
          "hide_name": 0,
          "bits": [ 6 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:10.17-10.22"
          }
        },
        "O_EN": {
          "hide_name": 0,
          "bits": [ 7 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:11.17-11.21"
          }
        },
        "O_PAD_$out": {
          "hide_name": 0,
          "bits": [ 5 ],
          "attributes": {
            "DELAY_CONST_O_DAT": "{iopath_OQI_IP}",
            "DELAY_CONST_O_EN": "{iopath_IE_IP}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:19.17-19.27"
          }
        }
      }
    }
  },
  "models": {
    "$mux:1": [
      /*   0 */ [ "port", "S", 0 ],
      /*   1 */ [ "port", "A", 0 ],
      /*   2 */ [ "port", "B", 0 ],
      /*   3 */ [ "nport", "S", 0 ],
      /*   4 */ [ "nand", 0, 2 ],
      /*   5 */ [ "nand", 1, 3 ],
      /*   6 */ [ "nand", 4, 5, "Y", 0 ]
    ],
    "$eq:1U:1U:1": [
      /*   0 */ [ "port", "A", 0 ],
      /*   1 */ [ "port", "B", 0 ],
      /*   2 */ [ "nport", "B", 0 ],
      /*   3 */ [ "nport", "A", 0 ],
      /*   4 */ [ "nand", 2, 3 ],
      /*   5 */ [ "nand", 0, 1 ],
      /*   6 */ [ "nand", 4, 5, "Y", 0 ]
    ]
  }
}
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v; proc; cd BIDIR_CELL; select -write /tmp/tmp2ez03bje c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v; proc; cd BIDIR_CELL; select -write /tmp/tmp2n1afxfo I_DAT %co* o:* %i I_DAT %d']
stderr   =======================================================================
Warning: Selection "I_DAT" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v; proc; cd BIDIR_CELL; select -write /tmp/tmpcs6m1wwh I_EN %co* o:* %i I_EN %d']
stderr   =======================================================================
Warning: Selection "I_EN" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v; proc; cd BIDIR_CELL; select -write /tmp/tmpt9buaqrv I_PAD_$inp %co* o:* %i I_PAD_$inp %d']
stderr   =======================================================================
Warning: Selection "I_PAD_$inp" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v; proc; cd BIDIR_CELL; select -write /tmp/tmp85wgpkkc O_DAT %co* o:* %i O_DAT %d']
stderr   =======================================================================
Warning: Selection "O_DAT" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v; proc; cd BIDIR_CELL; select -write /tmp/tmpz2bfrsoh O_EN %co* o:* %i O_EN %d']
stderr   =======================================================================
Warning: Selection "O_EN" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v; proc; cd BIDIR_CELL; select -write /tmp/tmp3_p_v176 O_PAD_$out %co* o:* %i O_PAD_$out %d']
stderr   =======================================================================
Warning: Selection "O_PAD_$out" did not match any object.
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_bidir_bidir_cell.model.xml
make -f quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir_cell.pb_type.xml.dir/build.make quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir_cell.pb_type.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/bidir /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir_cell.pb_type.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir_cell.pb_type.xml.dir/build.make quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir_cell.pb_type.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating bidir_cell.pb_type.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=pb_type -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.pb_type.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v; prep ; write_json ']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "BIDIR_CELL": {
      "attributes": {
        "whitebox": "00000000000000000000000000000001",
        "FASM_PARAMS": "INV.ESEL=ESEL;INV.OSEL=OSEL;INV.FIXHOLD=FIXHOLD;INV.WPD=WPD;INV.DS=DS",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:3.1-32.10"
      },
      "parameter_default_values": {
        "DS": "0",
        "ESEL": "0",
        "FIXHOLD": "0",
        "OSEL": "0",
        "WPD": "0"
      },
      "ports": {
        "I_PAD_$inp": {
          "direction": "input",
          "bits": [ 2 ]
        },
        "I_DAT": {
          "direction": "output",
          "bits": [ 3 ]
        },
        "I_EN": {
          "direction": "input",
          "bits": [ 4 ]
        },
        "O_PAD_$out": {
          "direction": "output",
          "bits": [ 5 ]
        },
        "O_DAT": {
          "direction": "input",
          "bits": [ 6 ]
        },
        "O_EN": {
          "direction": "input",
          "bits": [ 7 ]
        }
      },
      "cells": {
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:29$1": {
          "hide_name": 1,
          "type": "$eq",
          "parameters": {
            "A_SIGNED": "00000000000000000000000000000000",
            "A_WIDTH": "00000000000000000000000000000001",
            "B_SIGNED": "00000000000000000000000000000000",
            "B_WIDTH": "00000000000000000000000000000001",
            "Y_WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:29.21-29.33"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 4 ],
            "B": [ "1" ],
            "Y": [ 8 ]
          }
        },
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:30$3": {
          "hide_name": 1,
          "type": "$eq",
          "parameters": {
            "A_SIGNED": "00000000000000000000000000000000",
            "A_WIDTH": "00000000000000000000000000000001",
            "B_SIGNED": "00000000000000000000000000000000",
            "B_WIDTH": "00000000000000000000000000000001",
            "Y_WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:30.26-30.38"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 7 ],
            "B": [ "1" ],
            "Y": [ 9 ]
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:29$2": {
          "hide_name": 1,
          "type": "$mux",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:29.20-29.54"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ "0" ],
            "B": [ 2 ],
            "S": [ 8 ],
            "Y": [ 3 ]
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:30$4": {
          "hide_name": 1,
          "type": "$mux",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:30.25-30.54"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ "0" ],
            "B": [ 6 ],
            "S": [ 9 ],
            "Y": [ 5 ]
          }
        }
      },
      "netnames": {
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:29$1_Y": {
          "hide_name": 1,
          "bits": [ 8 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:29.21-29.33"
          }
        },
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:30$3_Y": {
          "hide_name": 1,
          "bits": [ 9 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:30.26-30.38"
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:29$2_Y": {
          "hide_name": 1,
          "bits": [ 3 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:29.20-29.54"
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:30$4_Y": {
          "hide_name": 1,
          "bits": [ 5 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:30.25-30.54"
          }
        },
        "I_DAT": {
          "hide_name": 0,
          "bits": [ 3 ],
          "attributes": {
            "DELAY_CONST_I_EN": "1e-10",
            "DELAY_CONST_I_PAD_$inp": "{iopath_IP_IZ}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:15.17-15.22"
          }
        },
        "I_EN": {
          "hide_name": 0,
          "bits": [ 4 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:8.17-8.21"
          }
        },
        "I_PAD_$inp": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:7.17-7.27"
          }
        },
        "O_DAT": {
          "hide_name": 0,
          "bits": [ 6 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:10.17-10.22"
          }
        },
        "O_EN": {
          "hide_name": 0,
          "bits": [ 7 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:11.17-11.21"
          }
        },
        "O_PAD_$out": {
          "hide_name": 0,
          "bits": [ 5 ],
          "attributes": {
            "DELAY_CONST_O_DAT": "{iopath_OQI_IP}",
            "DELAY_CONST_O_EN": "{iopath_IE_IP}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v:19.17-19.27"
          }
        }
      }
    }
  }
}
exitcode =======================================================================
0
================================================================================

is_blackbox True has_modes? False
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir_cell.sim.v; proc; cd BIDIR_CELL; select -write /tmp/tmpk8tsugz1 c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_bidir_bidir_cell.pb_type.xml
make -f quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir.sim.v.dir/build.make quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir.sim.v.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/bidir /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir.sim.v.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir.sim.v.dir/build.make quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir.sim.v.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating bidir.sim.v
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir && /usr/bin/cmake -E create_symlink /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/bidir/bidir.sim.v /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_bidir_bidir.sim.v
make -f quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir.pb_type.xml.dir/build.make quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir.pb_type.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/bidir /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir.pb_type.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir.pb_type.xml.dir/build.make quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir.pb_type.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating bidir.pb_type.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=pb_type -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.pb_type.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v; prep ; write_json ']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "BIDIR": {
      "attributes": {
        "MODES": "INPUT;OUTPUT;INOUT",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:6.1-98.10"
      },
      "parameter_default_values": {
        "MODE": "INPUT"
      },
      "ports": {
        "IE": {
          "direction": "input",
          "bits": [ 2 ]
        },
        "IQC": {
          "direction": "input",
          "bits": [ 3 ]
        },
        "OQI": {
          "direction": "input",
          "bits": [ 4 ]
        },
        "OQE": {
          "direction": "input",
          "bits": [ 5 ]
        },
        "IQE": {
          "direction": "input",
          "bits": [ 6 ]
        },
        "IQR": {
          "direction": "input",
          "bits": [ 7 ]
        },
        "INEN": {
          "direction": "input",
          "bits": [ 8 ]
        },
        "IQIN": {
          "direction": "input",
          "bits": [ 9 ]
        },
        "IZ": {
          "direction": "output",
          "bits": [ 10 ]
        },
        "IQZ": {
          "direction": "output",
          "bits": [ 11 ]
        }
      },
      "cells": {
        "bidir": {
          "hide_name": 0,
          "type": "BIDIR_CELL",
          "parameters": {
          },
          "attributes": {
            "FASM_PREFIX": "INTERFACE.BIDIR",
            "keep": "00000000000000000000000000000001",
            "module_not_derived": "00000000000000000000000000000001",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:61.20-68.10"
          },
          "port_directions": {
            "I_DAT": "output",
            "I_EN": "input",
            "I_PAD_$inp": "input",
            "O_DAT": "input",
            "O_EN": "input",
            "O_PAD_$out": "output"
          },
          "connections": {
            "I_DAT": [ 10 ],
            "I_EN": [ 8 ],
            "I_PAD_$inp": [ 12 ],
            "O_DAT": [ 4 ],
            "O_EN": [ 2 ],
            "O_PAD_$out": [ ]
          }
        },
        "inpad": {
          "hide_name": 0,
          "type": "VPR_IPAD",
          "parameters": {
          },
          "attributes": {
            "keep": "00000000000000000000000000000001",
            "module_not_derived": "00000000000000000000000000000001",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:28.18-28.30"
          },
          "port_directions": {
            "inpad": "output"
          },
          "connections": {
            "inpad": [ 12 ]
          }
        }
      },
      "netnames": {
        "IE": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:7.17-7.19"
          }
        },
        "INEN": {
          "hide_name": 0,
          "bits": [ 8 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:13.17-13.21"
          }
        },
        "IQC": {
          "hide_name": 0,
          "bits": [ 3 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:8.17-8.20"
          }
        },
        "IQE": {
          "hide_name": 0,
          "bits": [ 6 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:11.17-11.20"
          }
        },
        "IQIN": {
          "hide_name": 0,
          "bits": [ 9 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:14.17-14.21"
          }
        },
        "IQR": {
          "hide_name": 0,
          "bits": [ 7 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:12.17-12.20"
          }
        },
        "IQZ": {
          "hide_name": 0,
          "bits": [ 11 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:16.17-16.20"
          }
        },
        "IZ": {
          "hide_name": 0,
          "bits": [ 10 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:15.17-15.19"
          }
        },
        "OQE": {
          "hide_name": 0,
          "bits": [ 5 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:10.17-10.20"
          }
        },
        "OQI": {
          "hide_name": 0,
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stderr   =======================================================================
Warning: Wire BIDIR.\IQZ is used but has no driver.
exitcode =======================================================================
0
================================================================================

is_blackbox False has_modes? True
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v; proc; cd BIDIR; select -write /tmp/tmpkncdo_yk c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v; chparam -set MODE "INPUT" BIDIR; prep ; write_json ']
stdout   =======================================================================
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          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:30$4_Y": {
          "hide_name": 1,
          "bits": [ 5 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:30.25-30.54"
          }
        },
        "I_DAT": {
          "hide_name": 0,
          "bits": [ 3 ],
          "attributes": {
            "DELAY_CONST_I_EN": "1e-10",
            "DELAY_CONST_I_PAD_$inp": "{iopath_IP_IZ}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:15.17-15.22"
          }
        },
        "I_EN": {
          "hide_name": 0,
          "bits": [ 4 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:8.17-8.21"
          }
        },
        "I_PAD_$inp": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:7.17-7.27"
          }
        },
        "O_DAT": {
          "hide_name": 0,
          "bits": [ 6 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:10.17-10.22"
          }
        },
        "O_EN": {
          "hide_name": 0,
          "bits": [ 7 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:11.17-11.21"
          }
        },
        "O_PAD_$out": {
          "hide_name": 0,
          "bits": [ 5 ],
          "attributes": {
            "DELAY_CONST_O_DAT": "{iopath_OQI_IP}",
            "DELAY_CONST_O_EN": "{iopath_IE_IP}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:19.17-19.27"
          }
        }
      }
    },
    "VPR_IPAD": {
      "attributes": {
        "blackbox": "00000000000000000000000000000001",
        "CLASS": "input",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/../vpr_pad/vpr_ipad.sim.v:2.1-5.10"
      },
      "ports": {
        "inpad": {
          "direction": "output",
          "bits": [ 2 ]
        }
      },
      "cells": {
      },
      "netnames": {
        "inpad": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/../vpr_pad/vpr_ipad.sim.v:3.17-3.22"
          }
        }
      }
    },
    "VPR_OPAD": {
      "attributes": {
        "blackbox": "00000000000000000000000000000001",
        "CLASS": "output",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/../vpr_pad/vpr_opad.sim.v:2.1-5.10"
      },
      "ports": {
        "outpad": {
          "direction": "input",
          "bits": [ 2 ]
        }
      },
      "cells": {
      },
      "netnames": {
        "outpad": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/../vpr_pad/vpr_opad.sim.v:3.17-3.23"
          }
        }
      }
    }
  }
}
stderr   =======================================================================
Warning: Wire BIDIR.\IQZ is used but has no driver.
exitcode =======================================================================
0
================================================================================

is_blackbox False has_modes? True
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v; proc; cd BIDIR; select -write /tmp/tmpdh_4ywzd c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

[[(('bidir', 'I_EN'), {})],
 [(('bidir', 'I_PAD_$inp'), {'pack': 'IPAD_TO_BIDIR'})],
 [(('bidir', 'O_DAT'), {})],
 [(('bidir', 'O_EN'), {})],
 [((None, 'IZ'),
   {'DELAY_CONST_I_EN': '1e-10', 'DELAY_CONST_I_PAD_$inp': '{iopath_IP_IZ}'})]]
BIDIR
--
defaultdict(<class 'list'>,
            {(None, 'IE'): [(('bidir', 'O_EN'), {})],
             (None, 'INEN'): [(('bidir', 'I_EN'), {})],
             ('bidir', 'I_DAT'): [((None, 'IZ'),
                                   {'DELAY_CONST_I_EN': '1e-10',
                                    'DELAY_CONST_I_PAD_$inp': '{iopath_IP_IZ}'})],
             (None, 'OQI'): [(('bidir', 'O_DAT'), {})],
             ('inpad', 'inpad'): [(('bidir', 'I_PAD_$inp'),
                                   {'pack': 'IPAD_TO_BIDIR'})]})
--
[]
{}
--
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v; chparam -set MODE "OUTPUT" BIDIR; prep ; write_json ']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "BIDIR": {
      "attributes": {
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:6.1-98.10",
        "hdlname": "\\BIDIR",
        "MODES": "INPUT;OUTPUT;INOUT"
      },
      "parameter_default_values": {
        "MODE": "OUTPUT"
      },
      "ports": {
        "IE": {
          "direction": "input",
          "bits": [ 2 ]
        },
        "IQC": {
          "direction": "input",
          "bits": [ 3 ]
        },
        "OQI": {
          "direction": "input",
          "bits": [ 4 ]
        },
        "OQE": {
          "direction": "input",
          "bits": [ 5 ]
        },
        "IQE": {
          "direction": "input",
          "bits": [ 6 ]
        },
        "IQR": {
          "direction": "input",
          "bits": [ 7 ]
        },
        "INEN": {
          "direction": "input",
          "bits": [ 8 ]
        },
        "IQIN": {
          "direction": "input",
          "bits": [ 9 ]
        },
        "IZ": {
          "direction": "output",
          "bits": [ 10 ]
        },
        "IQZ": {
          "direction": "output",
          "bits": [ 11 ]
        }
      },
      "cells": {
        "bidir": {
          "hide_name": 0,
          "type": "BIDIR_CELL",
          "parameters": {
          },
          "attributes": {
            "FASM_PREFIX": "INTERFACE.BIDIR",
            "keep": "00000000000000000000000000000001",
            "module_not_derived": "00000000000000000000000000000001",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:74.20-81.10"
          },
          "port_directions": {
            "I_DAT": "output",
            "I_EN": "input",
            "I_PAD_$inp": "input",
            "O_DAT": "input",
            "O_EN": "input",
            "O_PAD_$out": "output"
          },
          "connections": {
            "I_DAT": [ 10 ],
            "I_EN": [ 8 ],
            "I_PAD_$inp": [ ],
            "O_DAT": [ 4 ],
            "O_EN": [ 2 ],
            "O_PAD_$out": [ 12 ]
          }
        },
        "outpad": {
          "hide_name": 0,
          "type": "VPR_OPAD",
          "parameters": {
          },
          "attributes": {
            "keep": "00000000000000000000000000000001",
            "module_not_derived": "00000000000000000000000000000001",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:37.18-37.31"
          },
          "port_directions": {
            "outpad": "input"
          },
          "connections": {
            "outpad": [ 12 ]
          }
        }
      },
      "netnames": {
        "IE": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:7.17-7.19"
          }
        },
        "INEN": {
          "hide_name": 0,
          "bits": [ 8 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:13.17-13.21"
          }
        },
        "IQC": {
          "hide_name": 0,
          "bits": [ 3 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:8.17-8.20"
          }
        },
        "IQE": {
          "hide_name": 0,
          "bits": [ 6 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:11.17-11.20"
          }
        },
        "IQIN": {
          "hide_name": 0,
          "bits": [ 9 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:14.17-14.21"
          }
        },
        "IQR": {
          "hide_name": 0,
          "bits": [ 7 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:12.17-12.20"
          }
        },
        "IQZ": {
          "hide_name": 0,
          "bits": [ 11 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:16.17-16.20"
          }
        },
        "IZ": {
          "hide_name": 0,
          "bits": [ 10 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:15.17-15.19"
          }
        },
        "OQE": {
          "hide_name": 0,
          "bits": [ 5 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:10.17-10.20"
          }
        },
        "OQI": {
          "hide_name": 0,
          "bits": [ 4 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:9.17-9.20"
          }
        },
        "o_pad": {
          "hide_name": 0,
          "bits": [ 12 ],
          "attributes": {
            "pack": "BIDIR_TO_OPAD",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:34.14-34.19"
          }
        }
      }
    },
    "BIDIR_CELL": {
      "attributes": {
        "whitebox": "00000000000000000000000000000001",
        "FASM_PARAMS": "INV.ESEL=ESEL;INV.OSEL=OSEL;INV.FIXHOLD=FIXHOLD;INV.WPD=WPD;INV.DS=DS",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:3.1-32.10"
      },
      "parameter_default_values": {
        "DS": "0",
        "ESEL": "0",
        "FIXHOLD": "0",
        "OSEL": "0",
        "WPD": "0"
      },
      "ports": {
        "I_PAD_$inp": {
          "direction": "input",
          "bits": [ 2 ]
        },
        "I_DAT": {
          "direction": "output",
          "bits": [ 3 ]
        },
        "I_EN": {
          "direction": "input",
          "bits": [ 4 ]
        },
        "O_PAD_$out": {
          "direction": "output",
          "bits": [ 5 ]
        },
        "O_DAT": {
          "direction": "input",
          "bits": [ 6 ]
        },
        "O_EN": {
          "direction": "input",
          "bits": [ 7 ]
        }
      },
      "cells": {
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:29$1": {
          "hide_name": 1,
          "type": "$eq",
          "parameters": {
            "A_SIGNED": "00000000000000000000000000000000",
            "A_WIDTH": "00000000000000000000000000000001",
            "B_SIGNED": "00000000000000000000000000000000",
            "B_WIDTH": "00000000000000000000000000000001",
            "Y_WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:29.21-29.33"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 4 ],
            "B": [ "1" ],
            "Y": [ 8 ]
          }
        },
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:30$3": {
          "hide_name": 1,
          "type": "$eq",
          "parameters": {
            "A_SIGNED": "00000000000000000000000000000000",
            "A_WIDTH": "00000000000000000000000000000001",
            "B_SIGNED": "00000000000000000000000000000000",
            "B_WIDTH": "00000000000000000000000000000001",
            "Y_WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:30.26-30.38"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 7 ],
            "B": [ "1" ],
            "Y": [ 9 ]
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:29$2": {
          "hide_name": 1,
          "type": "$mux",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:29.20-29.54"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ "0" ],
            "B": [ 2 ],
            "S": [ 8 ],
            "Y": [ 3 ]
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:30$4": {
          "hide_name": 1,
          "type": "$mux",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:30.25-30.54"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ "0" ],
            "B": [ 6 ],
            "S": [ 9 ],
            "Y": [ 5 ]
          }
        }
      },
      "netnames": {
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:29$1_Y": {
          "hide_name": 1,
          "bits": [ 8 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:29.21-29.33"
          }
        },
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:30$3_Y": {
          "hide_name": 1,
          "bits": [ 9 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:30.26-30.38"
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:29$2_Y": {
          "hide_name": 1,
          "bits": [ 3 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:29.20-29.54"
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:30$4_Y": {
          "hide_name": 1,
          "bits": [ 5 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:30.25-30.54"
          }
        },
        "I_DAT": {
          "hide_name": 0,
          "bits": [ 3 ],
          "attributes": {
            "DELAY_CONST_I_EN": "1e-10",
            "DELAY_CONST_I_PAD_$inp": "{iopath_IP_IZ}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:15.17-15.22"
          }
        },
        "I_EN": {
          "hide_name": 0,
          "bits": [ 4 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:8.17-8.21"
          }
        },
        "I_PAD_$inp": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:7.17-7.27"
          }
        },
        "O_DAT": {
          "hide_name": 0,
          "bits": [ 6 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:10.17-10.22"
          }
        },
        "O_EN": {
          "hide_name": 0,
          "bits": [ 7 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:11.17-11.21"
          }
        },
        "O_PAD_$out": {
          "hide_name": 0,
          "bits": [ 5 ],
          "attributes": {
            "DELAY_CONST_O_DAT": "{iopath_OQI_IP}",
            "DELAY_CONST_O_EN": "{iopath_IE_IP}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:19.17-19.27"
          }
        }
      }
    },
    "VPR_IPAD": {
      "attributes": {
        "blackbox": "00000000000000000000000000000001",
        "CLASS": "input",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/../vpr_pad/vpr_ipad.sim.v:2.1-5.10"
      },
      "ports": {
        "inpad": {
          "direction": "output",
          "bits": [ 2 ]
        }
      },
      "cells": {
      },
      "netnames": {
        "inpad": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/../vpr_pad/vpr_ipad.sim.v:3.17-3.22"
          }
        }
      }
    },
    "VPR_OPAD": {
      "attributes": {
        "blackbox": "00000000000000000000000000000001",
        "CLASS": "output",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/../vpr_pad/vpr_opad.sim.v:2.1-5.10"
      },
      "ports": {
        "outpad": {
          "direction": "input",
          "bits": [ 2 ]
        }
      },
      "cells": {
      },
      "netnames": {
        "outpad": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/../vpr_pad/vpr_opad.sim.v:3.17-3.23"
          }
        }
      }
    }
  }
}
stderr   =======================================================================
Warning: Wire BIDIR.\IQZ is used but has no driver.
exitcode =======================================================================
0
================================================================================

is_blackbox False has_modes? True
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v; proc; cd BIDIR; select -write /tmp/tmpbkgheend c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

[[(('bidir', 'I_EN'), {})],
 [(('bidir', 'O_DAT'), {})],
 [(('bidir', 'O_EN'), {})],
 [((None, 'IZ'),
   {'DELAY_CONST_I_EN': '1e-10', 'DELAY_CONST_I_PAD_$inp': '{iopath_IP_IZ}'})],
 [(('outpad', 'outpad'), {'pack': 'BIDIR_TO_OPAD'})]]
BIDIR
--
defaultdict(<class 'list'>,
            {('bidir', 'I_DAT'): [((None, 'IZ'),
                                   {'DELAY_CONST_I_EN': '1e-10',
                                    'DELAY_CONST_I_PAD_$inp': '{iopath_IP_IZ}'})],
             ('bidir', 'O_PAD_$out'): [(('outpad', 'outpad'),
                                        {'pack': 'BIDIR_TO_OPAD'})],
             (None, 'IE'): [(('bidir', 'O_EN'), {})],
             (None, 'INEN'): [(('bidir', 'I_EN'), {})],
             (None, 'OQI'): [(('bidir', 'O_DAT'), {})]})
--
[]
{}
--
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v; chparam -set MODE "INOUT" BIDIR; prep ; write_json ']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "BIDIR": {
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        "hdlname": "\\BIDIR",
        "MODES": "INPUT;OUTPUT;INOUT"
      },
      "parameter_default_values": {
        "MODE": "INOUT"
      },
      "ports": {
        "IE": {
          "direction": "input",
          "bits": [ 2 ]
        },
        "IQC": {
          "direction": "input",
          "bits": [ 3 ]
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        "OQI": {
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          "bits": [ 4 ]
        },
        "OQE": {
          "direction": "input",
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        "IQE": {
          "direction": "input",
          "bits": [ 6 ]
        },
        "IQR": {
          "direction": "input",
          "bits": [ 7 ]
        },
        "INEN": {
          "direction": "input",
          "bits": [ 8 ]
        },
        "IQIN": {
          "direction": "input",
          "bits": [ 9 ]
        },
        "IZ": {
          "direction": "output",
          "bits": [ 10 ]
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        "IQZ": {
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          "bits": [ 11 ]
        }
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      "cells": {
        "bidir": {
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          "type": "BIDIR_CELL",
          "parameters": {
          },
          "attributes": {
            "FASM_PREFIX": "INTERFACE.BIDIR",
            "keep": "00000000000000000000000000000001",
            "module_not_derived": "00000000000000000000000000000001",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:87.20-94.10"
          },
          "port_directions": {
            "I_DAT": "output",
            "I_EN": "input",
            "I_PAD_$inp": "input",
            "O_DAT": "input",
            "O_EN": "input",
            "O_PAD_$out": "output"
          },
          "connections": {
            "I_DAT": [ 10 ],
            "I_EN": [ 8 ],
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          "parameters": {
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            "module_not_derived": "00000000000000000000000000000001",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:49.18-49.30"
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            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:52.18-52.31"
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          "bits": [ 10 ],
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          "hide_name": 0,
          "bits": [ 5 ],
          "attributes": {
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          }
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        "i_pad": {
          "hide_name": 0,
          "bits": [ 12 ],
          "attributes": {
            "pack": "IOPAD_TO_BIDIR",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:43.14-43.19"
          }
        },
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          "hide_name": 0,
          "bits": [ 13 ],
          "attributes": {
            "pack": "IOPAD_TO_BIDIR",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:46.14-46.19"
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    "BIDIR_CELL": {
      "attributes": {
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        "FASM_PARAMS": "INV.ESEL=ESEL;INV.OSEL=OSEL;INV.FIXHOLD=FIXHOLD;INV.WPD=WPD;INV.DS=DS",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:3.1-32.10"
      },
      "parameter_default_values": {
        "DS": "0",
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      "ports": {
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        "I_DAT": {
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        "I_EN": {
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        "O_PAD_$out": {
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      "cells": {
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:29$1": {
          "hide_name": 1,
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          "connections": {
            "A": [ 4 ],
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          }
        },
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:30$3": {
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          "connections": {
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        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:29$2": {
          "hide_name": 1,
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        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:30$4": {
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      "netnames": {
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        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:30$3_Y": {
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        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:29$2_Y": {
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          "hide_name": 0,
          "bits": [ 3 ],
          "attributes": {
            "DELAY_CONST_I_EN": "1e-10",
            "DELAY_CONST_I_PAD_$inp": "{iopath_IP_IZ}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:15.17-15.22"
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          "hide_name": 0,
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            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:8.17-8.21"
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        "I_PAD_$inp": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:7.17-7.27"
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        },
        "O_DAT": {
          "hide_name": 0,
          "bits": [ 6 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:10.17-10.22"
          }
        },
        "O_EN": {
          "hide_name": 0,
          "bits": [ 7 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:11.17-11.21"
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        "O_PAD_$out": {
          "hide_name": 0,
          "bits": [ 5 ],
          "attributes": {
            "DELAY_CONST_O_DAT": "{iopath_OQI_IP}",
            "DELAY_CONST_O_EN": "{iopath_IE_IP}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/./bidir_cell.sim.v:19.17-19.27"
          }
        }
      }
    },
    "VPR_IPAD": {
      "attributes": {
        "blackbox": "00000000000000000000000000000001",
        "CLASS": "input",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/../vpr_pad/vpr_ipad.sim.v:2.1-5.10"
      },
      "ports": {
        "inpad": {
          "direction": "output",
          "bits": [ 2 ]
        }
      },
      "cells": {
      },
      "netnames": {
        "inpad": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/../vpr_pad/vpr_ipad.sim.v:3.17-3.22"
          }
        }
      }
    },
    "VPR_OPAD": {
      "attributes": {
        "blackbox": "00000000000000000000000000000001",
        "CLASS": "output",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/../vpr_pad/vpr_opad.sim.v:2.1-5.10"
      },
      "ports": {
        "outpad": {
          "direction": "input",
          "bits": [ 2 ]
        }
      },
      "cells": {
      },
      "netnames": {
        "outpad": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/../vpr_pad/vpr_opad.sim.v:3.17-3.23"
          }
        }
      }
    }
  }
}
stderr   =======================================================================
Warning: Wire BIDIR.\IQZ is used but has no driver.
exitcode =======================================================================
0
================================================================================

is_blackbox False has_modes? True
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v; proc; cd BIDIR; select -write /tmp/tmpt8adgtgf c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

[[(('bidir', 'I_EN'), {})],
 [(('bidir', 'I_PAD_$inp'), {'pack': 'IOPAD_TO_BIDIR'})],
 [(('bidir', 'O_DAT'), {})],
 [(('bidir', 'O_EN'), {})],
 [((None, 'IZ'),
   {'DELAY_CONST_I_EN': '1e-10', 'DELAY_CONST_I_PAD_$inp': '{iopath_IP_IZ}'})],
 [(('outpad', 'outpad'), {'pack': 'IOPAD_TO_BIDIR'})]]
BIDIR
--
defaultdict(<class 'list'>,
            {('bidir', 'I_DAT'): [((None, 'IZ'),
                                   {'DELAY_CONST_I_EN': '1e-10',
                                    'DELAY_CONST_I_PAD_$inp': '{iopath_IP_IZ}'})],
             ('bidir', 'O_PAD_$out'): [(('outpad', 'outpad'),
                                        {'pack': 'IOPAD_TO_BIDIR'})],
             ('inpad', 'inpad'): [(('bidir', 'I_PAD_$inp'),
                                   {'pack': 'IOPAD_TO_BIDIR'})],
             (None, 'IE'): [(('bidir', 'O_EN'), {})],
             (None, 'INEN'): [(('bidir', 'I_EN'), {})],
             (None, 'OQI'): [(('bidir', 'O_DAT'), {})]})
--
[]
{}
--
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_bidir_bidir.pb_type.xml
make -f quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir.model.xml.dir/build.make quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir.model.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/bidir /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir.model.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir.model.xml.dir/build.make quicklogic/primitives/bidir/CMakeFiles/file_quicklogic_primitives_bidir_bidir.model.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating bidir.model.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=model -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.model.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v; prep -flatten; write_json -aig']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "BIDIR": {
      "attributes": {
        "MODES": "INPUT;OUTPUT;INOUT",
        "top": "00000000000000000000000000000001",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/bidir/bidir.sim.v:6.1-98.10"
      },
      "parameter_default_values": {
        "MODE": "INPUT"
      },
      "ports": {
        "IE": {
          "direction": "input",
          "bits": [ 2 ]
        },
        "IQC": {
          "direction": "input",
          "bits": [ 3 ]
        },
        "OQI": {
          "direction": "input",
          "bits": [ 4 ]
        },
        "OQE": {
          "direction": "input",
          "bits": [ 5 ]
        },
        "IQE": {
          "direction": "input",
          "bits": [ 6 ]
        },
        "IQR": {
          "direction": "input",
          "bits": [ 7 ]
        },
        "INEN": {
          "direction": "input",
          "bits": [ 8 ]
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stderr   =======================================================================
Warning: Wire BIDIR.\IQZ is used but has no driver.
exitcode =======================================================================
0
================================================================================

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make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/sdiomux /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/CMakeFiles/file_quicklogic_primitives_sdiomux_sdiomux_cell.sim.v.dir/DependInfo.cmake --color=
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cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux && /usr/bin/cmake -E create_symlink /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v
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make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/sdiomux /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/CMakeFiles/file_quicklogic_primitives_sdiomux_sdiomux_cell.model.xml.dir/DependInfo.cmake --color=
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[  0%] Generating sdiomux_cell.model.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=model -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.model.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v; prep -flatten; write_json -aig']
stdout   =======================================================================
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            "B_WIDTH": "00000000000000000000000000000001",
            "Y_WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
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          },
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            "A": "input",
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            "Y": "output"
          },
          "connections": {
            "A": [ 7 ],
            "B": [ "0" ],
            "Y": [ 9 ]
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:21$2": {
          "hide_name": 1,
          "type": "$mux",
          "model": "$mux:1",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:21.20-21.54"
          },
          "port_directions": {
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          },
          "connections": {
            "A": [ "0" ],
            "B": [ 2 ],
            "S": [ 8 ],
            "Y": [ 3 ]
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:22$4": {
          "hide_name": 1,
          "type": "$mux",
          "model": "$mux:1",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:22.25-22.54"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
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            "A": [ "0" ],
            "B": [ 6 ],
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        }
      },
      "netnames": {
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:21$1_Y": {
          "hide_name": 1,
          "bits": [ 8 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:21.21-21.33"
          }
        },
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:22$3_Y": {
          "hide_name": 1,
          "bits": [ 9 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:22.26-22.38"
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:21$2_Y": {
          "hide_name": 1,
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          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:22$4_Y": {
          "hide_name": 1,
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          "bits": [ 3 ],
          "attributes": {
            "DELAY_CONST_I_EN": "1e-10",
            "DELAY_CONST_I_PAD_$inp": "{iopath_IP_IZ}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:14.17-14.22"
          }
        },
        "I_EN": {
          "hide_name": 0,
          "bits": [ 4 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:7.17-7.21"
          }
        },
        "I_PAD_$inp": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
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          }
        },
        "O_DAT": {
          "hide_name": 0,
          "bits": [ 6 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:9.17-9.22"
          }
        },
        "O_EN": {
          "hide_name": 0,
          "bits": [ 7 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:10.17-10.21"
          }
        },
        "O_PAD_$out": {
          "hide_name": 0,
          "bits": [ 5 ],
          "attributes": {
            "DELAY_CONST_O_DAT": "{iopath_OQI_IP}",
            "DELAY_CONST_O_EN": "{iopath_OE_IP}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:18.17-18.27"
          }
        }
      }
    }
  },
  "models": {
    "$mux:1": [
      /*   0 */ [ "port", "S", 0 ],
      /*   1 */ [ "port", "A", 0 ],
      /*   2 */ [ "port", "B", 0 ],
      /*   3 */ [ "nport", "S", 0 ],
      /*   4 */ [ "nand", 0, 2 ],
      /*   5 */ [ "nand", 1, 3 ],
      /*   6 */ [ "nand", 4, 5, "Y", 0 ]
    ],
    "$eq:1U:1U:1": [
      /*   0 */ [ "port", "A", 0 ],
      /*   1 */ [ "port", "B", 0 ],
      /*   2 */ [ "nport", "B", 0 ],
      /*   3 */ [ "nport", "A", 0 ],
      /*   4 */ [ "nand", 2, 3 ],
      /*   5 */ [ "nand", 0, 1 ],
      /*   6 */ [ "nand", 4, 5, "Y", 0 ]
    ]
  }
}
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v; proc; cd SDIOMUX_CELL; select -write /tmp/tmphmm0c_31 c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v; proc; cd SDIOMUX_CELL; select -write /tmp/tmpov_x2n78 I_DAT %co* o:* %i I_DAT %d']
stderr   =======================================================================
Warning: Selection "I_DAT" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v; proc; cd SDIOMUX_CELL; select -write /tmp/tmpoj1rdtf2 I_EN %co* o:* %i I_EN %d']
stderr   =======================================================================
Warning: Selection "I_EN" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v; proc; cd SDIOMUX_CELL; select -write /tmp/tmpf92sg2vi I_PAD_$inp %co* o:* %i I_PAD_$inp %d']
stderr   =======================================================================
Warning: Selection "I_PAD_$inp" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v; proc; cd SDIOMUX_CELL; select -write /tmp/tmpu0gb5r59 O_DAT %co* o:* %i O_DAT %d']
stderr   =======================================================================
Warning: Selection "O_DAT" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v; proc; cd SDIOMUX_CELL; select -write /tmp/tmp_gx1mapy O_EN %co* o:* %i O_EN %d']
stderr   =======================================================================
Warning: Selection "O_EN" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v; proc; cd SDIOMUX_CELL; select -write /tmp/tmpap6qnigy O_PAD_$out %co* o:* %i O_PAD_$out %d']
stderr   =======================================================================
Warning: Selection "O_PAD_$out" did not match any object.
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_sdiomux_sdiomux_cell.model.xml
make -f quicklogic/primitives/sdiomux/CMakeFiles/file_quicklogic_primitives_sdiomux_sdiomux_cell.pb_type.xml.dir/build.make quicklogic/primitives/sdiomux/CMakeFiles/file_quicklogic_primitives_sdiomux_sdiomux_cell.pb_type.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/sdiomux /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/CMakeFiles/file_quicklogic_primitives_sdiomux_sdiomux_cell.pb_type.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/sdiomux/CMakeFiles/file_quicklogic_primitives_sdiomux_sdiomux_cell.pb_type.xml.dir/build.make quicklogic/primitives/sdiomux/CMakeFiles/file_quicklogic_primitives_sdiomux_sdiomux_cell.pb_type.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating sdiomux_cell.pb_type.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=pb_type -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.pb_type.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v; prep ; write_json ']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "SDIOMUX_CELL": {
      "attributes": {
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        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:2.1-24.10"
      },
      "ports": {
        "I_PAD_$inp": {
          "direction": "input",
          "bits": [ 2 ]
        },
        "I_DAT": {
          "direction": "output",
          "bits": [ 3 ]
        },
        "I_EN": {
          "direction": "input",
          "bits": [ 4 ]
        },
        "O_PAD_$out": {
          "direction": "output",
          "bits": [ 5 ]
        },
        "O_DAT": {
          "direction": "input",
          "bits": [ 6 ]
        },
        "O_EN": {
          "direction": "input",
          "bits": [ 7 ]
        }
      },
      "cells": {
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:21$1": {
          "hide_name": 1,
          "type": "$eq",
          "parameters": {
            "A_SIGNED": "00000000000000000000000000000000",
            "A_WIDTH": "00000000000000000000000000000001",
            "B_SIGNED": "00000000000000000000000000000000",
            "B_WIDTH": "00000000000000000000000000000001",
            "Y_WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:21.21-21.33"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 4 ],
            "B": [ "0" ],
            "Y": [ 8 ]
          }
        },
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:22$3": {
          "hide_name": 1,
          "type": "$eq",
          "parameters": {
            "A_SIGNED": "00000000000000000000000000000000",
            "A_WIDTH": "00000000000000000000000000000001",
            "B_SIGNED": "00000000000000000000000000000000",
            "B_WIDTH": "00000000000000000000000000000001",
            "Y_WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:22.26-22.38"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 7 ],
            "B": [ "0" ],
            "Y": [ 9 ]
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:21$2": {
          "hide_name": 1,
          "type": "$mux",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:21.20-21.54"
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            "S": [ 8 ],
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          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:22$4": {
          "hide_name": 1,
          "type": "$mux",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:22.25-22.54"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
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            "A": [ "0" ],
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      "netnames": {
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:21$1_Y": {
          "hide_name": 1,
          "bits": [ 8 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:21.21-21.33"
          }
        },
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:22$3_Y": {
          "hide_name": 1,
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          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:22.26-22.38"
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:21$2_Y": {
          "hide_name": 1,
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          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:22$4_Y": {
          "hide_name": 1,
          "bits": [ 5 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:22.25-22.54"
          }
        },
        "I_DAT": {
          "hide_name": 0,
          "bits": [ 3 ],
          "attributes": {
            "DELAY_CONST_I_EN": "1e-10",
            "DELAY_CONST_I_PAD_$inp": "{iopath_IP_IZ}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:14.17-14.22"
          }
        },
        "I_EN": {
          "hide_name": 0,
          "bits": [ 4 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:7.17-7.21"
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        },
        "I_PAD_$inp": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:6.17-6.27"
          }
        },
        "O_DAT": {
          "hide_name": 0,
          "bits": [ 6 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:9.17-9.22"
          }
        },
        "O_EN": {
          "hide_name": 0,
          "bits": [ 7 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:10.17-10.21"
          }
        },
        "O_PAD_$out": {
          "hide_name": 0,
          "bits": [ 5 ],
          "attributes": {
            "DELAY_CONST_O_DAT": "{iopath_OQI_IP}",
            "DELAY_CONST_O_EN": "{iopath_OE_IP}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v:18.17-18.27"
          }
        }
      }
    }
  }
}
exitcode =======================================================================
0
================================================================================

is_blackbox True has_modes? False
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux_cell.sim.v; proc; cd SDIOMUX_CELL; select -write /tmp/tmpquxeoz_0 c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_sdiomux_sdiomux_cell.pb_type.xml
make -f quicklogic/primitives/sdiomux/CMakeFiles/file_quicklogic_primitives_sdiomux_sdiomux.sim.v.dir/build.make quicklogic/primitives/sdiomux/CMakeFiles/file_quicklogic_primitives_sdiomux_sdiomux.sim.v.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/sdiomux /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/CMakeFiles/file_quicklogic_primitives_sdiomux_sdiomux.sim.v.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/sdiomux/CMakeFiles/file_quicklogic_primitives_sdiomux_sdiomux.sim.v.dir/build.make quicklogic/primitives/sdiomux/CMakeFiles/file_quicklogic_primitives_sdiomux_sdiomux.sim.v.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating sdiomux.sim.v
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux && /usr/bin/cmake -E create_symlink /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/sdiomux/sdiomux.sim.v /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.sim.v
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_sdiomux_sdiomux.sim.v
make -f quicklogic/primitives/sdiomux/CMakeFiles/file_quicklogic_primitives_sdiomux_sdiomux.pb_type.xml.dir/build.make quicklogic/primitives/sdiomux/CMakeFiles/file_quicklogic_primitives_sdiomux_sdiomux.pb_type.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/sdiomux /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/CMakeFiles/file_quicklogic_primitives_sdiomux_sdiomux.pb_type.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/sdiomux/CMakeFiles/file_quicklogic_primitives_sdiomux_sdiomux.pb_type.xml.dir/build.make quicklogic/primitives/sdiomux/CMakeFiles/file_quicklogic_primitives_sdiomux_sdiomux.pb_type.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating sdiomux.pb_type.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=pb_type -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.pb_type.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.sim.v; prep ; write_json ']
stdout   =======================================================================
{
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      },
      "parameter_default_values": {
        "MODE": "INPUT"
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      "ports": {
        "OQI": {
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        },
        "IZ": {
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      },
      "cells": {
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          "parameters": {
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          "attributes": {
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          "port_directions": {
            "inpad": "output"
          },
          "connections": {
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        },
        "sdiomux": {
          "hide_name": 0,
          "type": "SDIOMUX_CELL",
          "parameters": {
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          "attributes": {
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            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.sim.v:54.22-61.10"
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          "port_directions": {
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        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:22$3": {
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          "connections": {
            "A": [ 7 ],
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        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:21$2": {
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}
exitcode =======================================================================
0
================================================================================

is_blackbox False has_modes? True
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.sim.v; proc; cd SDIOMUX; select -write /tmp/tmp_i8avgsg c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.sim.v; chparam -set MODE "INPUT" SDIOMUX; prep ; write_json ']
stdout   =======================================================================
{
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      "cells": {
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:21$1": {
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        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:22$3": {
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        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:21$2": {
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        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:22$4": {
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        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:22$3_Y": {
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        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:22$4_Y": {
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          "attributes": {
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            "DELAY_CONST_I_PAD_$inp": "{iopath_IP_IZ}",
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        },
        "I_EN": {
          "hide_name": 0,
          "bits": [ 4 ],
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        "I_PAD_$inp": {
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          "bits": [ 2 ],
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        },
        "O_DAT": {
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          "bits": [ 6 ],
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          "attributes": {
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          }
        },
        "O_PAD_$out": {
          "hide_name": 0,
          "bits": [ 5 ],
          "attributes": {
            "DELAY_CONST_O_DAT": "{iopath_OQI_IP}",
            "DELAY_CONST_O_EN": "{iopath_OE_IP}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:18.17-18.27"
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      }
    },
    "VPR_IPAD": {
      "attributes": {
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        "CLASS": "input",
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      },
      "ports": {
        "inpad": {
          "direction": "output",
          "bits": [ 2 ]
        }
      },
      "cells": {
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      "netnames": {
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          }
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      }
    },
    "VPR_OPAD": {
      "attributes": {
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        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/../vpr_pad/vpr_opad.sim.v:2.1-5.10"
      },
      "ports": {
        "outpad": {
          "direction": "input",
          "bits": [ 2 ]
        }
      },
      "cells": {
      },
      "netnames": {
        "outpad": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/../vpr_pad/vpr_opad.sim.v:3.17-3.23"
          }
        }
      }
    }
  }
}
exitcode =======================================================================
0
================================================================================

is_blackbox False has_modes? True
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.sim.v; proc; cd SDIOMUX; select -write /tmp/tmp1vb0brfb c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

[[(('sdiomux', 'I_EN'), {})],
 [(('sdiomux', 'I_PAD_$inp'), {'pack': 'IPAD_TO_SDIOMUX'})],
 [(('sdiomux', 'O_DAT'), {})],
 [(('sdiomux', 'O_EN'), {})],
 [((None, 'IZ'),
   {'DELAY_CONST_I_EN': '1e-10', 'DELAY_CONST_I_PAD_$inp': '{iopath_IP_IZ}'})]]
SDIOMUX
--
defaultdict(<class 'list'>,
            {(None, 'IE'): [(('sdiomux', 'I_EN'), {})],
             (None, 'OE'): [(('sdiomux', 'O_EN'), {})],
             (None, 'OQI'): [(('sdiomux', 'O_DAT'), {})],
             ('inpad', 'inpad'): [(('sdiomux', 'I_PAD_$inp'),
                                   {'pack': 'IPAD_TO_SDIOMUX'})],
             ('sdiomux', 'I_DAT'): [((None, 'IZ'),
                                     {'DELAY_CONST_I_EN': '1e-10',
                                      'DELAY_CONST_I_PAD_$inp': '{iopath_IP_IZ}'})]})
--
[]
{}
--
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.sim.v; chparam -set MODE "OUTPUT" SDIOMUX; prep ; write_json ']
stdout   =======================================================================
{
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        "hdlname": "\\SDIOMUX",
        "MODES": "INPUT;OUTPUT;INOUT"
      },
      "parameter_default_values": {
        "MODE": "OUTPUT"
      },
      "ports": {
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          "bits": [ 2 ]
        },
        "IE": {
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        },
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        },
        "IZ": {
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        }
      },
      "cells": {
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          "parameters": {
          },
          "attributes": {
            "keep": "00000000000000000000000000000001",
            "module_not_derived": "00000000000000000000000000000001",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.sim.v:31.18-31.31"
          },
          "port_directions": {
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          },
          "connections": {
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          }
        },
        "sdiomux": {
          "hide_name": 0,
          "type": "SDIOMUX_CELL",
          "parameters": {
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          "attributes": {
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            "O_DAT": "input",
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            "O_PAD_$out": "output"
          },
          "connections": {
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          "bits": [ 7 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:10.17-10.21"
          }
        },
        "O_PAD_$out": {
          "hide_name": 0,
          "bits": [ 5 ],
          "attributes": {
            "DELAY_CONST_O_DAT": "{iopath_OQI_IP}",
            "DELAY_CONST_O_EN": "{iopath_OE_IP}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:18.17-18.27"
          }
        }
      }
    },
    "VPR_IPAD": {
      "attributes": {
        "blackbox": "00000000000000000000000000000001",
        "CLASS": "input",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/../vpr_pad/vpr_ipad.sim.v:2.1-5.10"
      },
      "ports": {
        "inpad": {
          "direction": "output",
          "bits": [ 2 ]
        }
      },
      "cells": {
      },
      "netnames": {
        "inpad": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/../vpr_pad/vpr_ipad.sim.v:3.17-3.22"
          }
        }
      }
    },
    "VPR_OPAD": {
      "attributes": {
        "blackbox": "00000000000000000000000000000001",
        "CLASS": "output",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/../vpr_pad/vpr_opad.sim.v:2.1-5.10"
      },
      "ports": {
        "outpad": {
          "direction": "input",
          "bits": [ 2 ]
        }
      },
      "cells": {
      },
      "netnames": {
        "outpad": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/../vpr_pad/vpr_opad.sim.v:3.17-3.23"
          }
        }
      }
    }
  }
}
exitcode =======================================================================
0
================================================================================

is_blackbox False has_modes? True
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.sim.v; proc; cd SDIOMUX; select -write /tmp/tmpbenq4pdp c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

[[(('outpad', 'outpad'), {'pack': 'SDIOMUX_TO_OPAD'})],
 [(('sdiomux', 'I_EN'), {})],
 [(('sdiomux', 'O_DAT'), {})],
 [(('sdiomux', 'O_EN'), {})],
 [((None, 'IZ'),
   {'DELAY_CONST_I_EN': '1e-10', 'DELAY_CONST_I_PAD_$inp': '{iopath_IP_IZ}'})]]
SDIOMUX
--
defaultdict(<class 'list'>,
            {('sdiomux', 'I_DAT'): [((None, 'IZ'),
                                     {'DELAY_CONST_I_EN': '1e-10',
                                      'DELAY_CONST_I_PAD_$inp': '{iopath_IP_IZ}'})],
             (None, 'IE'): [(('sdiomux', 'I_EN'), {})],
             (None, 'OE'): [(('sdiomux', 'O_EN'), {})],
             (None, 'OQI'): [(('sdiomux', 'O_DAT'), {})],
             ('sdiomux', 'O_PAD_$out'): [(('outpad', 'outpad'),
                                          {'pack': 'SDIOMUX_TO_OPAD'})]})
--
[]
{}
--
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.sim.v; chparam -set MODE "INOUT" SDIOMUX; prep ; write_json ']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "SDIOMUX": {
      "attributes": {
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.sim.v:6.1-89.10",
        "hdlname": "\\SDIOMUX",
        "MODES": "INPUT;OUTPUT;INOUT"
      },
      "parameter_default_values": {
        "MODE": "INOUT"
      },
      "ports": {
        "OQI": {
          "direction": "input",
          "bits": [ 2 ]
        },
        "IE": {
          "direction": "input",
          "bits": [ 3 ]
        },
        "OE": {
          "direction": "input",
          "bits": [ 4 ]
        },
        "IZ": {
          "direction": "output",
          "bits": [ 5 ]
        }
      },
      "cells": {
        "inpad": {
          "hide_name": 0,
          "type": "VPR_IPAD",
          "parameters": {
          },
          "attributes": {
            "keep": "00000000000000000000000000000001",
            "module_not_derived": "00000000000000000000000000000001",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.sim.v:43.18-43.30"
          },
          "port_directions": {
            "inpad": "output"
          },
          "connections": {
            "inpad": [ 6 ]
          }
        },
        "outpad": {
          "hide_name": 0,
          "type": "VPR_OPAD",
          "parameters": {
          },
          "attributes": {
            "keep": "00000000000000000000000000000001",
            "module_not_derived": "00000000000000000000000000000001",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.sim.v:46.18-46.31"
          },
          "port_directions": {
            "outpad": "input"
          },
          "connections": {
            "outpad": [ 7 ]
          }
        },
        "sdiomux": {
          "hide_name": 0,
          "type": "SDIOMUX_CELL",
          "parameters": {
          },
          "attributes": {
            "keep": "00000000000000000000000000000001",
            "module_not_derived": "00000000000000000000000000000001",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.sim.v:78.22-85.10"
          },
          "port_directions": {
            "I_DAT": "output",
            "I_EN": "input",
            "I_PAD_$inp": "input",
            "O_DAT": "input",
            "O_EN": "input",
            "O_PAD_$out": "output"
          },
          "connections": {
            "I_DAT": [ 5 ],
            "I_EN": [ 3 ],
            "I_PAD_$inp": [ 6 ],
            "O_DAT": [ 2 ],
            "O_EN": [ 4 ],
            "O_PAD_$out": [ 7 ]
          }
        }
      },
      "netnames": {
        "IE": {
          "hide_name": 0,
          "bits": [ 3 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.sim.v:8.17-8.19"
          }
        },
        "IZ": {
          "hide_name": 0,
          "bits": [ 5 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.sim.v:10.17-10.19"
          }
        },
        "OE": {
          "hide_name": 0,
          "bits": [ 4 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.sim.v:9.17-9.19"
          }
        },
        "OQI": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.sim.v:7.17-7.20"
          }
        },
        "i_pad": {
          "hide_name": 0,
          "bits": [ 6 ],
          "attributes": {
            "pack": "IOPAD_TO_SDIOMUX",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.sim.v:37.14-37.19"
          }
        },
        "o_pad": {
          "hide_name": 0,
          "bits": [ 7 ],
          "attributes": {
            "pack": "IOPAD_TO_SDIOMUX",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.sim.v:40.14-40.19"
          }
        }
      }
    },
    "SDIOMUX_CELL": {
      "attributes": {
        "whitebox": "00000000000000000000000000000001",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:2.1-24.10"
      },
      "ports": {
        "I_PAD_$inp": {
          "direction": "input",
          "bits": [ 2 ]
        },
        "I_DAT": {
          "direction": "output",
          "bits": [ 3 ]
        },
        "I_EN": {
          "direction": "input",
          "bits": [ 4 ]
        },
        "O_PAD_$out": {
          "direction": "output",
          "bits": [ 5 ]
        },
        "O_DAT": {
          "direction": "input",
          "bits": [ 6 ]
        },
        "O_EN": {
          "direction": "input",
          "bits": [ 7 ]
        }
      },
      "cells": {
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:21$1": {
          "hide_name": 1,
          "type": "$eq",
          "parameters": {
            "A_SIGNED": "00000000000000000000000000000000",
            "A_WIDTH": "00000000000000000000000000000001",
            "B_SIGNED": "00000000000000000000000000000000",
            "B_WIDTH": "00000000000000000000000000000001",
            "Y_WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:21.21-21.33"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 4 ],
            "B": [ "0" ],
            "Y": [ 8 ]
          }
        },
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:22$3": {
          "hide_name": 1,
          "type": "$eq",
          "parameters": {
            "A_SIGNED": "00000000000000000000000000000000",
            "A_WIDTH": "00000000000000000000000000000001",
            "B_SIGNED": "00000000000000000000000000000000",
            "B_WIDTH": "00000000000000000000000000000001",
            "Y_WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:22.26-22.38"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 7 ],
            "B": [ "0" ],
            "Y": [ 9 ]
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:21$2": {
          "hide_name": 1,
          "type": "$mux",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:21.20-21.54"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ "0" ],
            "B": [ 2 ],
            "S": [ 8 ],
            "Y": [ 3 ]
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:22$4": {
          "hide_name": 1,
          "type": "$mux",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:22.25-22.54"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ "0" ],
            "B": [ 6 ],
            "S": [ 9 ],
            "Y": [ 5 ]
          }
        }
      },
      "netnames": {
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:21$1_Y": {
          "hide_name": 1,
          "bits": [ 8 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:21.21-21.33"
          }
        },
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:22$3_Y": {
          "hide_name": 1,
          "bits": [ 9 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:22.26-22.38"
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:21$2_Y": {
          "hide_name": 1,
          "bits": [ 3 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:21.20-21.54"
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:22$4_Y": {
          "hide_name": 1,
          "bits": [ 5 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:22.25-22.54"
          }
        },
        "I_DAT": {
          "hide_name": 0,
          "bits": [ 3 ],
          "attributes": {
            "DELAY_CONST_I_EN": "1e-10",
            "DELAY_CONST_I_PAD_$inp": "{iopath_IP_IZ}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:14.17-14.22"
          }
        },
        "I_EN": {
          "hide_name": 0,
          "bits": [ 4 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:7.17-7.21"
          }
        },
        "I_PAD_$inp": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:6.17-6.27"
          }
        },
        "O_DAT": {
          "hide_name": 0,
          "bits": [ 6 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:9.17-9.22"
          }
        },
        "O_EN": {
          "hide_name": 0,
          "bits": [ 7 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:10.17-10.21"
          }
        },
        "O_PAD_$out": {
          "hide_name": 0,
          "bits": [ 5 ],
          "attributes": {
            "DELAY_CONST_O_DAT": "{iopath_OQI_IP}",
            "DELAY_CONST_O_EN": "{iopath_OE_IP}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/./sdiomux_cell.sim.v:18.17-18.27"
          }
        }
      }
    },
    "VPR_IPAD": {
      "attributes": {
        "blackbox": "00000000000000000000000000000001",
        "CLASS": "input",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/../vpr_pad/vpr_ipad.sim.v:2.1-5.10"
      },
      "ports": {
        "inpad": {
          "direction": "output",
          "bits": [ 2 ]
        }
      },
      "cells": {
      },
      "netnames": {
        "inpad": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/../vpr_pad/vpr_ipad.sim.v:3.17-3.22"
          }
        }
      }
    },
    "VPR_OPAD": {
      "attributes": {
        "blackbox": "00000000000000000000000000000001",
        "CLASS": "output",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/../vpr_pad/vpr_opad.sim.v:2.1-5.10"
      },
      "ports": {
        "outpad": {
          "direction": "input",
          "bits": [ 2 ]
        }
      },
      "cells": {
      },
      "netnames": {
        "outpad": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/../vpr_pad/vpr_opad.sim.v:3.17-3.23"
          }
        }
      }
    }
  }
}
exitcode =======================================================================
0
================================================================================

is_blackbox False has_modes? True
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.sim.v; proc; cd SDIOMUX; select -write /tmp/tmplf6p4fi7 c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

[[(('outpad', 'outpad'), {'pack': 'IOPAD_TO_SDIOMUX'})],
 [(('sdiomux', 'I_EN'), {})],
 [(('sdiomux', 'I_PAD_$inp'), {'pack': 'IOPAD_TO_SDIOMUX'})],
 [(('sdiomux', 'O_DAT'), {})],
 [(('sdiomux', 'O_EN'), {})],
 [((None, 'IZ'),
   {'DELAY_CONST_I_EN': '1e-10', 'DELAY_CONST_I_PAD_$inp': '{iopath_IP_IZ}'})]]
SDIOMUX
--
defaultdict(<class 'list'>,
            {('inpad', 'inpad'): [(('sdiomux', 'I_PAD_$inp'),
                                   {'pack': 'IOPAD_TO_SDIOMUX'})],
             ('sdiomux', 'O_PAD_$out'): [(('outpad', 'outpad'),
                                          {'pack': 'IOPAD_TO_SDIOMUX'})],
             (None, 'IE'): [(('sdiomux', 'I_EN'), {})],
             (None, 'OE'): [(('sdiomux', 'O_EN'), {})],
             (None, 'OQI'): [(('sdiomux', 'O_DAT'), {})],
             ('sdiomux', 'I_DAT'): [((None, 'IZ'),
                                     {'DELAY_CONST_I_EN': '1e-10',
                                      'DELAY_CONST_I_PAD_$inp': '{iopath_IP_IZ}'})]})
--
[]
{}
--
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_sdiomux_sdiomux.pb_type.xml
make -f quicklogic/primitives/sdiomux/CMakeFiles/file_quicklogic_primitives_sdiomux_sdiomux.model.xml.dir/build.make quicklogic/primitives/sdiomux/CMakeFiles/file_quicklogic_primitives_sdiomux_sdiomux.model.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/sdiomux /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/CMakeFiles/file_quicklogic_primitives_sdiomux_sdiomux.model.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/sdiomux/CMakeFiles/file_quicklogic_primitives_sdiomux_sdiomux.model.xml.dir/build.make quicklogic/primitives/sdiomux/CMakeFiles/file_quicklogic_primitives_sdiomux_sdiomux.model.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating sdiomux.model.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=model -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.model.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/sdiomux/sdiomux.sim.v; prep -flatten; write_json -aig']
stdout   =======================================================================
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exitcode =======================================================================
0
================================================================================

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make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_t_frag.sim.v.dir/DependInfo.cmake --color=
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cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic && /usr/bin/cmake -E create_symlink /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/logic/t_frag.sim.v /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v
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cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_t_frag.pb_type.xml.dir/DependInfo.cmake --color=
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make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating t_frag.pb_type.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=pb_type -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.pb_type.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v; prep ; write_json ']
stdout   =======================================================================
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}
exitcode =======================================================================
0
================================================================================

is_blackbox True has_modes? False
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v; proc; cd T_FRAG; select -write /tmp/tmp9ixt2j2v c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_logic_t_frag.pb_type.xml
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_b_frag.sim.v.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_b_frag.sim.v.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_b_frag.sim.v.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_b_frag.sim.v.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_b_frag.sim.v.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating b_frag.sim.v
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic && /usr/bin/cmake -E create_symlink /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/logic/b_frag.sim.v /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_logic_b_frag.sim.v
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_b_frag.pb_type.xml.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_b_frag.pb_type.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_b_frag.pb_type.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_b_frag.pb_type.xml.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_b_frag.pb_type.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating b_frag.pb_type.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=pb_type -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.pb_type.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v; prep ; write_json ']
stdout   =======================================================================
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            "DELAY_CONST_TBS": "{iopath_TBS_CZ}",
            "DELAY_CONST_XA1": "{iopath_BA1_CZ}",
            "DELAY_CONST_XA2": "{iopath_BA2_CZ}",
            "DELAY_CONST_XAB": "{iopath_BAB_CZ}",
            "DELAY_CONST_XB1": "{iopath_BB1_CZ}",
            "DELAY_CONST_XB2": "{iopath_BB2_CZ}",
            "DELAY_CONST_XSL": "{iopath_BSL_CZ}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:27.17-27.19"
          }
        },
        "XZI": {
          "hide_name": 0,
          "bits": [ 12 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:46.10-46.13"
          }
        }
      }
    }
  }
}
exitcode =======================================================================
0
================================================================================

is_blackbox True has_modes? False
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v; proc; cd B_FRAG; select -write /tmp/tmp6942keyo c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_logic_b_frag.pb_type.xml
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_q_frag.sim.v.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_q_frag.sim.v.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_q_frag.sim.v.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_q_frag.sim.v.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_q_frag.sim.v.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating q_frag.sim.v
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic && /usr/bin/cmake -E create_symlink /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/logic/q_frag.sim.v /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_logic_q_frag.sim.v
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_q_frag.model.xml.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_q_frag.model.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_q_frag.model.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_q_frag.model.xml.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_q_frag.model.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating q_frag.model.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=model -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.model.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v; prep -flatten; write_json -aig']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "Q_FRAG": {
      "attributes": {
        "whitebox": "00000000000000000000000000000001",
        "FASM_PARAMS": "ZINV.QCK=Z_QCKS",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:3.1-53.10"
      },
      "parameter_default_values": {
        "Z_QCKS": "1"
      },
      "ports": {
        "QCK": {
          "direction": "input",
          "bits": [ 2 ]
        },
        "QST": {
          "direction": "input",
          "bits": [ 3 ]
        },
        "QRT": {
          "direction": "input",
          "bits": [ 4 ]
        },
        "QEN": {
          "direction": "input",
          "bits": [ 5 ]
        },
        "QDI": {
          "direction": "input",
          "bits": [ 6 ]
        },
        "QDS": {
          "direction": "input",
          "bits": [ 7 ]
        },
        "CZI": {
          "direction": "input",
          "bits": [ 8 ]
        },
        "QZ": {
          "direction": "output",
          "bits": [ 9 ]
        }
      },
      "cells": {
        "$auto$proc_dff.cc:105:gen_dffsr_complex$12": {
          "hide_name": 1,
          "type": "$not",
          "model": "$not:1U:1",
          "parameters": {
            "A_SIGNED": "00000000000000000000000000000000",
            "A_WIDTH": "00000000000000000000000000000001",
            "Y_WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
          },
          "port_directions": {
            "A": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ "0" ],
            "Y": [ 10 ]
          }
        },
        "$auto$proc_dff.cc:105:gen_dffsr_complex$6": {
          "hide_name": 1,
          "type": "$not",
          "model": "$not:1U:1",
          "parameters": {
            "A_SIGNED": "00000000000000000000000000000000",
            "A_WIDTH": "00000000000000000000000000000001",
            "Y_WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
          },
          "port_directions": {
            "A": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ "1" ],
            "Y": [ 11 ]
          }
        },
        "$auto$proc_dff.cc:112:gen_dffsr_complex$14": {
          "hide_name": 1,
          "type": "$mux",
          "model": "$mux:1",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 12 ],
            "B": [ "0" ],
            "S": [ 4 ],
            "Y": [ 13 ]
          }
        },
        "$auto$proc_dff.cc:112:gen_dffsr_complex$8": {
          "hide_name": 1,
          "type": "$mux",
          "model": "$mux:1",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ "0" ],
            "B": [ "1" ],
            "S": [ 3 ],
            "Y": [ 12 ]
          }
        },
        "$auto$proc_dff.cc:119:gen_dffsr_complex$10": {
          "hide_name": 1,
          "type": "$mux",
          "model": "$mux:1",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ "0" ],
            "B": [ 11 ],
            "S": [ 3 ],
            "Y": [ 14 ]
          }
        },
        "$auto$proc_dff.cc:119:gen_dffsr_complex$16": {
          "hide_name": 1,
          "type": "$mux",
          "model": "$mux:1",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 14 ],
            "B": [ 10 ],
            "S": [ 4 ],
            "Y": [ 15 ]
          }
        },
        "$procdff$18": {
          "hide_name": 1,
          "type": "$dffsr",
          "parameters": {
            "CLK_POLARITY": "1",
            "CLR_POLARITY": "1",
            "SET_POLARITY": "1",
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:44.2-51.5"
          },
          "port_directions": {
            "CLK": "input",
            "CLR": "input",
            "D": "input",
            "Q": "output",
            "SET": "input"
          },
          "connections": {
            "CLK": [ 2 ],
            "CLR": [ 15 ],
            "D": [ 16 ],
            "Q": [ 9 ],
            "SET": [ 13 ]
          }
        },
        "$procmux$4": {
          "hide_name": 1,
          "type": "$mux",
          "model": "$mux:1",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:49.12-49.15|/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:49.8-50.12"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 9 ],
            "B": [ 17 ],
            "S": [ 5 ],
            "Y": [ 16 ]
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:40$1": {
          "hide_name": 1,
          "type": "$mux",
          "model": "$mux:1",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:40.14-40.31"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 8 ],
            "B": [ 6 ],
            "S": [ 7 ],
            "Y": [ 17 ]
          }
        }
      },
      "netnames": {
        "$0\\QZ[0:0]": {
          "hide_name": 1,
          "bits": [ 16 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:44.2-51.5"
          }
        },
        "$1\\QZ[0:0]": {
          "hide_name": 1,
          "bits": [ "0" ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:0.0-0.0"
          }
        },
        "$auto$proc_dff.cc:110:gen_dffsr_complex$13": {
          "hide_name": 1,
          "bits": [ 10 ],
          "attributes": {
          }
        },
        "$auto$proc_dff.cc:110:gen_dffsr_complex$7": {
          "hide_name": 1,
          "bits": [ 11 ],
          "attributes": {
          }
        },
        "$auto$proc_dff.cc:117:gen_dffsr_complex$15": {
          "hide_name": 1,
          "bits": [ 13 ],
          "attributes": {
          }
        },
        "$auto$proc_dff.cc:117:gen_dffsr_complex$9": {
          "hide_name": 1,
          "bits": [ 12 ],
          "attributes": {
          }
        },
        "$auto$proc_dff.cc:124:gen_dffsr_complex$11": {
          "hide_name": 1,
          "bits": [ 14 ],
          "attributes": {
          }
        },
        "$auto$proc_dff.cc:124:gen_dffsr_complex$17": {
          "hide_name": 1,
          "bits": [ 15 ],
          "attributes": {
          }
        },
        "$procmux$4_Y": {
          "hide_name": 1,
          "bits": [ 16 ],
          "attributes": {
          }
        },
        "$procmux$5_CMP": {
          "hide_name": 1,
          "bits": [ 5 ],
          "attributes": {
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:40$1_Y": {
          "hide_name": 1,
          "bits": [ 17 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:40.14-40.31"
          }
        },
        "CZI": {
          "hide_name": 0,
          "bits": [ 8 ],
          "attributes": {
            "HOLD": "QCK {hold_QCK_QDI}",
            "NO_COMB": "00000000000000000000000000000001",
            "SETUP": "QCK {setup_QCK_QDI}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:31.17-31.20"
          }
        },
        "QCK": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "CLOCK": "00000000000000000000000000000001",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:5.17-5.20"
          }
        },
        "QDI": {
          "hide_name": 0,
          "bits": [ 6 ],
          "attributes": {
            "HOLD": "QCK {hold_QCK_QDI}",
            "NO_COMB": "00000000000000000000000000000001",
            "SETUP": "QCK {setup_QCK_QDI}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:21.17-21.20"
          }
        },
        "QDS": {
          "hide_name": 0,
          "bits": [ 7 ],
          "attributes": {
            "HOLD": "QCK {hold_QCK_QDS}",
            "NO_COMB": "00000000000000000000000000000001",
            "SETUP": "QCK {setup_QCK_QDS}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:25.17-25.20"
          }
        },
        "QEN": {
          "hide_name": 0,
          "bits": [ 5 ],
          "attributes": {
            "NO_COMB": "00000000000000000000000000000001",
            "SETUP": "QCK 1e-10",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:17.17-17.20"
          }
        },
        "QRT": {
          "hide_name": 0,
          "bits": [ 4 ],
          "attributes": {
            "NO_COMB": "00000000000000000000000000000001",
            "SETUP": "QCK 1e-10",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:13.17-13.20"
          }
        },
        "QST": {
          "hide_name": 0,
          "bits": [ 3 ],
          "attributes": {
            "NO_COMB": "00000000000000000000000000000001",
            "SETUP": "QCK 1e-10",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:9.17-9.20"
          }
        },
        "QZ": {
          "hide_name": 0,
          "bits": [ 9 ],
          "attributes": {
            "CLK_TO_Q": "QCK {setuphold_QCK_QZ}",
            "init": "0",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:34.17-34.19"
          }
        },
        "d": {
          "hide_name": 0,
          "bits": [ 17 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:40.10-40.11"
          }
        }
      }
    }
  },
  "models": {
    "$mux:1": [
      /*   0 */ [ "port", "S", 0 ],
      /*   1 */ [ "port", "A", 0 ],
      /*   2 */ [ "port", "B", 0 ],
      /*   3 */ [ "nport", "S", 0 ],
      /*   4 */ [ "nand", 0, 2 ],
      /*   5 */ [ "nand", 1, 3 ],
      /*   6 */ [ "nand", 4, 5, "Y", 0 ]
    ],
    "$not:1U:1": [
      /*   0 */ [ "nport", "A", 0, "Y", 0 ]
    ]
  }
}
stderr   =======================================================================
Warning: Complex async reset for dff `\QZ'.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v; proc; cd Q_FRAG; select -write /tmp/tmp0uviwb80 c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
stderr   =======================================================================
Warning: Complex async reset for dff `\QZ'.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v; proc; cd Q_FRAG; select -write /tmp/tmp_fvgbbcn CZI %co* o:* %i CZI %d']
stderr   =======================================================================
Warning: Complex async reset for dff `\QZ'.
Warning: Selection "CZI" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v; proc; cd Q_FRAG; select -write /tmp/tmp7lcj9ecf QCK %co* o:* %i QCK %d']
stderr   =======================================================================
Warning: Complex async reset for dff `\QZ'.
Warning: Selection "QCK" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v; proc; cd Q_FRAG; select -write /tmp/tmpuhjjzyk3 QDI %co* o:* %i QDI %d']
stderr   =======================================================================
Warning: Complex async reset for dff `\QZ'.
Warning: Selection "QDI" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v; proc; cd Q_FRAG; select -write /tmp/tmpi6ulq_s8 QDS %co* o:* %i QDS %d']
stderr   =======================================================================
Warning: Complex async reset for dff `\QZ'.
Warning: Selection "QDS" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v; proc; cd Q_FRAG; select -write /tmp/tmpcnugbojk QEN %co* o:* %i QEN %d']
stderr   =======================================================================
Warning: Complex async reset for dff `\QZ'.
Warning: Selection "QEN" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v; proc; cd Q_FRAG; select -write /tmp/tmpt9sug6f6 QRT %co* o:* %i QRT %d']
stderr   =======================================================================
Warning: Complex async reset for dff `\QZ'.
Warning: Selection "QRT" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v; proc; cd Q_FRAG; select -write /tmp/tmp4y0pir3o QST %co* o:* %i QST %d']
stderr   =======================================================================
Warning: Complex async reset for dff `\QZ'.
Warning: Selection "QST" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v; proc; cd Q_FRAG; select -write /tmp/tmpucftcklc QZ %co* o:* %i QZ %d']
stderr   =======================================================================
Warning: Complex async reset for dff `\QZ'.
Warning: Selection "QZ" did not match any object.
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_logic_q_frag.model.xml
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_b_frag.model.xml.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_b_frag.model.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_b_frag.model.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_b_frag.model.xml.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_b_frag.model.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating b_frag.model.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=model -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.model.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v; prep -flatten; write_json -aig']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "B_FRAG": {
      "attributes": {
        "FASM_PARAMS": "INV.BA1=XAS1;INV.BA2=XAS2;INV.BB1=XBS1;INV.BB2=XBS2",
        "whitebox": "00000000000000000000000000000001",
        "MODEL_NAME": "T_FRAG",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:4.1-54.10"
      },
      "parameter_default_values": {
        "XAS1": "0",
        "XAS2": "0",
        "XBS1": "0",
        "XBS2": "0"
      },
      "ports": {
        "TBS": {
          "direction": "input",
          "bits": [ 2 ]
        },
        "XAB": {
          "direction": "input",
          "bits": [ 3 ]
        },
        "XSL": {
          "direction": "input",
          "bits": [ 4 ]
        },
        "XA1": {
          "direction": "input",
          "bits": [ 5 ]
        },
        "XA2": {
          "direction": "input",
          "bits": [ 6 ]
        },
        "XB1": {
          "direction": "input",
          "bits": [ 7 ]
        },
        "XB2": {
          "direction": "input",
          "bits": [ 8 ]
        },
        "XZ": {
          "direction": "output",
          "bits": [ 9 ]
        }
      },
      "cells": {
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:42$1": {
          "hide_name": 1,
          "type": "$mux",
          "model": "$mux:1",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:42.16-42.33"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
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          "connections": {
            "A": [ 5 ],
            "B": [ 6 ],
            "S": [ 4 ],
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          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:43$2": {
          "hide_name": 1,
          "type": "$mux",
          "model": "$mux:1",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:43.16-43.33"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 7 ],
            "B": [ 8 ],
            "S": [ 4 ],
            "Y": [ 11 ]
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:46$3": {
          "hide_name": 1,
          "type": "$mux",
          "model": "$mux:1",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:46.16-46.31"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 10 ],
            "B": [ 11 ],
            "S": [ 3 ],
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          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:52$4": {
          "hide_name": 1,
          "type": "$mux",
          "model": "$mux:1",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:52.17-52.33"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ "0" ],
            "B": [ 12 ],
            "S": [ 2 ],
            "Y": [ 9 ]
          }
        }
      },
      "netnames": {
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:42$1_Y": {
          "hide_name": 1,
          "bits": [ 10 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:42.16-42.33"
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:43$2_Y": {
          "hide_name": 1,
          "bits": [ 11 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:43.16-43.33"
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:46$3_Y": {
          "hide_name": 1,
          "bits": [ 12 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:46.16-46.31"
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:52$4_Y": {
          "hide_name": 1,
          "bits": [ 9 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:52.17-52.33"
          }
        },
        "TBS": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:7.17-7.20"
          }
        },
        "XA1": {
          "hide_name": 0,
          "bits": [ 5 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:11.17-11.20"
          }
        },
        "XA2": {
          "hide_name": 0,
          "bits": [ 6 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:12.17-12.20"
          }
        },
        "XAB": {
          "hide_name": 0,
          "bits": [ 3 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:9.17-9.20"
          }
        },
        "XAI": {
          "hide_name": 0,
          "bits": [ 10 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:42.10-42.13"
          }
        },
        "XAP1": {
          "hide_name": 0,
          "bits": [ 5 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:36.10-36.14"
          }
        },
        "XAP2": {
          "hide_name": 0,
          "bits": [ 6 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:37.10-37.14"
          }
        },
        "XB1": {
          "hide_name": 0,
          "bits": [ 7 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:13.17-13.20"
          }
        },
        "XB2": {
          "hide_name": 0,
          "bits": [ 8 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:14.17-14.20"
          }
        },
        "XBI": {
          "hide_name": 0,
          "bits": [ 11 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:43.10-43.13"
          }
        },
        "XBP1": {
          "hide_name": 0,
          "bits": [ 7 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:38.10-38.14"
          }
        },
        "XBP2": {
          "hide_name": 0,
          "bits": [ 8 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:39.10-39.14"
          }
        },
        "XSL": {
          "hide_name": 0,
          "bits": [ 4 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:10.17-10.20"
          }
        },
        "XZ": {
          "hide_name": 0,
          "bits": [ 9 ],
          "attributes": {
            "DELAY_CONST_TBS": "{iopath_TBS_CZ}",
            "DELAY_CONST_XA1": "{iopath_BA1_CZ}",
            "DELAY_CONST_XA2": "{iopath_BA2_CZ}",
            "DELAY_CONST_XAB": "{iopath_BAB_CZ}",
            "DELAY_CONST_XB1": "{iopath_BB1_CZ}",
            "DELAY_CONST_XB2": "{iopath_BB2_CZ}",
            "DELAY_CONST_XSL": "{iopath_BSL_CZ}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:27.17-27.19"
          }
        },
        "XZI": {
          "hide_name": 0,
          "bits": [ 12 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v:46.10-46.13"
          }
        }
      }
    }
  },
  "models": {
    "$mux:1": [
      /*   0 */ [ "port", "S", 0 ],
      /*   1 */ [ "port", "A", 0 ],
      /*   2 */ [ "port", "B", 0 ],
      /*   3 */ [ "nport", "S", 0 ],
      /*   4 */ [ "nand", 0, 2 ],
      /*   5 */ [ "nand", 1, 3 ],
      /*   6 */ [ "nand", 4, 5, "Y", 0 ]
    ]
  }
}
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v; proc; cd B_FRAG; select -write /tmp/tmpla8b8cjw c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v; proc; cd B_FRAG; select -write /tmp/tmpmmkw_bs3 TBS %co* o:* %i TBS %d']
stderr   =======================================================================
Warning: Selection "TBS" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v; proc; cd B_FRAG; select -write /tmp/tmp7wdl1pe8 XA1 %co* o:* %i XA1 %d']
stderr   =======================================================================
Warning: Selection "XA1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v; proc; cd B_FRAG; select -write /tmp/tmpsvy5_ax5 XA2 %co* o:* %i XA2 %d']
stderr   =======================================================================
Warning: Selection "XA2" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v; proc; cd B_FRAG; select -write /tmp/tmp8pr97al2 XAB %co* o:* %i XAB %d']
stderr   =======================================================================
Warning: Selection "XAB" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v; proc; cd B_FRAG; select -write /tmp/tmpr5l7r61p XB1 %co* o:* %i XB1 %d']
stderr   =======================================================================
Warning: Selection "XB1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v; proc; cd B_FRAG; select -write /tmp/tmp9xuoc525 XB2 %co* o:* %i XB2 %d']
stderr   =======================================================================
Warning: Selection "XB2" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v; proc; cd B_FRAG; select -write /tmp/tmp_x9u059y XSL %co* o:* %i XSL %d']
stderr   =======================================================================
Warning: Selection "XSL" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/b_frag.sim.v; proc; cd B_FRAG; select -write /tmp/tmpsjp5vs71 XZ %co* o:* %i XZ %d']
stderr   =======================================================================
Warning: Selection "XZ" did not match any object.
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_logic_b_frag.model.xml
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_f_frag.sim.v.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_f_frag.sim.v.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_f_frag.sim.v.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_f_frag.sim.v.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_f_frag.sim.v.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating f_frag.sim.v
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic && /usr/bin/cmake -E create_symlink /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/logic/f_frag.sim.v /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_logic_f_frag.sim.v
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_f_frag.pb_type.xml.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_f_frag.pb_type.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_f_frag.pb_type.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_f_frag.pb_type.xml.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_f_frag.pb_type.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating f_frag.pb_type.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=pb_type -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.pb_type.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v; prep ; write_json ']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "F_FRAG": {
      "attributes": {
        "whitebox": "00000000000000000000000000000001",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v:2.1-15.10"
      },
      "ports": {
        "F1": {
          "direction": "input",
          "bits": [ 2 ]
        },
        "F2": {
          "direction": "input",
          "bits": [ 3 ]
        },
        "FS": {
          "direction": "input",
          "bits": [ 4 ]
        },
        "FZ": {
          "direction": "output",
          "bits": [ 5 ]
        }
      },
      "cells": {
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v:13$1": {
          "hide_name": 1,
          "type": "$mux",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v:13.17-13.29"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 2 ],
            "B": [ 3 ],
            "S": [ 4 ],
            "Y": [ 5 ]
          }
        }
      },
      "netnames": {
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v:13$1_Y": {
          "hide_name": 1,
          "bits": [ 5 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v:13.17-13.29"
          }
        },
        "F1": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v:3.17-3.19"
          }
        },
        "F2": {
          "hide_name": 0,
          "bits": [ 3 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v:4.17-4.19"
          }
        },
        "FS": {
          "hide_name": 0,
          "bits": [ 4 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v:5.17-5.19"
          }
        },
        "FZ": {
          "hide_name": 0,
          "bits": [ 5 ],
          "attributes": {
            "DELAY_CONST_F1": "{iopath_F1_FZ}",
            "DELAY_CONST_F2": "{iopath_F2_FZ}",
            "DELAY_CONST_FS": "{iopath_FS_FZ}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v:10.17-10.19"
          }
        }
      }
    }
  }
}
exitcode =======================================================================
0
================================================================================

is_blackbox True has_modes? False
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v; proc; cd F_FRAG; select -write /tmp/tmp598qiavf c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_logic_f_frag.pb_type.xml
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_t_frag.model.xml.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_t_frag.model.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_t_frag.model.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_t_frag.model.xml.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_t_frag.model.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating t_frag.model.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=model -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.model.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v; prep -flatten; write_json -aig']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "T_FRAG": {
      "attributes": {
        "FASM_PARAMS": "INV.TA1=XAS1;INV.TA2=XAS2;INV.TB1=XBS1;INV.TB2=XBS2",
        "whitebox": "00000000000000000000000000000001",
        "MODEL_NAME": "T_FRAG",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:4.1-56.10"
      },
      "parameter_default_values": {
        "XAS1": "0",
        "XAS2": "0",
        "XBS1": "0",
        "XBS2": "0"
      },
      "ports": {
        "TBS": {
          "direction": "input",
          "bits": [ 2 ]
        },
        "XAB": {
          "direction": "input",
          "bits": [ 3 ]
        },
        "XSL": {
          "direction": "input",
          "bits": [ 4 ]
        },
        "XA1": {
          "direction": "input",
          "bits": [ 5 ]
        },
        "XA2": {
          "direction": "input",
          "bits": [ 6 ]
        },
        "XB1": {
          "direction": "input",
          "bits": [ 7 ]
        },
        "XB2": {
          "direction": "input",
          "bits": [ 8 ]
        },
        "XZ": {
          "direction": "output",
          "bits": [ 9 ]
        }
      },
      "cells": {
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:44$1": {
          "hide_name": 1,
          "type": "$mux",
          "model": "$mux:1",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:44.16-44.33"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 5 ],
            "B": [ 6 ],
            "S": [ 4 ],
            "Y": [ 10 ]
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:45$2": {
          "hide_name": 1,
          "type": "$mux",
          "model": "$mux:1",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:45.16-45.33"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 7 ],
            "B": [ 8 ],
            "S": [ 4 ],
            "Y": [ 11 ]
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:48$3": {
          "hide_name": 1,
          "type": "$mux",
          "model": "$mux:1",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:48.16-48.31"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 10 ],
            "B": [ 11 ],
            "S": [ 3 ],
            "Y": [ 12 ]
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:54$4": {
          "hide_name": 1,
          "type": "$mux",
          "model": "$mux:1",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:54.17-54.33"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ "0" ],
            "B": [ 12 ],
            "S": [ 2 ],
            "Y": [ 9 ]
          }
        }
      },
      "netnames": {
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:44$1_Y": {
          "hide_name": 1,
          "bits": [ 10 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:44.16-44.33"
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:45$2_Y": {
          "hide_name": 1,
          "bits": [ 11 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:45.16-45.33"
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:48$3_Y": {
          "hide_name": 1,
          "bits": [ 12 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:48.16-48.31"
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:54$4_Y": {
          "hide_name": 1,
          "bits": [ 9 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:54.17-54.33"
          }
        },
        "TBS": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:9.17-9.20"
          }
        },
        "XA1": {
          "hide_name": 0,
          "bits": [ 5 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:13.17-13.20"
          }
        },
        "XA2": {
          "hide_name": 0,
          "bits": [ 6 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:14.17-14.20"
          }
        },
        "XAB": {
          "hide_name": 0,
          "bits": [ 3 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:11.17-11.20"
          }
        },
        "XAI": {
          "hide_name": 0,
          "bits": [ 10 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:44.10-44.13"
          }
        },
        "XAP1": {
          "hide_name": 0,
          "bits": [ 5 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:38.10-38.14"
          }
        },
        "XAP2": {
          "hide_name": 0,
          "bits": [ 6 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:39.10-39.14"
          }
        },
        "XB1": {
          "hide_name": 0,
          "bits": [ 7 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:15.17-15.20"
          }
        },
        "XB2": {
          "hide_name": 0,
          "bits": [ 8 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:16.17-16.20"
          }
        },
        "XBI": {
          "hide_name": 0,
          "bits": [ 11 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:45.10-45.13"
          }
        },
        "XBP1": {
          "hide_name": 0,
          "bits": [ 7 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:40.10-40.14"
          }
        },
        "XBP2": {
          "hide_name": 0,
          "bits": [ 8 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:41.10-41.14"
          }
        },
        "XSL": {
          "hide_name": 0,
          "bits": [ 4 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:12.17-12.20"
          }
        },
        "XZ": {
          "hide_name": 0,
          "bits": [ 9 ],
          "attributes": {
            "DELAY_CONST_TBS": "{iopath_TBS_CZ}",
            "DELAY_CONST_XA1": "{iopath_TA1_TZ}",
            "DELAY_CONST_XA2": "{iopath_TA2_TZ}",
            "DELAY_CONST_XAB": "{iopath_TAB_TZ}",
            "DELAY_CONST_XB1": "{iopath_TB1_TZ}",
            "DELAY_CONST_XB2": "{iopath_TB2_TZ}",
            "DELAY_CONST_XSL": "{iopath_TSL_TZ}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:29.17-29.19"
          }
        },
        "XZI": {
          "hide_name": 0,
          "bits": [ 12 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v:48.10-48.13"
          }
        }
      }
    }
  },
  "models": {
    "$mux:1": [
      /*   0 */ [ "port", "S", 0 ],
      /*   1 */ [ "port", "A", 0 ],
      /*   2 */ [ "port", "B", 0 ],
      /*   3 */ [ "nport", "S", 0 ],
      /*   4 */ [ "nand", 0, 2 ],
      /*   5 */ [ "nand", 1, 3 ],
      /*   6 */ [ "nand", 4, 5, "Y", 0 ]
    ]
  }
}
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v; proc; cd T_FRAG; select -write /tmp/tmpefbkott3 c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v; proc; cd T_FRAG; select -write /tmp/tmpg6m9_m6y TBS %co* o:* %i TBS %d']
stderr   =======================================================================
Warning: Selection "TBS" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v; proc; cd T_FRAG; select -write /tmp/tmpz1z590oo XA1 %co* o:* %i XA1 %d']
stderr   =======================================================================
Warning: Selection "XA1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v; proc; cd T_FRAG; select -write /tmp/tmpptliaa2u XA2 %co* o:* %i XA2 %d']
stderr   =======================================================================
Warning: Selection "XA2" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v; proc; cd T_FRAG; select -write /tmp/tmpd8o66ot8 XAB %co* o:* %i XAB %d']
stderr   =======================================================================
Warning: Selection "XAB" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v; proc; cd T_FRAG; select -write /tmp/tmpt4yq0wxe XB1 %co* o:* %i XB1 %d']
stderr   =======================================================================
Warning: Selection "XB1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v; proc; cd T_FRAG; select -write /tmp/tmpx5pq7c_j XB2 %co* o:* %i XB2 %d']
stderr   =======================================================================
Warning: Selection "XB2" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v; proc; cd T_FRAG; select -write /tmp/tmpklbsm3em XSL %co* o:* %i XSL %d']
stderr   =======================================================================
Warning: Selection "XSL" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/t_frag.sim.v; proc; cd T_FRAG; select -write /tmp/tmp_k616frj XZ %co* o:* %i XZ %d']
stderr   =======================================================================
Warning: Selection "XZ" did not match any object.
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
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make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_c_frag.sim.v.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_c_frag.sim.v.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_c_frag.sim.v.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_c_frag.sim.v.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_c_frag.sim.v.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating c_frag.sim.v
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic && /usr/bin/cmake -E create_symlink /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/logic/c_frag.sim.v /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/c_frag.sim.v
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_logic_c_frag.sim.v
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_c_frag.pb_type.xml.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_c_frag.pb_type.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_c_frag.pb_type.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_c_frag.pb_type.xml.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_c_frag.pb_type.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating c_frag.pb_type.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=pb_type -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/c_frag.pb_type.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/c_frag.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/c_frag.sim.v; prep ; write_json ']
stdout   =======================================================================
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        "MODEL_NAME": "T_FRAG",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:4.1-56.10"
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      "ports": {
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      "cells": {
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        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:45$2": {
          "hide_name": 1,
          "type": "$mux",
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          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:45.16-45.33"
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          "port_directions": {
            "A": "input",
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          }
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        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:48$3": {
          "hide_name": 1,
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          "parameters": {
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          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:48.16-48.31"
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          "port_directions": {
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            "S": [ 3 ],
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          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:54$4": {
          "hide_name": 1,
          "type": "$mux",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:54.17-54.33"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
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            "B": [ 12 ],
            "S": [ 2 ],
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          }
        }
      },
      "netnames": {
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:44$1_Y": {
          "hide_name": 1,
          "bits": [ 10 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:44.16-44.33"
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:45$2_Y": {
          "hide_name": 1,
          "bits": [ 11 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:45.16-45.33"
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:48$3_Y": {
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          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:48.16-48.31"
          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:54$4_Y": {
          "hide_name": 1,
          "bits": [ 9 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:54.17-54.33"
          }
        },
        "TBS": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:9.17-9.20"
          }
        },
        "XA1": {
          "hide_name": 0,
          "bits": [ 5 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:13.17-13.20"
          }
        },
        "XA2": {
          "hide_name": 0,
          "bits": [ 6 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:14.17-14.20"
          }
        },
        "XAB": {
          "hide_name": 0,
          "bits": [ 3 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:11.17-11.20"
          }
        },
        "XAI": {
          "hide_name": 0,
          "bits": [ 10 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:44.10-44.13"
          }
        },
        "XAP1": {
          "hide_name": 0,
          "bits": [ 5 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:38.10-38.14"
          }
        },
        "XAP2": {
          "hide_name": 0,
          "bits": [ 6 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:39.10-39.14"
          }
        },
        "XB1": {
          "hide_name": 0,
          "bits": [ 7 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:15.17-15.20"
          }
        },
        "XB2": {
          "hide_name": 0,
          "bits": [ 8 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:16.17-16.20"
          }
        },
        "XBI": {
          "hide_name": 0,
          "bits": [ 11 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:45.10-45.13"
          }
        },
        "XBP1": {
          "hide_name": 0,
          "bits": [ 7 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:40.10-40.14"
          }
        },
        "XBP2": {
          "hide_name": 0,
          "bits": [ 8 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:41.10-41.14"
          }
        },
        "XSL": {
          "hide_name": 0,
          "bits": [ 4 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:12.17-12.20"
          }
        },
        "XZ": {
          "hide_name": 0,
          "bits": [ 9 ],
          "attributes": {
            "DELAY_CONST_TBS": "{iopath_TBS_CZ}",
            "DELAY_CONST_XA1": "{iopath_TA1_TZ}",
            "DELAY_CONST_XA2": "{iopath_TA2_TZ}",
            "DELAY_CONST_XAB": "{iopath_TAB_TZ}",
            "DELAY_CONST_XB1": "{iopath_TB1_TZ}",
            "DELAY_CONST_XB2": "{iopath_TB2_TZ}",
            "DELAY_CONST_XSL": "{iopath_TSL_TZ}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:29.17-29.19"
          }
        },
        "XZI": {
          "hide_name": 0,
          "bits": [ 12 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:48.10-48.13"
          }
        }
      }
    }
  }
}
exitcode =======================================================================
0
================================================================================

is_blackbox False has_modes? False
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/c_frag.sim.v; proc; cd C_FRAG; select -write /tmp/tmpimodn0cc c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

[[(('b_frag', 'TBS'), {}), (('t_frag', 'TBS'), {})],
 [(('b_frag', 'XA1'), {})],
 [(('b_frag', 'XA2'), {})],
 [(('b_frag', 'XAB'), {})],
 [(('b_frag', 'XB1'), {})],
 [(('b_frag', 'XB2'), {})],
 [(('b_frag', 'XSL'), {})],
 [((None, 'CZ'),
   {'DELAY_CONST_TBS': '{iopath_TBS_CZ}',
    'DELAY_CONST_XA1': '{iopath_BA1_CZ}',
    'DELAY_CONST_XA2': '{iopath_BA2_CZ}',
    'DELAY_CONST_XAB': '{iopath_BAB_CZ}',
    'DELAY_CONST_XB1': '{iopath_BB1_CZ}',
    'DELAY_CONST_XB2': '{iopath_BB2_CZ}',
    'DELAY_CONST_XSL': '{iopath_BSL_CZ}'})],
 [(('t_frag', 'XA1'), {})],
 [(('t_frag', 'XA2'), {})],
 [(('t_frag', 'XAB'), {})],
 [(('t_frag', 'XB1'), {})],
 [(('t_frag', 'XB2'), {})],
 [(('t_frag', 'XSL'), {})],
 [((None, 'TZ'),
   {'DELAY_CONST_TBS': '{iopath_TBS_CZ}',
    'DELAY_CONST_XA1': '{iopath_TA1_TZ}',
    'DELAY_CONST_XA2': '{iopath_TA2_TZ}',
    'DELAY_CONST_XAB': '{iopath_TAB_TZ}',
    'DELAY_CONST_XB1': '{iopath_TB1_TZ}',
    'DELAY_CONST_XB2': '{iopath_TB2_TZ}',
    'DELAY_CONST_XSL': '{iopath_TSL_TZ}'})]]
C_FRAG
--
defaultdict(<class 'list'>,
            {('b_frag', 'XZ'): [((None, 'CZ'),
                                 {'DELAY_CONST_TBS': '{iopath_TBS_CZ}',
                                  'DELAY_CONST_XA1': '{iopath_BA1_CZ}',
                                  'DELAY_CONST_XA2': '{iopath_BA2_CZ}',
                                  'DELAY_CONST_XAB': '{iopath_BAB_CZ}',
                                  'DELAY_CONST_XB1': '{iopath_BB1_CZ}',
                                  'DELAY_CONST_XB2': '{iopath_BB2_CZ}',
                                  'DELAY_CONST_XSL': '{iopath_BSL_CZ}'})],
             (None, 'BA1'): [(('b_frag', 'XA1'), {})],
             (None, 'BA2'): [(('b_frag', 'XA2'), {})],
             (None, 'BAB'): [(('b_frag', 'XAB'), {})],
             ('t_frag', 'XZ'): [((None, 'TZ'),
                                 {'DELAY_CONST_TBS': '{iopath_TBS_CZ}',
                                  'DELAY_CONST_XA1': '{iopath_TA1_TZ}',
                                  'DELAY_CONST_XA2': '{iopath_TA2_TZ}',
                                  'DELAY_CONST_XAB': '{iopath_TAB_TZ}',
                                  'DELAY_CONST_XB1': '{iopath_TB1_TZ}',
                                  'DELAY_CONST_XB2': '{iopath_TB2_TZ}',
                                  'DELAY_CONST_XSL': '{iopath_TSL_TZ}'})],
             (None, 'BB1'): [(('b_frag', 'XB1'), {})],
             (None, 'BB2'): [(('b_frag', 'XB2'), {})],
             (None, 'BSL'): [(('b_frag', 'XSL'), {})],
             (None, 'TA1'): [(('t_frag', 'XA1'), {})],
             (None, 'TA2'): [(('t_frag', 'XA2'), {})],
             (None, 'TAB'): [(('t_frag', 'XAB'), {})],
             (None, 'TB1'): [(('t_frag', 'XB1'), {})],
             (None, 'TB2'): [(('t_frag', 'XB2'), {})],
             (None, 'TBS'): [(('b_frag', 'TBS'), {}), (('t_frag', 'TBS'), {})],
             (None, 'TSL'): [(('t_frag', 'XSL'), {})]})
--
[]
{}
--
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_logic_c_frag.pb_type.xml
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_c_frag.model.xml.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_c_frag.model.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_c_frag.model.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_c_frag.model.xml.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_c_frag.model.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating c_frag.model.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=model -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/c_frag.model.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/c_frag.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/c_frag.sim.v; prep -flatten; write_json -aig']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "B_FRAG": {
      "attributes": {
        "FASM_PARAMS": "INV.BA1=XAS1;INV.BA2=XAS2;INV.BB1=XBS1;INV.BB2=XBS2",
        "whitebox": "00000000000000000000000000000001",
        "MODEL_NAME": "T_FRAG",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./b_frag.sim.v:4.1-54.10"
      },
      "parameter_default_values": {
        "XAS1": "0",
        "XAS2": "0",
        "XBS1": "0",
        "XBS2": "0"
      },
      "ports": {
        "TBS": {
          "direction": "input",
          "bits": [ 2 ]
        },
        "XAB": {
          "direction": "input",
          "bits": [ 3 ]
        },
        "XSL": {
          "direction": "input",
          "bits": [ 4 ]
        },
        "XA1": {
          "direction": "input",
          "bits": [ 5 ]
        },
        "XA2": {
          "direction": "input",
          "bits": [ 6 ]
        },
        "XB1": {
          "direction": "input",
          "bits": [ 7 ]
        },
        "XB2": {
          "direction": "input",
          "bits": [ 8 ]
        },
        "XZ": {
          "direction": "output",
          "bits": [ 9 ]
        }
      },
      "cells": {
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./b_frag.sim.v:42$5": {
          "hide_name": 1,
          "type": "$mux",
          "model": "$mux:1",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./b_frag.sim.v:42.16-42.33"
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          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./b_frag.sim.v:43$6": {
          "hide_name": 1,
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            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
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        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./b_frag.sim.v:46$7": {
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        }
      },
      "netnames": {
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./b_frag.sim.v:42$5_Y": {
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            "DELAY_CONST_XA1": "{iopath_TA1_TZ}",
            "DELAY_CONST_XA2": "{iopath_TA2_TZ}",
            "DELAY_CONST_XAB": "{iopath_TAB_TZ}",
            "DELAY_CONST_XB1": "{iopath_TB1_TZ}",
            "DELAY_CONST_XB2": "{iopath_TB2_TZ}",
            "DELAY_CONST_XSL": "{iopath_TSL_TZ}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:29.17-29.19"
          }
        },
        "XZI": {
          "hide_name": 0,
          "bits": [ 12 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/./t_frag.sim.v:48.10-48.13"
          }
        }
      }
    }
  },
  "models": {
    "$mux:1": [
      /*   0 */ [ "port", "S", 0 ],
      /*   1 */ [ "port", "A", 0 ],
      /*   2 */ [ "port", "B", 0 ],
      /*   3 */ [ "nport", "S", 0 ],
      /*   4 */ [ "nand", 0, 2 ],
      /*   5 */ [ "nand", 1, 3 ],
      /*   6 */ [ "nand", 4, 5, "Y", 0 ]
    ]
  }
}
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_logic_c_frag.model.xml
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_q_frag.pb_type.xml.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_q_frag.pb_type.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_q_frag.pb_type.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_q_frag.pb_type.xml.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_q_frag.pb_type.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating q_frag.pb_type.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=pb_type -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.pb_type.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v; prep ; write_json ']
stdout   =======================================================================
{
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  "modules": {
    "Q_FRAG": {
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        "FASM_PARAMS": "ZINV.QCK=Z_QCKS",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:3.1-53.10"
      },
      "parameter_default_values": {
        "Z_QCKS": "1"
      },
      "ports": {
        "QCK": {
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          "bits": [ 2 ]
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        "QRT": {
          "direction": "input",
          "bits": [ 4 ]
        },
        "QEN": {
          "direction": "input",
          "bits": [ 5 ]
        },
        "QDI": {
          "direction": "input",
          "bits": [ 6 ]
        },
        "QDS": {
          "direction": "input",
          "bits": [ 7 ]
        },
        "CZI": {
          "direction": "input",
          "bits": [ 8 ]
        },
        "QZ": {
          "direction": "output",
          "bits": [ 9 ]
        }
      },
      "cells": {
        "$auto$proc_dff.cc:105:gen_dffsr_complex$12": {
          "hide_name": 1,
          "type": "$not",
          "parameters": {
            "A_SIGNED": "00000000000000000000000000000000",
            "A_WIDTH": "00000000000000000000000000000001",
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          "attributes": {
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          "port_directions": {
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          "connections": {
            "A": [ "0" ],
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          }
        },
        "$auto$proc_dff.cc:105:gen_dffsr_complex$6": {
          "hide_name": 1,
          "type": "$not",
          "parameters": {
            "A_SIGNED": "00000000000000000000000000000000",
            "A_WIDTH": "00000000000000000000000000000001",
            "Y_WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
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          "port_directions": {
            "A": "input",
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          },
          "connections": {
            "A": [ "1" ],
            "Y": [ 11 ]
          }
        },
        "$auto$proc_dff.cc:112:gen_dffsr_complex$14": {
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            "WIDTH": "00000000000000000000000000000001"
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        "$auto$proc_dff.cc:112:gen_dffsr_complex$8": {
          "hide_name": 1,
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          "port_directions": {
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        "$auto$proc_dff.cc:119:gen_dffsr_complex$10": {
          "hide_name": 1,
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        "$auto$proc_dff.cc:119:gen_dffsr_complex$16": {
          "hide_name": 1,
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          "port_directions": {
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          "connections": {
            "A": [ 14 ],
            "B": [ 10 ],
            "S": [ 4 ],
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          }
        },
        "$procdff$18": {
          "hide_name": 1,
          "type": "$dffsr",
          "parameters": {
            "CLK_POLARITY": "1",
            "CLR_POLARITY": "1",
            "SET_POLARITY": "1",
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:44.2-51.5"
          },
          "port_directions": {
            "CLK": "input",
            "CLR": "input",
            "D": "input",
            "Q": "output",
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          "connections": {
            "CLK": [ 2 ],
            "CLR": [ 15 ],
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            "SET": [ 13 ]
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        "$procmux$4": {
          "hide_name": 1,
          "type": "$mux",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:49.12-49.15|/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:49.8-50.12"
          },
          "port_directions": {
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          "connections": {
            "A": [ 9 ],
            "B": [ 17 ],
            "S": [ 5 ],
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          }
        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:40$1": {
          "hide_name": 1,
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          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:40.14-40.31"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
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          "connections": {
            "A": [ 8 ],
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            "S": [ 7 ],
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        }
      },
      "netnames": {
        "$0\\QZ[0:0]": {
          "hide_name": 1,
          "bits": [ 16 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:44.2-51.5"
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        },
        "$1\\QZ[0:0]": {
          "hide_name": 1,
          "bits": [ "0" ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:0.0-0.0"
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        },
        "$auto$proc_dff.cc:110:gen_dffsr_complex$13": {
          "hide_name": 1,
          "bits": [ 10 ],
          "attributes": {
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        },
        "$auto$proc_dff.cc:110:gen_dffsr_complex$7": {
          "hide_name": 1,
          "bits": [ 11 ],
          "attributes": {
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        },
        "$auto$proc_dff.cc:117:gen_dffsr_complex$15": {
          "hide_name": 1,
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        },
        "$auto$proc_dff.cc:117:gen_dffsr_complex$9": {
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        "$auto$proc_dff.cc:124:gen_dffsr_complex$11": {
          "hide_name": 1,
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        },
        "$auto$proc_dff.cc:124:gen_dffsr_complex$17": {
          "hide_name": 1,
          "bits": [ 15 ],
          "attributes": {
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        },
        "$procmux$4_Y": {
          "hide_name": 1,
          "bits": [ 16 ],
          "attributes": {
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        },
        "$procmux$5_CMP": {
          "hide_name": 1,
          "bits": [ 5 ],
          "attributes": {
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        },
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:40$1_Y": {
          "hide_name": 1,
          "bits": [ 17 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:40.14-40.31"
          }
        },
        "CZI": {
          "hide_name": 0,
          "bits": [ 8 ],
          "attributes": {
            "HOLD": "QCK {hold_QCK_QDI}",
            "NO_COMB": "00000000000000000000000000000001",
            "SETUP": "QCK {setup_QCK_QDI}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:31.17-31.20"
          }
        },
        "QCK": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "CLOCK": "00000000000000000000000000000001",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:5.17-5.20"
          }
        },
        "QDI": {
          "hide_name": 0,
          "bits": [ 6 ],
          "attributes": {
            "HOLD": "QCK {hold_QCK_QDI}",
            "NO_COMB": "00000000000000000000000000000001",
            "SETUP": "QCK {setup_QCK_QDI}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:21.17-21.20"
          }
        },
        "QDS": {
          "hide_name": 0,
          "bits": [ 7 ],
          "attributes": {
            "HOLD": "QCK {hold_QCK_QDS}",
            "NO_COMB": "00000000000000000000000000000001",
            "SETUP": "QCK {setup_QCK_QDS}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:25.17-25.20"
          }
        },
        "QEN": {
          "hide_name": 0,
          "bits": [ 5 ],
          "attributes": {
            "NO_COMB": "00000000000000000000000000000001",
            "SETUP": "QCK 1e-10",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:17.17-17.20"
          }
        },
        "QRT": {
          "hide_name": 0,
          "bits": [ 4 ],
          "attributes": {
            "NO_COMB": "00000000000000000000000000000001",
            "SETUP": "QCK 1e-10",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:13.17-13.20"
          }
        },
        "QST": {
          "hide_name": 0,
          "bits": [ 3 ],
          "attributes": {
            "NO_COMB": "00000000000000000000000000000001",
            "SETUP": "QCK 1e-10",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:9.17-9.20"
          }
        },
        "QZ": {
          "hide_name": 0,
          "bits": [ 9 ],
          "attributes": {
            "CLK_TO_Q": "QCK {setuphold_QCK_QZ}",
            "init": "0",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:34.17-34.19"
          }
        },
        "d": {
          "hide_name": 0,
          "bits": [ 17 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v:40.10-40.11"
          }
        }
      }
    }
  }
}
stderr   =======================================================================
Warning: Complex async reset for dff `\QZ'.
exitcode =======================================================================
0
================================================================================

is_blackbox True has_modes? False
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/q_frag.sim.v; proc; cd Q_FRAG; select -write /tmp/tmpfhvrcn7e c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
stderr   =======================================================================
Warning: Complex async reset for dff `\QZ'.
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_logic_q_frag.pb_type.xml
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_f_frag.model.xml.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_f_frag.model.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_f_frag.model.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_f_frag.model.xml.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_f_frag.model.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating f_frag.model.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=model -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.model.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v; prep -flatten; write_json -aig']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "F_FRAG": {
      "attributes": {
        "whitebox": "00000000000000000000000000000001",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v:2.1-15.10"
      },
      "ports": {
        "F1": {
          "direction": "input",
          "bits": [ 2 ]
        },
        "F2": {
          "direction": "input",
          "bits": [ 3 ]
        },
        "FS": {
          "direction": "input",
          "bits": [ 4 ]
        },
        "FZ": {
          "direction": "output",
          "bits": [ 5 ]
        }
      },
      "cells": {
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v:13$1": {
          "hide_name": 1,
          "type": "$mux",
          "model": "$mux:1",
          "parameters": {
            "WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v:13.17-13.29"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 2 ],
            "B": [ 3 ],
            "S": [ 4 ],
            "Y": [ 5 ]
          }
        }
      },
      "netnames": {
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v:13$1_Y": {
          "hide_name": 1,
          "bits": [ 5 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v:13.17-13.29"
          }
        },
        "F1": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v:3.17-3.19"
          }
        },
        "F2": {
          "hide_name": 0,
          "bits": [ 3 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v:4.17-4.19"
          }
        },
        "FS": {
          "hide_name": 0,
          "bits": [ 4 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v:5.17-5.19"
          }
        },
        "FZ": {
          "hide_name": 0,
          "bits": [ 5 ],
          "attributes": {
            "DELAY_CONST_F1": "{iopath_F1_FZ}",
            "DELAY_CONST_F2": "{iopath_F2_FZ}",
            "DELAY_CONST_FS": "{iopath_FS_FZ}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v:10.17-10.19"
          }
        }
      }
    }
  },
  "models": {
    "$mux:1": [
      /*   0 */ [ "port", "S", 0 ],
      /*   1 */ [ "port", "A", 0 ],
      /*   2 */ [ "port", "B", 0 ],
      /*   3 */ [ "nport", "S", 0 ],
      /*   4 */ [ "nand", 0, 2 ],
      /*   5 */ [ "nand", 1, 3 ],
      /*   6 */ [ "nand", 4, 5, "Y", 0 ]
    ]
  }
}
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v; proc; cd F_FRAG; select -write /tmp/tmp82k4vyfx c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v; proc; cd F_FRAG; select -write /tmp/tmp0_d7fh4_ F1 %co* o:* %i F1 %d']
stderr   =======================================================================
Warning: Selection "F1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v; proc; cd F_FRAG; select -write /tmp/tmpoax9r923 F2 %co* o:* %i F2 %d']
stderr   =======================================================================
Warning: Selection "F2" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v; proc; cd F_FRAG; select -write /tmp/tmp3sn5mswf FS %co* o:* %i FS %d']
stderr   =======================================================================
Warning: Selection "FS" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/f_frag.sim.v; proc; cd F_FRAG; select -write /tmp/tmpg3q7nxld FZ %co* o:* %i FZ %d']
stderr   =======================================================================
Warning: Selection "FZ" did not match any object.
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_logic_f_frag.model.xml
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_logic.sim.v.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_logic.sim.v.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_logic.sim.v.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_logic.sim.v.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_logic.sim.v.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating logic.sim.v
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic && /usr/bin/cmake -E create_symlink /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/logic/logic.sim.v /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/logic.sim.v
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Built target file_quicklogic_primitives_logic_logic.sim.v
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_logic.pb_type.xml.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_logic.pb_type.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_logic.pb_type.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_logic.pb_type.xml.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_logic.pb_type.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[  0%] Generating logic.pb_type.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=pb_type -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/logic.pb_type.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/logic.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/logic.sim.v; prep ; write_json ']
stdout   =======================================================================
{
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    "B_FRAG": {
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        "whitebox": "00000000000000000000000000000001",
        "MODEL_NAME": "T_FRAG",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/././b_frag.sim.v:4.1-54.10"
      },
      "parameter_default_values": {
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      "ports": {
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        "XAB": {
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        "XSL": {
          "direction": "input",
          "bits": [ 4 ]
        },
        "XA1": {
          "direction": "input",
          "bits": [ 5 ]
        },
        "XA2": {
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        },
        "XB1": {
          "direction": "input",
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        },
        "XB2": {
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        },
        "XZ": {
          "direction": "output",
          "bits": [ 9 ]
        }
      },
      "cells": {
        "$ternary$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/././b_frag.sim.v:42$5": {
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        "XAP1": {
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    },
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        "XB1": {
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        "XB2": {
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        },
        "XBI": {
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          "attributes": {
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          }
        },
        "XBP1": {
          "hide_name": 0,
          "bits": [ 7 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/././t_frag.sim.v:40.10-40.14"
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        },
        "XBP2": {
          "hide_name": 0,
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          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/././t_frag.sim.v:41.10-41.14"
          }
        },
        "XSL": {
          "hide_name": 0,
          "bits": [ 4 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/././t_frag.sim.v:12.17-12.20"
          }
        },
        "XZ": {
          "hide_name": 0,
          "bits": [ 9 ],
          "attributes": {
            "DELAY_CONST_TBS": "{iopath_TBS_CZ}",
            "DELAY_CONST_XA1": "{iopath_TA1_TZ}",
            "DELAY_CONST_XA2": "{iopath_TA2_TZ}",
            "DELAY_CONST_XAB": "{iopath_TAB_TZ}",
            "DELAY_CONST_XB1": "{iopath_TB1_TZ}",
            "DELAY_CONST_XB2": "{iopath_TB2_TZ}",
            "DELAY_CONST_XSL": "{iopath_TSL_TZ}",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/././t_frag.sim.v:29.17-29.19"
          }
        },
        "XZI": {
          "hide_name": 0,
          "bits": [ 12 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/././t_frag.sim.v:48.10-48.13"
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      }
    }
  }
}
stderr   =======================================================================
Warning: Complex async reset for dff `\QZ'.
exitcode =======================================================================
0
================================================================================

is_blackbox False has_modes? False
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/logic.sim.v; proc; cd LOGIC; select -write /tmp/tmp_a4yaw3q c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
stderr   =======================================================================
Warning: Complex async reset for dff `\QZ'.
exitcode =======================================================================
0
================================================================================

[[(('c_frag', 'BA1'), {})],
 [(('c_frag', 'BA2'), {})],
 [(('c_frag', 'BAB'), {})],
 [(('c_frag', 'BB1'), {})],
 [(('c_frag', 'BB2'), {})],
 [(('c_frag', 'BSL'), {})],
 [(('c_frag', 'TA1'), {})],
 [(('c_frag', 'TA2'), {})],
 [(('c_frag', 'TAB'), {})],
 [(('c_frag', 'TB1'), {})],
 [(('c_frag', 'TB2'), {})],
 [(('c_frag', 'TBS'), {})],
 [(('c_frag', 'TSL'), {})],
 [((None, 'CZ'), {})],
 [((None, 'TZ'), {})],
 [(('f_frag', 'F1'), {})],
 [(('f_frag', 'F2'), {})],
 [(('f_frag', 'FS'), {})],
 [((None, 'FZ'),
   {'DELAY_CONST_F1': '{iopath_F1_FZ}',
    'DELAY_CONST_F2': '{iopath_F2_FZ}',
    'DELAY_CONST_FS': '{iopath_FS_FZ}'})],
 [(('q_frag', 'QCK'), {'CLOCK': '00000000000000000000000000000001'})],
 [(('q_frag', 'QDI'),
   {'HOLD': 'QCK {hold_QCK_QDI}',
    'NO_COMB': '00000000000000000000000000000001',
    'SETUP': 'QCK {setup_QCK_QDI}'})],
 [(('q_frag', 'QDS'),
   {'HOLD': 'QCK {hold_QCK_QDS}',
    'NO_COMB': '00000000000000000000000000000001',
    'SETUP': 'QCK {setup_QCK_QDS}'})],
 [(('q_frag', 'QEN'),
   {'NO_COMB': '00000000000000000000000000000001', 'SETUP': 'QCK 1e-10'})],
 [(('q_frag', 'QRT'),
   {'NO_COMB': '00000000000000000000000000000001', 'SETUP': 'QCK 1e-10'})],
 [(('q_frag', 'QST'),
   {'NO_COMB': '00000000000000000000000000000001', 'SETUP': 'QCK 1e-10'})],
 [((None, 'QZ'), {'CLK_TO_Q': 'QCK {setuphold_QCK_QZ}', 'init': '0'})]]
LOGIC
--
defaultdict(<class 'list'>,
            {('c_frag', 'CZ'): [((None, 'CZ'), {})],
             ('f_frag', 'FZ'): [((None, 'FZ'),
                                 {'DELAY_CONST_F1': '{iopath_F1_FZ}',
                                  'DELAY_CONST_F2': '{iopath_F2_FZ}',
                                  'DELAY_CONST_FS': '{iopath_FS_FZ}'})],
             (None, 'BA1'): [(('c_frag', 'BA1'), {})],
             (None, 'BA2'): [(('c_frag', 'BA2'), {})],
             (None, 'BAB'): [(('c_frag', 'BAB'), {})],
             (None, 'BB1'): [(('c_frag', 'BB1'), {})],
             (None, 'BB2'): [(('c_frag', 'BB2'), {})],
             (None, 'BSL'): [(('c_frag', 'BSL'), {})],
             (None, 'F1'): [(('f_frag', 'F1'), {})],
             (None, 'F2'): [(('f_frag', 'F2'), {})],
             (None, 'FS'): [(('f_frag', 'FS'), {})],
             (None, 'QCK'): [(('q_frag', 'QCK'),
                              {'CLOCK': '00000000000000000000000000000001'})],
             (None, 'QDI'): [(('q_frag', 'QDI'),
                              {'HOLD': 'QCK {hold_QCK_QDI}',
                               'NO_COMB': '00000000000000000000000000000001',
                               'SETUP': 'QCK {setup_QCK_QDI}'})],
             (None, 'QDS'): [(('q_frag', 'QDS'),
                              {'HOLD': 'QCK {hold_QCK_QDS}',
                               'NO_COMB': '00000000000000000000000000000001',
                               'SETUP': 'QCK {setup_QCK_QDS}'})],
             (None, 'QEN'): [(('q_frag', 'QEN'),
                              {'NO_COMB': '00000000000000000000000000000001',
                               'SETUP': 'QCK 1e-10'})],
             ('q_frag', 'QZ'): [((None, 'QZ'),
                                 {'CLK_TO_Q': 'QCK {setuphold_QCK_QZ}',
                                  'init': '0'})],
             (None, 'QRT'): [(('q_frag', 'QRT'),
                              {'NO_COMB': '00000000000000000000000000000001',
                               'SETUP': 'QCK 1e-10'})],
             (None, 'QST'): [(('q_frag', 'QST'),
                              {'NO_COMB': '00000000000000000000000000000001',
                               'SETUP': 'QCK 1e-10'})],
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--
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Built target file_quicklogic_primitives_logic_logic.pb_type.xml
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_logic.model.xml.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_logic.model.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_logic.model.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_logic.model.xml.dir/build.make quicklogic/primitives/logic/CMakeFiles/file_quicklogic_primitives_logic_logic.model.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Generating logic.model.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=model -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/logic.model.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/logic.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/logic/logic.sim.v; prep -flatten; write_json -aig']
stdout   =======================================================================
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stderr   =======================================================================
Warning: Complex async reset for dff `\QZ'.
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Built target file_quicklogic_primitives_logic_logic.model.xml
make -f quicklogic/primitives/assp/CMakeFiles/file_quicklogic_primitives_assp_assp.sim.v.dir/build.make quicklogic/primitives/assp/CMakeFiles/file_quicklogic_primitives_assp_assp.sim.v.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/assp /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/CMakeFiles/file_quicklogic_primitives_assp_assp.sim.v.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/assp/CMakeFiles/file_quicklogic_primitives_assp_assp.sim.v.dir/build.make quicklogic/primitives/assp/CMakeFiles/file_quicklogic_primitives_assp_assp.sim.v.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Generating assp.sim.v
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp && /usr/bin/cmake -E create_symlink /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/assp/assp.sim.v /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
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make -f quicklogic/primitives/assp/CMakeFiles/file_quicklogic_primitives_assp_assp.pb_type.xml.dir/build.make quicklogic/primitives/assp/CMakeFiles/file_quicklogic_primitives_assp_assp.pb_type.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/assp /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/CMakeFiles/file_quicklogic_primitives_assp_assp.pb_type.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/assp/CMakeFiles/file_quicklogic_primitives_assp_assp.pb_type.xml.dir/build.make quicklogic/primitives/assp/CMakeFiles/file_quicklogic_primitives_assp_assp.pb_type.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Generating assp.pb_type.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=pb_type -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.pb_type.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; prep ; write_json ']
stdout   =======================================================================
{
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      },
      "ports": {
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        "WBs_BYTE_STB": {
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          "bits": [ 36, 37, 38, 39 ]
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        "WBs_WE": {
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        "WBs_STB": {
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        "WBs_ADR": {
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          "bits": [ 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131 ]
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        "WBs_WR_DAT": {
          "direction": "output",
          "bits": [ 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163 ]
        },
        "FB_PKfbPush": {
          "direction": "input",
          "bits": [ 164, 165, 166, 167 ]
        },
        "FB_PKfbSOF": {
          "direction": "input",
          "bits": [ 168 ]
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        "FB_PKfbEOF": {
          "direction": "input",
          "bits": [ 169 ]
        },
        "Sensor_Int": {
          "direction": "output",
          "bits": [ 170, 171, 172, 173, 174, 175, 176, 177 ]
        },
        "FB_PKfbOverflow": {
          "direction": "output",
          "bits": [ 178 ]
        },
        "TimeStamp": {
          "direction": "output",
          "bits": [ 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202 ]
        },
        "Sys_PSel": {
          "direction": "input",
          "bits": [ 203 ]
        },
        "SPIm_Paddr": {
          "direction": "input",
          "bits": [ 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219 ]
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        "SPIm_PEnable": {
          "direction": "input",
          "bits": [ 220 ]
        },
        "SPIm_PWrite": {
          "direction": "input",
          "bits": [ 221 ]
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        "SPIm_PWdata": {
          "direction": "input",
          "bits": [ 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253 ]
        },
        "SPIm_PReady": {
          "direction": "output",
          "bits": [ 254 ]
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        "SPIm_PSlvErr": {
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          "bits": [ 255 ]
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        "SPIm_Prdata": {
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          "bits": [ 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287 ]
        },
        "Device_ID": {
          "direction": "input",
          "bits": [ 288, 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303 ]
        }
      },
      "cells": {
      },
      "netnames": {
        "Device_ID": {
          "hide_name": 0,
          "bits": [ 288, 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303 ],
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          "bits": [ 90 ],
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        "FB_Int_Clr": {
          "hide_name": 0,
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        "FB_PKfbData": {
          "hide_name": 0,
          "bits": [ 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131 ],
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        },
        "FB_PKfbEOF": {
          "hide_name": 0,
          "bits": [ 169 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:33.17-33.27"
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        },
        "FB_PKfbOverflow": {
          "hide_name": 0,
          "bits": [ 178 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:35.17-35.32"
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        },
        "FB_PKfbPush": {
          "hide_name": 0,
          "bits": [ 164, 165, 166, 167 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:31.17-31.28"
          }
        },
        "FB_PKfbSOF": {
          "hide_name": 0,
          "bits": [ 168 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:32.17-32.27"
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        },
        "FB_Start": {
          "hide_name": 0,
          "bits": [ 89 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:18.17-18.25"
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        },
        "FB_msg_out": {
          "hide_name": 0,
          "bits": [ 77, 78, 79, 80 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:16.17-16.27"
          }
        },
        "SDMA_Active": {
          "hide_name": 0,
          "bits": [ 73, 74, 75, 76 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:15.17-15.28"
          }
        },
        "SDMA_Done": {
          "hide_name": 0,
          "bits": [ 69, 70, 71, 72 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:14.17-14.26"
          }
        },
        "SDMA_Req": {
          "hide_name": 0,
          "bits": [ 61, 62, 63, 64 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:12.17-12.25"
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        },
        "SDMA_Sreq": {
          "hide_name": 0,
          "bits": [ 65, 66, 67, 68 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:13.17-13.26"
          }
        },
        "SPIm_PEnable": {
          "hide_name": 0,
          "bits": [ 220 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:39.17-39.29"
          }
        },
        "SPIm_PReady": {
          "hide_name": 0,
          "bits": [ 254 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:42.17-42.28"
          }
        },
        "SPIm_PSlvErr": {
          "hide_name": 0,
          "bits": [ 255 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:43.17-43.29"
          }
        },
        "SPIm_PWdata": {
          "hide_name": 0,
          "bits": [ 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:41.17-41.28"
          }
        },
        "SPIm_PWrite": {
          "hide_name": 0,
          "bits": [ 221 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:40.17-40.28"
          }
        },
        "SPIm_Paddr": {
          "hide_name": 0,
          "bits": [ 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:38.17-38.27"
          }
        },
        "SPIm_Prdata": {
          "hide_name": 0,
          "bits": [ 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:44.17-44.28"
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        },
        "Sensor_Int": {
          "hide_name": 0,
          "bits": [ 170, 171, 172, 173, 174, 175, 176, 177 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:34.17-34.27"
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        },
        "Sys_Clk0": {
          "hide_name": 0,
          "bits": [ 93 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:22.17-22.25"
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        "Sys_Clk0_Rst": {
          "hide_name": 0,
          "bits": [ 94 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:23.17-23.29"
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        },
        "Sys_Clk1": {
          "hide_name": 0,
          "bits": [ 95 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:24.17-24.25"
          }
        },
        "Sys_Clk1_Rst": {
          "hide_name": 0,
          "bits": [ 96 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:25.17-25.29"
          }
        },
        "Sys_PKfb_Clk": {
          "hide_name": 0,
          "bits": [ 99 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:28.17-28.29"
          }
        },
        "Sys_PKfb_Rst": {
          "hide_name": 0,
          "bits": [ 92 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:21.17-21.29"
          }
        },
        "Sys_PSel": {
          "hide_name": 0,
          "bits": [ 203 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:37.17-37.25"
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        },
        "Sys_Pclk": {
          "hide_name": 0,
          "bits": [ 97 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:26.17-26.25"
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        "Sys_Pclk_Rst": {
          "hide_name": 0,
          "bits": [ 98 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:27.17-27.29"
          }
        },
        "TimeStamp": {
          "hide_name": 0,
          "bits": [ 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:36.17-36.26"
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        "WB_CLK": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:3.17-3.23"
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        },
        "WB_RST": {
          "hide_name": 0,
          "bits": [ 91 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:20.17-20.23"
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        },
        "WBs_ACK": {
          "hide_name": 0,
          "bits": [ 3 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:4.17-4.24"
          }
        },
        "WBs_ADR": {
          "hide_name": 0,
          "bits": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:11.17-11.24"
          }
        },
        "WBs_BYTE_STB": {
          "hide_name": 0,
          "bits": [ 36, 37, 38, 39 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:6.17-6.29"
          }
        },
        "WBs_CYC": {
          "hide_name": 0,
          "bits": [ 40 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:7.17-7.24"
          }
        },
        "WBs_RD": {
          "hide_name": 0,
          "bits": [ 42 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:9.17-9.23"
          }
        },
        "WBs_RD_DAT": {
          "hide_name": 0,
          "bits": [ 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:5.17-5.27"
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        "WBs_STB": {
          "hide_name": 0,
          "bits": [ 43 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:10.17-10.24"
          }
        },
        "WBs_WE": {
          "hide_name": 0,
          "bits": [ 41 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:8.17-8.23"
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        },
        "WBs_WR_DAT": {
          "hide_name": 0,
          "bits": [ 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:30.17-30.27"
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        }
      }
    }
  }
}
exitcode =======================================================================
0
================================================================================

is_blackbox True has_modes? False
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmpjvlikyan c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Built target file_quicklogic_primitives_assp_assp.pb_type.xml
make -f quicklogic/primitives/assp/CMakeFiles/file_quicklogic_primitives_assp_assp.model.xml.dir/build.make quicklogic/primitives/assp/CMakeFiles/file_quicklogic_primitives_assp_assp.model.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/assp /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/CMakeFiles/file_quicklogic_primitives_assp_assp.model.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/assp/CMakeFiles/file_quicklogic_primitives_assp_assp.model.xml.dir/build.make quicklogic/primitives/assp/CMakeFiles/file_quicklogic_primitives_assp_assp.model.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Generating assp.model.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=model -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.model.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; prep -flatten; write_json -aig']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "ASSP": {
      "attributes": {
        "blackbox": "00000000000000000000000000000001",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:2.1-48.10"
      },
      "ports": {
        "WB_CLK": {
          "direction": "input",
          "bits": [ 2 ]
        },
        "WBs_ACK": {
          "direction": "input",
          "bits": [ 3 ]
        },
        "WBs_RD_DAT": {
          "direction": "input",
          "bits": [ 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35 ]
        },
        "WBs_BYTE_STB": {
          "direction": "output",
          "bits": [ 36, 37, 38, 39 ]
        },
        "WBs_CYC": {
          "direction": "output",
          "bits": [ 40 ]
        },
        "WBs_WE": {
          "direction": "output",
          "bits": [ 41 ]
        },
        "WBs_RD": {
          "direction": "output",
          "bits": [ 42 ]
        },
        "WBs_STB": {
          "direction": "output",
          "bits": [ 43 ]
        },
        "WBs_ADR": {
          "direction": "output",
          "bits": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60 ]
        },
        "SDMA_Req": {
          "direction": "input",
          "bits": [ 61, 62, 63, 64 ]
        },
        "SDMA_Sreq": {
          "direction": "input",
          "bits": [ 65, 66, 67, 68 ]
        },
        "SDMA_Done": {
          "direction": "output",
          "bits": [ 69, 70, 71, 72 ]
        },
        "SDMA_Active": {
          "direction": "output",
          "bits": [ 73, 74, 75, 76 ]
        },
        "FB_msg_out": {
          "direction": "input",
          "bits": [ 77, 78, 79, 80 ]
        },
        "FB_Int_Clr": {
          "direction": "input",
          "bits": [ 81, 82, 83, 84, 85, 86, 87, 88 ]
        },
        "FB_Start": {
          "direction": "output",
          "bits": [ 89 ]
        },
        "FB_Busy": {
          "direction": "input",
          "bits": [ 90 ]
        },
        "WB_RST": {
          "direction": "output",
          "bits": [ 91 ]
        },
        "Sys_PKfb_Rst": {
          "direction": "output",
          "bits": [ 92 ]
        },
        "Sys_Clk0": {
          "direction": "output",
          "bits": [ 93 ]
        },
        "Sys_Clk0_Rst": {
          "direction": "output",
          "bits": [ 94 ]
        },
        "Sys_Clk1": {
          "direction": "output",
          "bits": [ 95 ]
        },
        "Sys_Clk1_Rst": {
          "direction": "output",
          "bits": [ 96 ]
        },
        "Sys_Pclk": {
          "direction": "output",
          "bits": [ 97 ]
        },
        "Sys_Pclk_Rst": {
          "direction": "output",
          "bits": [ 98 ]
        },
        "Sys_PKfb_Clk": {
          "direction": "input",
          "bits": [ 99 ]
        },
        "FB_PKfbData": {
          "direction": "input",
          "bits": [ 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131 ]
        },
        "WBs_WR_DAT": {
          "direction": "output",
          "bits": [ 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163 ]
        },
        "FB_PKfbPush": {
          "direction": "input",
          "bits": [ 164, 165, 166, 167 ]
        },
        "FB_PKfbSOF": {
          "direction": "input",
          "bits": [ 168 ]
        },
        "FB_PKfbEOF": {
          "direction": "input",
          "bits": [ 169 ]
        },
        "Sensor_Int": {
          "direction": "output",
          "bits": [ 170, 171, 172, 173, 174, 175, 176, 177 ]
        },
        "FB_PKfbOverflow": {
          "direction": "output",
          "bits": [ 178 ]
        },
        "TimeStamp": {
          "direction": "output",
          "bits": [ 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202 ]
        },
        "Sys_PSel": {
          "direction": "input",
          "bits": [ 203 ]
        },
        "SPIm_Paddr": {
          "direction": "input",
          "bits": [ 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219 ]
        },
        "SPIm_PEnable": {
          "direction": "input",
          "bits": [ 220 ]
        },
        "SPIm_PWrite": {
          "direction": "input",
          "bits": [ 221 ]
        },
        "SPIm_PWdata": {
          "direction": "input",
          "bits": [ 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253 ]
        },
        "SPIm_PReady": {
          "direction": "output",
          "bits": [ 254 ]
        },
        "SPIm_PSlvErr": {
          "direction": "output",
          "bits": [ 255 ]
        },
        "SPIm_Prdata": {
          "direction": "output",
          "bits": [ 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287 ]
        },
        "Device_ID": {
          "direction": "input",
          "bits": [ 288, 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303 ]
        }
      },
      "cells": {
      },
      "netnames": {
        "Device_ID": {
          "hide_name": 0,
          "bits": [ 288, 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:45.17-45.26"
          }
        },
        "FB_Busy": {
          "hide_name": 0,
          "bits": [ 90 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:19.17-19.24"
          }
        },
        "FB_Int_Clr": {
          "hide_name": 0,
          "bits": [ 81, 82, 83, 84, 85, 86, 87, 88 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:17.17-17.27"
          }
        },
        "FB_PKfbData": {
          "hide_name": 0,
          "bits": [ 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:29.17-29.28"
          }
        },
        "FB_PKfbEOF": {
          "hide_name": 0,
          "bits": [ 169 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:33.17-33.27"
          }
        },
        "FB_PKfbOverflow": {
          "hide_name": 0,
          "bits": [ 178 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:35.17-35.32"
          }
        },
        "FB_PKfbPush": {
          "hide_name": 0,
          "bits": [ 164, 165, 166, 167 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:31.17-31.28"
          }
        },
        "FB_PKfbSOF": {
          "hide_name": 0,
          "bits": [ 168 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:32.17-32.27"
          }
        },
        "FB_Start": {
          "hide_name": 0,
          "bits": [ 89 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:18.17-18.25"
          }
        },
        "FB_msg_out": {
          "hide_name": 0,
          "bits": [ 77, 78, 79, 80 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:16.17-16.27"
          }
        },
        "SDMA_Active": {
          "hide_name": 0,
          "bits": [ 73, 74, 75, 76 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:15.17-15.28"
          }
        },
        "SDMA_Done": {
          "hide_name": 0,
          "bits": [ 69, 70, 71, 72 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:14.17-14.26"
          }
        },
        "SDMA_Req": {
          "hide_name": 0,
          "bits": [ 61, 62, 63, 64 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:12.17-12.25"
          }
        },
        "SDMA_Sreq": {
          "hide_name": 0,
          "bits": [ 65, 66, 67, 68 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:13.17-13.26"
          }
        },
        "SPIm_PEnable": {
          "hide_name": 0,
          "bits": [ 220 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:39.17-39.29"
          }
        },
        "SPIm_PReady": {
          "hide_name": 0,
          "bits": [ 254 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:42.17-42.28"
          }
        },
        "SPIm_PSlvErr": {
          "hide_name": 0,
          "bits": [ 255 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:43.17-43.29"
          }
        },
        "SPIm_PWdata": {
          "hide_name": 0,
          "bits": [ 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:41.17-41.28"
          }
        },
        "SPIm_PWrite": {
          "hide_name": 0,
          "bits": [ 221 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:40.17-40.28"
          }
        },
        "SPIm_Paddr": {
          "hide_name": 0,
          "bits": [ 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:38.17-38.27"
          }
        },
        "SPIm_Prdata": {
          "hide_name": 0,
          "bits": [ 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:44.17-44.28"
          }
        },
        "Sensor_Int": {
          "hide_name": 0,
          "bits": [ 170, 171, 172, 173, 174, 175, 176, 177 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:34.17-34.27"
          }
        },
        "Sys_Clk0": {
          "hide_name": 0,
          "bits": [ 93 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:22.17-22.25"
          }
        },
        "Sys_Clk0_Rst": {
          "hide_name": 0,
          "bits": [ 94 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:23.17-23.29"
          }
        },
        "Sys_Clk1": {
          "hide_name": 0,
          "bits": [ 95 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:24.17-24.25"
          }
        },
        "Sys_Clk1_Rst": {
          "hide_name": 0,
          "bits": [ 96 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:25.17-25.29"
          }
        },
        "Sys_PKfb_Clk": {
          "hide_name": 0,
          "bits": [ 99 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:28.17-28.29"
          }
        },
        "Sys_PKfb_Rst": {
          "hide_name": 0,
          "bits": [ 92 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:21.17-21.29"
          }
        },
        "Sys_PSel": {
          "hide_name": 0,
          "bits": [ 203 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:37.17-37.25"
          }
        },
        "Sys_Pclk": {
          "hide_name": 0,
          "bits": [ 97 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:26.17-26.25"
          }
        },
        "Sys_Pclk_Rst": {
          "hide_name": 0,
          "bits": [ 98 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:27.17-27.29"
          }
        },
        "TimeStamp": {
          "hide_name": 0,
          "bits": [ 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:36.17-36.26"
          }
        },
        "WB_CLK": {
          "hide_name": 0,
          "bits": [ 2 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:3.17-3.23"
          }
        },
        "WB_RST": {
          "hide_name": 0,
          "bits": [ 91 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:20.17-20.23"
          }
        },
        "WBs_ACK": {
          "hide_name": 0,
          "bits": [ 3 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:4.17-4.24"
          }
        },
        "WBs_ADR": {
          "hide_name": 0,
          "bits": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:11.17-11.24"
          }
        },
        "WBs_BYTE_STB": {
          "hide_name": 0,
          "bits": [ 36, 37, 38, 39 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:6.17-6.29"
          }
        },
        "WBs_CYC": {
          "hide_name": 0,
          "bits": [ 40 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:7.17-7.24"
          }
        },
        "WBs_RD": {
          "hide_name": 0,
          "bits": [ 42 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:9.17-9.23"
          }
        },
        "WBs_RD_DAT": {
          "hide_name": 0,
          "bits": [ 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:5.17-5.27"
          }
        },
        "WBs_STB": {
          "hide_name": 0,
          "bits": [ 43 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:10.17-10.24"
          }
        },
        "WBs_WE": {
          "hide_name": 0,
          "bits": [ 41 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:8.17-8.23"
          }
        },
        "WBs_WR_DAT": {
          "hide_name": 0,
          "bits": [ 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v:30.17-30.27"
          }
        }
      }
    }
  }
}
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmprqpdoda_ c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmpobluvpva Device_ID %co* o:* %i Device_ID %d']
stderr   =======================================================================
Warning: Selection "Device_ID" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmp3kike0m1 FB_Busy %co* o:* %i FB_Busy %d']
stderr   =======================================================================
Warning: Selection "FB_Busy" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmphij386n6 FB_Int_Clr %co* o:* %i FB_Int_Clr %d']
stderr   =======================================================================
Warning: Selection "FB_Int_Clr" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmp16wyxnrz FB_PKfbData %co* o:* %i FB_PKfbData %d']
stderr   =======================================================================
Warning: Selection "FB_PKfbData" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmp8iqk739p FB_PKfbEOF %co* o:* %i FB_PKfbEOF %d']
stderr   =======================================================================
Warning: Selection "FB_PKfbEOF" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmp2_d7uxn9 FB_PKfbOverflow %co* o:* %i FB_PKfbOverflow %d']
stderr   =======================================================================
Warning: Selection "FB_PKfbOverflow" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmpw13ffdzp FB_PKfbPush %co* o:* %i FB_PKfbPush %d']
stderr   =======================================================================
Warning: Selection "FB_PKfbPush" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmpotztg3fn FB_PKfbSOF %co* o:* %i FB_PKfbSOF %d']
stderr   =======================================================================
Warning: Selection "FB_PKfbSOF" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmp0m4bk0a7 FB_Start %co* o:* %i FB_Start %d']
stderr   =======================================================================
Warning: Selection "FB_Start" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmphvqkiy50 FB_msg_out %co* o:* %i FB_msg_out %d']
stderr   =======================================================================
Warning: Selection "FB_msg_out" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmpd9yf0ady SDMA_Active %co* o:* %i SDMA_Active %d']
stderr   =======================================================================
Warning: Selection "SDMA_Active" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmpy0fhi1hd SDMA_Done %co* o:* %i SDMA_Done %d']
stderr   =======================================================================
Warning: Selection "SDMA_Done" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmp0athm2j8 SDMA_Req %co* o:* %i SDMA_Req %d']
stderr   =======================================================================
Warning: Selection "SDMA_Req" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmpnx5jpwq0 SDMA_Sreq %co* o:* %i SDMA_Sreq %d']
stderr   =======================================================================
Warning: Selection "SDMA_Sreq" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmplwc_v4r3 SPIm_PEnable %co* o:* %i SPIm_PEnable %d']
stderr   =======================================================================
Warning: Selection "SPIm_PEnable" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmpr_d9ithi SPIm_PReady %co* o:* %i SPIm_PReady %d']
stderr   =======================================================================
Warning: Selection "SPIm_PReady" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmpbyjkx9j7 SPIm_PSlvErr %co* o:* %i SPIm_PSlvErr %d']
stderr   =======================================================================
Warning: Selection "SPIm_PSlvErr" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmpbnds5mo9 SPIm_PWdata %co* o:* %i SPIm_PWdata %d']
stderr   =======================================================================
Warning: Selection "SPIm_PWdata" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmpfhul2_d_ SPIm_PWrite %co* o:* %i SPIm_PWrite %d']
stderr   =======================================================================
Warning: Selection "SPIm_PWrite" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmp5k6i4hv8 SPIm_Paddr %co* o:* %i SPIm_Paddr %d']
stderr   =======================================================================
Warning: Selection "SPIm_Paddr" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmpxoi_nbu6 SPIm_Prdata %co* o:* %i SPIm_Prdata %d']
stderr   =======================================================================
Warning: Selection "SPIm_Prdata" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmp0ekuubjw Sensor_Int %co* o:* %i Sensor_Int %d']
stderr   =======================================================================
Warning: Selection "Sensor_Int" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmpe9v_j069 Sys_Clk0 %co* o:* %i Sys_Clk0 %d']
stderr   =======================================================================
Warning: Selection "Sys_Clk0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmptz77a6hz Sys_Clk0_Rst %co* o:* %i Sys_Clk0_Rst %d']
stderr   =======================================================================
Warning: Selection "Sys_Clk0_Rst" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmp2yvxjk0h Sys_Clk1 %co* o:* %i Sys_Clk1 %d']
stderr   =======================================================================
Warning: Selection "Sys_Clk1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmpjeplohyr Sys_Clk1_Rst %co* o:* %i Sys_Clk1_Rst %d']
stderr   =======================================================================
Warning: Selection "Sys_Clk1_Rst" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmpashn49eo Sys_PKfb_Clk %co* o:* %i Sys_PKfb_Clk %d']
stderr   =======================================================================
Warning: Selection "Sys_PKfb_Clk" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmp80oro8bj Sys_PKfb_Rst %co* o:* %i Sys_PKfb_Rst %d']
stderr   =======================================================================
Warning: Selection "Sys_PKfb_Rst" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmp4kygdtg0 Sys_PSel %co* o:* %i Sys_PSel %d']
stderr   =======================================================================
Warning: Selection "Sys_PSel" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmpq0nm3c6a Sys_Pclk %co* o:* %i Sys_Pclk %d']
stderr   =======================================================================
Warning: Selection "Sys_Pclk" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmp908s0ui3 Sys_Pclk_Rst %co* o:* %i Sys_Pclk_Rst %d']
stderr   =======================================================================
Warning: Selection "Sys_Pclk_Rst" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmp1cs7hsld TimeStamp %co* o:* %i TimeStamp %d']
stderr   =======================================================================
Warning: Selection "TimeStamp" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmpde71mhv6 WB_CLK %co* o:* %i WB_CLK %d']
stderr   =======================================================================
Warning: Selection "WB_CLK" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmpd969nfh9 WB_RST %co* o:* %i WB_RST %d']
stderr   =======================================================================
Warning: Selection "WB_RST" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmplvlrtoif WBs_ACK %co* o:* %i WBs_ACK %d']
stderr   =======================================================================
Warning: Selection "WBs_ACK" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmp8std241r WBs_ADR %co* o:* %i WBs_ADR %d']
stderr   =======================================================================
Warning: Selection "WBs_ADR" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmpph1dlef5 WBs_BYTE_STB %co* o:* %i WBs_BYTE_STB %d']
stderr   =======================================================================
Warning: Selection "WBs_BYTE_STB" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmpndkgphd3 WBs_CYC %co* o:* %i WBs_CYC %d']
stderr   =======================================================================
Warning: Selection "WBs_CYC" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmp0fev9f9x WBs_RD %co* o:* %i WBs_RD %d']
stderr   =======================================================================
Warning: Selection "WBs_RD" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmpzc5eb3t3 WBs_RD_DAT %co* o:* %i WBs_RD_DAT %d']
stderr   =======================================================================
Warning: Selection "WBs_RD_DAT" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmpcviagi0m WBs_STB %co* o:* %i WBs_STB %d']
stderr   =======================================================================
Warning: Selection "WBs_STB" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmpvmf8g0d1 WBs_WE %co* o:* %i WBs_WE %d']
stderr   =======================================================================
Warning: Selection "WBs_WE" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/assp/assp.sim.v; proc; cd ASSP; select -write /tmp/tmp6kk98aku WBs_WR_DAT %co* o:* %i WBs_WR_DAT %d']
stderr   =======================================================================
Warning: Selection "WBs_WR_DAT" did not match any object.
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Built target file_quicklogic_primitives_assp_assp.model.xml
make -f quicklogic/primitives/ram/CMakeFiles/file_quicklogic_primitives_ram_ram.sim.v.dir/build.make quicklogic/primitives/ram/CMakeFiles/file_quicklogic_primitives_ram_ram.sim.v.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/ram /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/CMakeFiles/file_quicklogic_primitives_ram_ram.sim.v.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/ram/CMakeFiles/file_quicklogic_primitives_ram_ram.sim.v.dir/build.make quicklogic/primitives/ram/CMakeFiles/file_quicklogic_primitives_ram_ram.sim.v.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Generating ram.sim.v
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram && /usr/bin/cmake -E create_symlink /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/ram/ram.sim.v /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Built target file_quicklogic_primitives_ram_ram.sim.v
make -f quicklogic/primitives/ram/CMakeFiles/file_quicklogic_primitives_ram_ram.pb_type.xml.dir/build.make quicklogic/primitives/ram/CMakeFiles/file_quicklogic_primitives_ram_ram.pb_type.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/ram /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/CMakeFiles/file_quicklogic_primitives_ram_ram.pb_type.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/ram/CMakeFiles/file_quicklogic_primitives_ram_ram.pb_type.xml.dir/build.make quicklogic/primitives/ram/CMakeFiles/file_quicklogic_primitives_ram_ram.pb_type.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Generating ram.pb_type.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=pb_type -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.pb_type.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; prep ; write_json ']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "RAM": {
      "attributes": {
        "blackbox": "00000000000000000000000000000001",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:2.1-32.10"
      },
      "ports": {
        "A1_0": {
          "direction": "input",
          "bits": [ 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 ]
        },
        "A1_1": {
          "direction": "input",
          "bits": [ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 ]
        },
        "A2_0": {
          "direction": "input",
          "bits": [ 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 ]
        },
        "A2_1": {
          "direction": "input",
          "bits": [ 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45 ]
        },
        "CLK1_0": {
          "direction": "input",
          "bits": [ 46 ]
        },
        "CLK1_1": {
          "direction": "input",
          "bits": [ 47 ]
        },
        "Almost_Empty_0": {
          "direction": "output",
          "bits": [ 48 ]
        },
        "Almost_Empty_1": {
          "direction": "output",
          "bits": [ 49 ]
        },
        "Almost_Full_0": {
          "direction": "output",
          "bits": [ 50 ]
        },
        "Almost_Full_1": {
          "direction": "output",
          "bits": [ 51 ]
        },
        "ASYNC_FLUSH_0": {
          "direction": "input",
          "bits": [ 52 ]
        },
        "ASYNC_FLUSH_1": {
          "direction": "input",
          "bits": [ 53 ]
        },
        "CLK2_0": {
          "direction": "input",
          "bits": [ 54 ]
        },
        "CLK2_1": {
          "direction": "input",
          "bits": [ 55 ]
        },
        "CLK1EN_0": {
          "direction": "input",
          "bits": [ 56 ]
        },
        "CLK1EN_1": {
          "direction": "input",
          "bits": [ 57 ]
        },
        "CLK2EN_0": {
          "direction": "input",
          "bits": [ 58 ]
        },
        "CLK2EN_1": {
          "direction": "input",
          "bits": [ 59 ]
        },
        "CONCAT_EN_0": {
          "direction": "input",
          "bits": [ 60 ]
        },
        "CONCAT_EN_1": {
          "direction": "input",
          "bits": [ 61 ]
        },
        "CS1_0": {
          "direction": "input",
          "bits": [ 62 ]
        },
        "CS1_1": {
          "direction": "input",
          "bits": [ 63 ]
        },
        "CS2_0": {
          "direction": "input",
          "bits": [ 64 ]
        },
        "CS2_1": {
          "direction": "input",
          "bits": [ 65 ]
        },
        "DIR_0": {
          "direction": "input",
          "bits": [ 66 ]
        },
        "DIR_1": {
          "direction": "input",
          "bits": [ 67 ]
        },
        "FIFO_EN_0": {
          "direction": "input",
          "bits": [ 68 ]
        },
        "FIFO_EN_1": {
          "direction": "input",
          "bits": [ 69 ]
        },
        "P1_0": {
          "direction": "input",
          "bits": [ 70 ]
        },
        "P1_1": {
          "direction": "input",
          "bits": [ 71 ]
        },
        "P2_0": {
          "direction": "input",
          "bits": [ 72 ]
        },
        "P2_1": {
          "direction": "input",
          "bits": [ 73 ]
        },
        "PIPELINE_RD_0": {
          "direction": "input",
          "bits": [ 74 ]
        },
        "PIPELINE_RD_1": {
          "direction": "input",
          "bits": [ 75 ]
        },
        "POP_FLAG_0": {
          "direction": "output",
          "bits": [ 76, 77, 78, 79 ]
        },
        "POP_FLAG_1": {
          "direction": "output",
          "bits": [ 80, 81, 82, 83 ]
        },
        "PUSH_FLAG_0": {
          "direction": "output",
          "bits": [ 84, 85, 86, 87 ]
        },
        "PUSH_FLAG_1": {
          "direction": "output",
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}
exitcode =======================================================================
0
================================================================================

is_blackbox True has_modes? False
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog -DPB_TYPE  /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpxqaoc52j c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Built target file_quicklogic_primitives_ram_ram.pb_type.xml
make -f quicklogic/primitives/ram/CMakeFiles/file_quicklogic_primitives_ram_ram.model.xml.dir/build.make quicklogic/primitives/ram/CMakeFiles/file_quicklogic_primitives_ram_ram.model.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/ram /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/CMakeFiles/file_quicklogic_primitives_ram_ram.model.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/ram/CMakeFiles/file_quicklogic_primitives_ram_ram.model.xml.dir/build.make quicklogic/primitives/ram/CMakeFiles/file_quicklogic_primitives_ram_ram.model.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Generating ram.model.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=model -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.model.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; prep -flatten; write_json -aig']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "RAM": {
      "attributes": {
        "blackbox": "00000000000000000000000000000001",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:2.1-32.10"
      },
      "ports": {
        "A1_0": {
          "direction": "input",
          "bits": [ 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 ]
        },
        "A1_1": {
          "direction": "input",
          "bits": [ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 ]
        },
        "A2_0": {
          "direction": "input",
          "bits": [ 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 ]
        },
        "A2_1": {
          "direction": "input",
          "bits": [ 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45 ]
        },
        "CLK1_0": {
          "direction": "input",
          "bits": [ 46 ]
        },
        "CLK1_1": {
          "direction": "input",
          "bits": [ 47 ]
        },
        "Almost_Empty_0": {
          "direction": "output",
          "bits": [ 48 ]
        },
        "Almost_Empty_1": {
          "direction": "output",
          "bits": [ 49 ]
        },
        "Almost_Full_0": {
          "direction": "output",
          "bits": [ 50 ]
        },
        "Almost_Full_1": {
          "direction": "output",
          "bits": [ 51 ]
        },
        "ASYNC_FLUSH_0": {
          "direction": "input",
          "bits": [ 52 ]
        },
        "ASYNC_FLUSH_1": {
          "direction": "input",
          "bits": [ 53 ]
        },
        "CLK2_0": {
          "direction": "input",
          "bits": [ 54 ]
        },
        "CLK2_1": {
          "direction": "input",
          "bits": [ 55 ]
        },
        "CLK1EN_0": {
          "direction": "input",
          "bits": [ 56 ]
        },
        "CLK1EN_1": {
          "direction": "input",
          "bits": [ 57 ]
        },
        "CLK2EN_0": {
          "direction": "input",
          "bits": [ 58 ]
        },
        "CLK2EN_1": {
          "direction": "input",
          "bits": [ 59 ]
        },
        "CONCAT_EN_0": {
          "direction": "input",
          "bits": [ 60 ]
        },
        "CONCAT_EN_1": {
          "direction": "input",
          "bits": [ 61 ]
        },
        "CS1_0": {
          "direction": "input",
          "bits": [ 62 ]
        },
        "CS1_1": {
          "direction": "input",
          "bits": [ 63 ]
        },
        "CS2_0": {
          "direction": "input",
          "bits": [ 64 ]
        },
        "CS2_1": {
          "direction": "input",
          "bits": [ 65 ]
        },
        "DIR_0": {
          "direction": "input",
          "bits": [ 66 ]
        },
        "DIR_1": {
          "direction": "input",
          "bits": [ 67 ]
        },
        "FIFO_EN_0": {
          "direction": "input",
          "bits": [ 68 ]
        },
        "FIFO_EN_1": {
          "direction": "input",
          "bits": [ 69 ]
        },
        "P1_0": {
          "direction": "input",
          "bits": [ 70 ]
        },
        "P1_1": {
          "direction": "input",
          "bits": [ 71 ]
        },
        "P2_0": {
          "direction": "input",
          "bits": [ 72 ]
        },
        "P2_1": {
          "direction": "input",
          "bits": [ 73 ]
        },
        "PIPELINE_RD_0": {
          "direction": "input",
          "bits": [ 74 ]
        },
        "PIPELINE_RD_1": {
          "direction": "input",
          "bits": [ 75 ]
        },
        "POP_FLAG_0": {
          "direction": "output",
          "bits": [ 76, 77, 78, 79 ]
        },
        "POP_FLAG_1": {
          "direction": "output",
          "bits": [ 80, 81, 82, 83 ]
        },
        "PUSH_FLAG_0": {
          "direction": "output",
          "bits": [ 84, 85, 86, 87 ]
        },
        "PUSH_FLAG_1": {
          "direction": "output",
          "bits": [ 88, 89, 90, 91 ]
        },
        "RD_0": {
          "direction": "output",
          "bits": [ 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109 ]
        },
        "RD_1": {
          "direction": "output",
          "bits": [ 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127 ]
        },
        "SYNC_FIFO_0": {
          "direction": "input",
          "bits": [ 128 ]
        },
        "SYNC_FIFO_1": {
          "direction": "input",
          "bits": [ 129 ]
        },
        "WD_0": {
          "direction": "input",
          "bits": [ 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147 ]
        },
        "WD_1": {
          "direction": "input",
          "bits": [ 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165 ]
        },
        "WEN1_0": {
          "direction": "input",
          "bits": [ 166, 167 ]
        },
        "WEN1_1": {
          "direction": "input",
          "bits": [ 168, 169 ]
        },
        "WIDTH_SELECT1_0": {
          "direction": "input",
          "bits": [ 170, 171 ]
        },
        "WIDTH_SELECT1_1": {
          "direction": "input",
          "bits": [ 172, 173 ]
        },
        "WIDTH_SELECT2_0": {
          "direction": "input",
          "bits": [ 174, 175 ]
        },
        "WIDTH_SELECT2_1": {
          "direction": "input",
          "bits": [ 176, 177 ]
        },
        "SD": {
          "direction": "input",
          "bits": [ 178 ]
        },
        "DS": {
          "direction": "input",
          "bits": [ 179 ]
        },
        "LS": {
          "direction": "input",
          "bits": [ 180 ]
        },
        "SD_RB1": {
          "direction": "input",
          "bits": [ 181 ]
        },
        "LS_RB1": {
          "direction": "input",
          "bits": [ 182 ]
        },
        "DS_RB1": {
          "direction": "input",
          "bits": [ 183 ]
        },
        "RMEA": {
          "direction": "input",
          "bits": [ 184 ]
        },
        "RMEB": {
          "direction": "input",
          "bits": [ 185 ]
        },
        "RMA": {
          "direction": "input",
          "bits": [ 186, 187, 188, 189 ]
        },
        "RMB": {
          "direction": "input",
          "bits": [ 190, 191, 192, 193 ]
        },
        "TEST1A": {
          "direction": "input",
          "bits": [ 194 ]
        },
        "TEST1B": {
          "direction": "input",
          "bits": [ 195 ]
        }
      },
      "cells": {
      },
      "netnames": {
        "A1_0": {
          "hide_name": 0,
          "bits": [ 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 ],
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            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:3.18-3.22"
          }
        },
        "A1_1": {
          "hide_name": 0,
          "bits": [ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:4.18-4.22"
          }
        },
        "A2_0": {
          "hide_name": 0,
          "bits": [ 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:5.18-5.22"
          }
        },
        "A2_1": {
          "hide_name": 0,
          "bits": [ 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:6.18-6.22"
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        },
        "ASYNC_FLUSH_0": {
          "hide_name": 0,
          "bits": [ 52 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:10.11-10.24"
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        },
        "ASYNC_FLUSH_1": {
          "hide_name": 0,
          "bits": [ 53 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:10.26-10.39"
          }
        },
        "Almost_Empty_0": {
          "hide_name": 0,
          "bits": [ 48 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:9.12-9.26"
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        },
        "Almost_Empty_1": {
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          "bits": [ 49 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:9.28-9.42"
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        "Almost_Full_0": {
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            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:9.44-9.57"
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        "CLK1_1": {
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        "PUSH_FLAG_1": {
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        "RD_0": {
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        "RD_1": {
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        "RMB": {
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            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:28.17-28.20"
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            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:26.41-26.45"
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        "RMEB": {
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        "SD": {
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        "SD_RB1": {
          "hide_name": 0,
          "bits": [ 181 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:26.20-26.26"
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        "SYNC_FIFO_0": {
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          "bits": [ 128 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:17.12-17.23"
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        "SYNC_FIFO_1": {
          "hide_name": 0,
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          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:17.25-17.36"
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        },
        "TEST1A": {
          "hide_name": 0,
          "bits": [ 194 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:29.11-29.17"
          }
        },
        "TEST1B": {
          "hide_name": 0,
          "bits": [ 195 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:29.19-29.25"
          }
        },
        "WD_0": {
          "hide_name": 0,
          "bits": [ 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:18.18-18.22"
          }
        },
        "WD_1": {
          "hide_name": 0,
          "bits": [ 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:19.18-19.22"
          }
        },
        "WEN1_0": {
          "hide_name": 0,
          "bits": [ 166, 167 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:20.17-20.23"
          }
        },
        "WEN1_1": {
          "hide_name": 0,
          "bits": [ 168, 169 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:21.17-21.23"
          }
        },
        "WIDTH_SELECT1_0": {
          "hide_name": 0,
          "bits": [ 170, 171 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:22.17-22.32"
          }
        },
        "WIDTH_SELECT1_1": {
          "hide_name": 0,
          "bits": [ 172, 173 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:23.17-23.32"
          }
        },
        "WIDTH_SELECT2_0": {
          "hide_name": 0,
          "bits": [ 174, 175 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:24.17-24.32"
          }
        },
        "WIDTH_SELECT2_1": {
          "hide_name": 0,
          "bits": [ 176, 177 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v:25.17-25.32"
          }
        }
      }
    }
  }
}
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpqic_b0q8 c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmprkucpmhi A1_0 %co* o:* %i A1_0 %d']
stderr   =======================================================================
Warning: Selection "A1_0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpl65_qq0b A1_1 %co* o:* %i A1_1 %d']
stderr   =======================================================================
Warning: Selection "A1_1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmp91lse7zp A2_0 %co* o:* %i A2_0 %d']
stderr   =======================================================================
Warning: Selection "A2_0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpt3aczgnw A2_1 %co* o:* %i A2_1 %d']
stderr   =======================================================================
Warning: Selection "A2_1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmp1jtw1weo ASYNC_FLUSH_0 %co* o:* %i ASYNC_FLUSH_0 %d']
stderr   =======================================================================
Warning: Selection "ASYNC_FLUSH_0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmph8ipn1v_ ASYNC_FLUSH_1 %co* o:* %i ASYNC_FLUSH_1 %d']
stderr   =======================================================================
Warning: Selection "ASYNC_FLUSH_1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmp9qwezjkh Almost_Empty_0 %co* o:* %i Almost_Empty_0 %d']
stderr   =======================================================================
Warning: Selection "Almost_Empty_0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpno14gixj Almost_Empty_1 %co* o:* %i Almost_Empty_1 %d']
stderr   =======================================================================
Warning: Selection "Almost_Empty_1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpu5hol3x8 Almost_Full_0 %co* o:* %i Almost_Full_0 %d']
stderr   =======================================================================
Warning: Selection "Almost_Full_0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmp2590p_iv Almost_Full_1 %co* o:* %i Almost_Full_1 %d']
stderr   =======================================================================
Warning: Selection "Almost_Full_1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpi62npns7 CLK1EN_0 %co* o:* %i CLK1EN_0 %d']
stderr   =======================================================================
Warning: Selection "CLK1EN_0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmphkivkr4d CLK1EN_1 %co* o:* %i CLK1EN_1 %d']
stderr   =======================================================================
Warning: Selection "CLK1EN_1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmppsfaovct CLK1_0 %co* o:* %i CLK1_0 %d']
stderr   =======================================================================
Warning: Selection "CLK1_0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpv04xrx5b CLK1_1 %co* o:* %i CLK1_1 %d']
stderr   =======================================================================
Warning: Selection "CLK1_1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpnn_l8qi9 CLK2EN_0 %co* o:* %i CLK2EN_0 %d']
stderr   =======================================================================
Warning: Selection "CLK2EN_0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpg1en1n8x CLK2EN_1 %co* o:* %i CLK2EN_1 %d']
stderr   =======================================================================
Warning: Selection "CLK2EN_1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmp9gipi9vf CLK2_0 %co* o:* %i CLK2_0 %d']
stderr   =======================================================================
Warning: Selection "CLK2_0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpayk9azj1 CLK2_1 %co* o:* %i CLK2_1 %d']
stderr   =======================================================================
Warning: Selection "CLK2_1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmp49e7sye3 CONCAT_EN_0 %co* o:* %i CONCAT_EN_0 %d']
stderr   =======================================================================
Warning: Selection "CONCAT_EN_0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpma0_5jss CONCAT_EN_1 %co* o:* %i CONCAT_EN_1 %d']
stderr   =======================================================================
Warning: Selection "CONCAT_EN_1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpx1_vg_ef CS1_0 %co* o:* %i CS1_0 %d']
stderr   =======================================================================
Warning: Selection "CS1_0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpdkmaxk34 CS1_1 %co* o:* %i CS1_1 %d']
stderr   =======================================================================
Warning: Selection "CS1_1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmp_af2gsya CS2_0 %co* o:* %i CS2_0 %d']
stderr   =======================================================================
Warning: Selection "CS2_0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpooe29nb0 CS2_1 %co* o:* %i CS2_1 %d']
stderr   =======================================================================
Warning: Selection "CS2_1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmp47vwq2_4 DIR_0 %co* o:* %i DIR_0 %d']
stderr   =======================================================================
Warning: Selection "DIR_0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmp4en9g4m3 DIR_1 %co* o:* %i DIR_1 %d']
stderr   =======================================================================
Warning: Selection "DIR_1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmp8lza05qr DS %co* o:* %i DS %d']
stderr   =======================================================================
Warning: Selection "DS" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmprdoadeid DS_RB1 %co* o:* %i DS_RB1 %d']
stderr   =======================================================================
Warning: Selection "DS_RB1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmp7kxd9x92 FIFO_EN_0 %co* o:* %i FIFO_EN_0 %d']
stderr   =======================================================================
Warning: Selection "FIFO_EN_0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpu3xrn43j FIFO_EN_1 %co* o:* %i FIFO_EN_1 %d']
stderr   =======================================================================
Warning: Selection "FIFO_EN_1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmp8k8g65n9 LS %co* o:* %i LS %d']
stderr   =======================================================================
Warning: Selection "LS" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpitbqy0va LS_RB1 %co* o:* %i LS_RB1 %d']
stderr   =======================================================================
Warning: Selection "LS_RB1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpegkx8yq9 P1_0 %co* o:* %i P1_0 %d']
stderr   =======================================================================
Warning: Selection "P1_0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmp4k7y2qe1 P1_1 %co* o:* %i P1_1 %d']
stderr   =======================================================================
Warning: Selection "P1_1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmp5pg_bcju P2_0 %co* o:* %i P2_0 %d']
stderr   =======================================================================
Warning: Selection "P2_0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmp66joae8k P2_1 %co* o:* %i P2_1 %d']
stderr   =======================================================================
Warning: Selection "P2_1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpreavevwy PIPELINE_RD_0 %co* o:* %i PIPELINE_RD_0 %d']
stderr   =======================================================================
Warning: Selection "PIPELINE_RD_0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmp8s3zdz_0 PIPELINE_RD_1 %co* o:* %i PIPELINE_RD_1 %d']
stderr   =======================================================================
Warning: Selection "PIPELINE_RD_1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmprvh0h476 POP_FLAG_0 %co* o:* %i POP_FLAG_0 %d']
stderr   =======================================================================
Warning: Selection "POP_FLAG_0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmptk30cy9b POP_FLAG_1 %co* o:* %i POP_FLAG_1 %d']
stderr   =======================================================================
Warning: Selection "POP_FLAG_1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpm32bqt28 PUSH_FLAG_0 %co* o:* %i PUSH_FLAG_0 %d']
stderr   =======================================================================
Warning: Selection "PUSH_FLAG_0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpci0eyusp PUSH_FLAG_1 %co* o:* %i PUSH_FLAG_1 %d']
stderr   =======================================================================
Warning: Selection "PUSH_FLAG_1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmp3face2a1 RD_0 %co* o:* %i RD_0 %d']
stderr   =======================================================================
Warning: Selection "RD_0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmphyu4j83c RD_1 %co* o:* %i RD_1 %d']
stderr   =======================================================================
Warning: Selection "RD_1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpu5kad2ra RMA %co* o:* %i RMA %d']
stderr   =======================================================================
Warning: Selection "RMA" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmp9iz_pi84 RMB %co* o:* %i RMB %d']
stderr   =======================================================================
Warning: Selection "RMB" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmp_spt0dkd RMEA %co* o:* %i RMEA %d']
stderr   =======================================================================
Warning: Selection "RMEA" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpqxbzzvnh RMEB %co* o:* %i RMEB %d']
stderr   =======================================================================
Warning: Selection "RMEB" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmp6rokm6n9 SD %co* o:* %i SD %d']
stderr   =======================================================================
Warning: Selection "SD" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpzn7nqcdo SD_RB1 %co* o:* %i SD_RB1 %d']
stderr   =======================================================================
Warning: Selection "SD_RB1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpvi1fyniu SYNC_FIFO_0 %co* o:* %i SYNC_FIFO_0 %d']
stderr   =======================================================================
Warning: Selection "SYNC_FIFO_0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpksn_8xa3 SYNC_FIFO_1 %co* o:* %i SYNC_FIFO_1 %d']
stderr   =======================================================================
Warning: Selection "SYNC_FIFO_1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpvk2707xv TEST1A %co* o:* %i TEST1A %d']
stderr   =======================================================================
Warning: Selection "TEST1A" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmp1_kjjcbm TEST1B %co* o:* %i TEST1B %d']
stderr   =======================================================================
Warning: Selection "TEST1B" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpic5lbim6 WD_0 %co* o:* %i WD_0 %d']
stderr   =======================================================================
Warning: Selection "WD_0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpg5ww7b0c WD_1 %co* o:* %i WD_1 %d']
stderr   =======================================================================
Warning: Selection "WD_1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpt5c9scbq WEN1_0 %co* o:* %i WEN1_0 %d']
stderr   =======================================================================
Warning: Selection "WEN1_0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmphvls6d1c WEN1_1 %co* o:* %i WEN1_1 %d']
stderr   =======================================================================
Warning: Selection "WEN1_1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmp_ksz8_2b WIDTH_SELECT1_0 %co* o:* %i WIDTH_SELECT1_0 %d']
stderr   =======================================================================
Warning: Selection "WIDTH_SELECT1_0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmptyc2hptj WIDTH_SELECT1_1 %co* o:* %i WIDTH_SELECT1_1 %d']
stderr   =======================================================================
Warning: Selection "WIDTH_SELECT1_1" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpwpl9w8c5 WIDTH_SELECT2_0 %co* o:* %i WIDTH_SELECT2_0 %d']
stderr   =======================================================================
Warning: Selection "WIDTH_SELECT2_0" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/ram/ram.sim.v; proc; cd RAM; select -write /tmp/tmpivbdx9r6 WIDTH_SELECT2_1 %co* o:* %i WIDTH_SELECT2_1 %d']
stderr   =======================================================================
Warning: Selection "WIDTH_SELECT2_1" did not match any object.
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Built target file_quicklogic_primitives_ram_ram.model.xml
make -f quicklogic/primitives/mult/CMakeFiles/file_quicklogic_primitives_mult_mult.model.xml.dir/build.make quicklogic/primitives/mult/CMakeFiles/file_quicklogic_primitives_mult_mult.model.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/primitives/mult /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/CMakeFiles/file_quicklogic_primitives_mult_mult.model.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/primitives/mult/CMakeFiles/file_quicklogic_primitives_mult_mult.model.xml.dir/build.make quicklogic/primitives/mult/CMakeFiles/file_quicklogic_primitives_mult_mult.model.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Generating mult.model.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x/v2x && /usr/bin/cmake -E env YOSYS=/opt/openfpga/bin/yosys PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-symbiflow-v2x:/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/env/conda/lib/python3.7/site-packages /opt/openfpga/vtr/_pyenv/bin/python3 -m v2x --mode=model -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.model.xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v
command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v; prep -flatten; write_json -aig']
stdout   =======================================================================
{
  "creator": "Yosys 0.9+2406 (git sha1 4a66ab39, gcc 9.2.0-r2 -fPIC -Os)",
  "modules": {
    "MULT": {
      "attributes": {
        "whitebox": "00000000000000000000000000000001",
        "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:2.1-36.10"
      },
      "ports": {
        "Amult": {
          "direction": "input",
          "bits": [ 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33 ]
        },
        "Bmult": {
          "direction": "input",
          "bits": [ 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65 ]
        },
        "Valid_mult": {
          "direction": "input",
          "bits": [ 66, 67 ]
        },
        "Cmult": {
          "direction": "output",
          "bits": [ 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131 ]
        },
        "sel_mul_32x32": {
          "direction": "input",
          "bits": [ 132 ]
        }
      },
      "cells": {
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:21$2": {
          "hide_name": 1,
          "type": "$eq",
          "model": "$eq:1U:1U:1",
          "parameters": {
            "A_SIGNED": "00000000000000000000000000000000",
            "A_WIDTH": "00000000000000000000000000000001",
            "B_SIGNED": "00000000000000000000000000000000",
            "B_WIDTH": "00000000000000000000000000000001",
            "Y_WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:21.7-21.28"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
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          },
          "connections": {
            "A": [ 132 ],
            "B": [ "1" ],
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          }
        },
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:22$3": {
          "hide_name": 1,
          "type": "$eq",
          "model": "$eq:1U:1U:1",
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          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:22.8-22.29"
          },
          "port_directions": {
            "A": "input",
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          },
          "connections": {
            "A": [ 66 ],
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        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:26$5": {
          "hide_name": 1,
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            "A": "input",
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            "A": [ 66 ],
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        },
        "$eq$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:29$7": {
          "hide_name": 1,
          "type": "$eq",
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          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:29.8-29.29"
          },
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            "A": "input",
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          "connections": {
            "A": [ 67 ],
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        },
        "$mul$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:23$4": {
          "hide_name": 1,
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          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:23.14-23.27"
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            "A": "input",
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            "B": [ 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65 ],
            "Y": [ 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200 ]
          }
        },
        "$mul$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:27$6": {
          "hide_name": 1,
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          "parameters": {
            "A_SIGNED": "00000000000000000000000000000000",
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            "B_SIGNED": "00000000000000000000000000000000",
            "B_WIDTH": "00000000000000000000000000010000",
            "Y_WIDTH": "00000000000000000000000000100000"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:27.20-27.45"
          },
          "port_directions": {
            "A": "input",
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          },
          "connections": {
            "A": [ 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 ],
            "B": [ 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49 ],
            "Y": [ 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232 ]
          }
        },
        "$mul$/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:30$8": {
          "hide_name": 1,
          "type": "$mul",
          "parameters": {
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          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:30.21-30.48"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
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          "connections": {
            "A": [ 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33 ],
            "B": [ 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65 ],
            "Y": [ 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264 ]
          }
        },
        "$procmux$12": {
          "hide_name": 1,
          "type": "$mux",
          "model": "$mux:32",
          "parameters": {
            "WIDTH": "00000000000000000000000000100000"
          },
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:22.8-22.29|/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:22.4-24.7"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131 ],
            "B": [ 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200 ],
            "S": [ 134 ],
            "Y": [ 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, 296 ]
          }
        },
        "$procmux$14": {
          "hide_name": 1,
          "type": "$mux",
          "model": "$mux:32",
          "parameters": {
            "WIDTH": "00000000000000000000000000100000"
          },
          "attributes": {
            "full_case": "00000000000000000000000000000001",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:21.7-21.28|/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:21.3-32.6"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
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{iopath_Amult3_Cmult60} {iopath_Amult3_Cmult61} {iopath_Amult3_Cmult62} {iopath_Amult3_Cmult63} 0 0 0 0 {iopath_Amult4_Cmult4} {iopath_Amult4_Cmult5} {iopath_Amult4_Cmult6} {iopath_Amult4_Cmult7} {iopath_Amult4_Cmult8} {iopath_Amult4_Cmult9} {iopath_Amult4_Cmult10} {iopath_Amult4_Cmult11} {iopath_Amult4_Cmult12} {iopath_Amult4_Cmult13} {iopath_Amult4_Cmult14} {iopath_Amult4_Cmult15} {iopath_Amult4_Cmult16} {iopath_Amult4_Cmult17} {iopath_Amult4_Cmult18} {iopath_Amult4_Cmult19} {iopath_Amult4_Cmult20} {iopath_Amult4_Cmult21} {iopath_Amult4_Cmult22} {iopath_Amult4_Cmult23} {iopath_Amult4_Cmult24} {iopath_Amult4_Cmult25} {iopath_Amult4_Cmult26} {iopath_Amult4_Cmult27} {iopath_Amult4_Cmult28} {iopath_Amult4_Cmult29} {iopath_Amult4_Cmult30} {iopath_Amult4_Cmult31} {iopath_Amult4_Cmult32} {iopath_Amult4_Cmult33} {iopath_Amult4_Cmult34} {iopath_Amult4_Cmult35} {iopath_Amult4_Cmult36} {iopath_Amult4_Cmult37} {iopath_Amult4_Cmult38} {iopath_Amult4_Cmult39} {iopath_Amult4_Cmult40} {iopath_Amult4_Cmult41} {iopath_Amult4_Cmult42} {iopath_Amult4_Cmult43} {iopath_Amult4_Cmult44} {iopath_Amult4_Cmult45} {iopath_Amult4_Cmult46} {iopath_Amult4_Cmult47} {iopath_Amult4_Cmult48} {iopath_Amult4_Cmult49} {iopath_Amult4_Cmult50} {iopath_Amult4_Cmult51} {iopath_Amult4_Cmult52} {iopath_Amult4_Cmult53} {iopath_Amult4_Cmult54} {iopath_Amult4_Cmult55} {iopath_Amult4_Cmult56} {iopath_Amult4_Cmult57} {iopath_Amult4_Cmult58} {iopath_Amult4_Cmult59} {iopath_Amult4_Cmult60} {iopath_Amult4_Cmult61} {iopath_Amult4_Cmult62} {iopath_Amult4_Cmult63} 0 0 0 0 0 {iopath_Amult5_Cmult5} {iopath_Amult5_Cmult6} {iopath_Amult5_Cmult7} {iopath_Amult5_Cmult8} {iopath_Amult5_Cmult9} {iopath_Amult5_Cmult10} {iopath_Amult5_Cmult11} {iopath_Amult5_Cmult12} {iopath_Amult5_Cmult13} {iopath_Amult5_Cmult14} {iopath_Amult5_Cmult15} {iopath_Amult5_Cmult16} {iopath_Amult5_Cmult17} {iopath_Amult5_Cmult18} {iopath_Amult5_Cmult19} {iopath_Amult5_Cmult20} {iopath_Amult5_Cmult21} {iopath_Amult5_Cmult22} {iopath_Amult5_Cmult23} {iopath_Amult5_Cmult24} {iopath_Amult5_Cmult25} {iopath_Amult5_Cmult26} {iopath_Amult5_Cmult27} {iopath_Amult5_Cmult28} {iopath_Amult5_Cmult29} {iopath_Amult5_Cmult30} {iopath_Amult5_Cmult31} {iopath_Amult5_Cmult32} {iopath_Amult5_Cmult33} {iopath_Amult5_Cmult34} {iopath_Amult5_Cmult35} {iopath_Amult5_Cmult36} {iopath_Amult5_Cmult37} {iopath_Amult5_Cmult38} {iopath_Amult5_Cmult39} {iopath_Amult5_Cmult40} {iopath_Amult5_Cmult41} {iopath_Amult5_Cmult42} {iopath_Amult5_Cmult43} {iopath_Amult5_Cmult44} {iopath_Amult5_Cmult45} {iopath_Amult5_Cmult46} {iopath_Amult5_Cmult47} {iopath_Amult5_Cmult48} {iopath_Amult5_Cmult49} {iopath_Amult5_Cmult50} {iopath_Amult5_Cmult51} {iopath_Amult5_Cmult52} {iopath_Amult5_Cmult53} {iopath_Amult5_Cmult54} {iopath_Amult5_Cmult55} {iopath_Amult5_Cmult56} {iopath_Amult5_Cmult57} {iopath_Amult5_Cmult58} {iopath_Amult5_Cmult59} {iopath_Amult5_Cmult60} {iopath_Amult5_Cmult61} {iopath_Amult5_Cmult62} {iopath_Amult5_Cmult63} 0 0 0 0 0 0 {iopath_Amult6_Cmult6} {iopath_Amult6_Cmult7} {iopath_Amult6_Cmult8} {iopath_Amult6_Cmult9} {iopath_Amult6_Cmult10} {iopath_Amult6_Cmult11} {iopath_Amult6_Cmult12} {iopath_Amult6_Cmult13} {iopath_Amult6_Cmult14} {iopath_Amult6_Cmult15} {iopath_Amult6_Cmult16} {iopath_Amult6_Cmult17} {iopath_Amult6_Cmult18} {iopath_Amult6_Cmult19} {iopath_Amult6_Cmult20} {iopath_Amult6_Cmult21} {iopath_Amult6_Cmult22} {iopath_Amult6_Cmult23} {iopath_Amult6_Cmult24} {iopath_Amult6_Cmult25} {iopath_Amult6_Cmult26} {iopath_Amult6_Cmult27} {iopath_Amult6_Cmult28} {iopath_Amult6_Cmult29} {iopath_Amult6_Cmult30} {iopath_Amult6_Cmult31} {iopath_Amult6_Cmult32} {iopath_Amult6_Cmult33} {iopath_Amult6_Cmult34} {iopath_Amult6_Cmult35} {iopath_Amult6_Cmult36} {iopath_Amult6_Cmult37} {iopath_Amult6_Cmult38} {iopath_Amult6_Cmult39} {iopath_Amult6_Cmult40} {iopath_Amult6_Cmult41} {iopath_Amult6_Cmult42} {iopath_Amult6_Cmult43} {iopath_Amult6_Cmult44} {iopath_Amult6_Cmult45} {iopath_Amult6_Cmult46} {iopath_Amult6_Cmult47} {iopath_Amult6_Cmult48} {iopath_Amult6_Cmult49} {iopath_Amult6_Cmult50} {iopath_Amult6_Cmult51} {iopath_Amult6_Cmult52} {iopath_Amult6_Cmult53} {iopath_Amult6_Cmult54} {iopath_Amult6_Cmult55} {iopath_Amult6_Cmult56} {iopath_Amult6_Cmult57} {iopath_Amult6_Cmult58} {iopath_Amult6_Cmult59} {iopath_Amult6_Cmult60} {iopath_Amult6_Cmult61} {iopath_Amult6_Cmult62} {iopath_Amult6_Cmult63} 0 0 0 0 0 0 0 {iopath_Amult7_Cmult7} {iopath_Amult7_Cmult8} {iopath_Amult7_Cmult9} {iopath_Amult7_Cmult10} {iopath_Amult7_Cmult11} {iopath_Amult7_Cmult12} {iopath_Amult7_Cmult13} {iopath_Amult7_Cmult14} {iopath_Amult7_Cmult15} {iopath_Amult7_Cmult16} {iopath_Amult7_Cmult17} {iopath_Amult7_Cmult18} {iopath_Amult7_Cmult19} {iopath_Amult7_Cmult20} {iopath_Amult7_Cmult21} {iopath_Amult7_Cmult22} {iopath_Amult7_Cmult23} {iopath_Amult7_Cmult24} {iopath_Amult7_Cmult25} {iopath_Amult7_Cmult26} {iopath_Amult7_Cmult27} {iopath_Amult7_Cmult28} {iopath_Amult7_Cmult29} {iopath_Amult7_Cmult30} {iopath_Amult7_Cmult31} {iopath_Amult7_Cmult32} {iopath_Amult7_Cmult33} {iopath_Amult7_Cmult34} {iopath_Amult7_Cmult35} {iopath_Amult7_Cmult36} {iopath_Amult7_Cmult37} {iopath_Amult7_Cmult38} {iopath_Amult7_Cmult39} {iopath_Amult7_Cmult40} {iopath_Amult7_Cmult41} {iopath_Amult7_Cmult42} {iopath_Amult7_Cmult43} {iopath_Amult7_Cmult44} {iopath_Amult7_Cmult45} {iopath_Amult7_Cmult46} {iopath_Amult7_Cmult47} {iopath_Amult7_Cmult48} {iopath_Amult7_Cmult49} {iopath_Amult7_Cmult50} {iopath_Amult7_Cmult51} {iopath_Amult7_Cmult52} {iopath_Amult7_Cmult53} {iopath_Amult7_Cmult54} {iopath_Amult7_Cmult55} {iopath_Amult7_Cmult56} {iopath_Amult7_Cmult57} {iopath_Amult7_Cmult58} {iopath_Amult7_Cmult59} {iopath_Amult7_Cmult60} {iopath_Amult7_Cmult61} {iopath_Amult7_Cmult62} {iopath_Amult7_Cmult63} 0 0 0 0 0 0 0 0 {iopath_Amult8_Cmult8} {iopath_Amult8_Cmult9} {iopath_Amult8_Cmult10} {iopath_Amult8_Cmult11} {iopath_Amult8_Cmult12} {iopath_Amult8_Cmult13} {iopath_Amult8_Cmult14} {iopath_Amult8_Cmult15} {iopath_Amult8_Cmult16} {iopath_Amult8_Cmult17} {iopath_Amult8_Cmult18} {iopath_Amult8_Cmult19} {iopath_Amult8_Cmult20} {iopath_Amult8_Cmult21} {iopath_Amult8_Cmult22} {iopath_Amult8_Cmult23} {iopath_Amult8_Cmult24} {iopath_Amult8_Cmult25} {iopath_Amult8_Cmult26} {iopath_Amult8_Cmult27} {iopath_Amult8_Cmult28} {iopath_Amult8_Cmult29} {iopath_Amult8_Cmult30} {iopath_Amult8_Cmult31} {iopath_Amult8_Cmult32} {iopath_Amult8_Cmult33} {iopath_Amult8_Cmult34} {iopath_Amult8_Cmult35} {iopath_Amult8_Cmult36} {iopath_Amult8_Cmult37} {iopath_Amult8_Cmult38} {iopath_Amult8_Cmult39} {iopath_Amult8_Cmult40} {iopath_Amult8_Cmult41} {iopath_Amult8_Cmult42} {iopath_Amult8_Cmult43} {iopath_Amult8_Cmult44} {iopath_Amult8_Cmult45} {iopath_Amult8_Cmult46} {iopath_Amult8_Cmult47} {iopath_Amult8_Cmult48} {iopath_Amult8_Cmult49} {iopath_Amult8_Cmult50} {iopath_Amult8_Cmult51} {iopath_Amult8_Cmult52} {iopath_Amult8_Cmult53} {iopath_Amult8_Cmult54} {iopath_Amult8_Cmult55} {iopath_Amult8_Cmult56} {iopath_Amult8_Cmult57} {iopath_Amult8_Cmult58} {iopath_Amult8_Cmult59} {iopath_Amult8_Cmult60} {iopath_Amult8_Cmult61} {iopath_Amult8_Cmult62} {iopath_Amult8_Cmult63} 0 0 0 0 0 0 0 0 0 {iopath_Amult9_Cmult9} {iopath_Amult9_Cmult10} {iopath_Amult9_Cmult11} {iopath_Amult9_Cmult12} {iopath_Amult9_Cmult13} {iopath_Amult9_Cmult14} {iopath_Amult9_Cmult15} {iopath_Amult9_Cmult16} {iopath_Amult9_Cmult17} {iopath_Amult9_Cmult18} {iopath_Amult9_Cmult19} {iopath_Amult9_Cmult20} {iopath_Amult9_Cmult21} {iopath_Amult9_Cmult22} {iopath_Amult9_Cmult23} {iopath_Amult9_Cmult24} {iopath_Amult9_Cmult25} {iopath_Amult9_Cmult26} {iopath_Amult9_Cmult27} {iopath_Amult9_Cmult28} {iopath_Amult9_Cmult29} {iopath_Amult9_Cmult30} {iopath_Amult9_Cmult31} {iopath_Amult9_Cmult32} {iopath_Amult9_Cmult33} {iopath_Amult9_Cmult34} {iopath_Amult9_Cmult35} {iopath_Amult9_Cmult36} {iopath_Amult9_Cmult37} {iopath_Amult9_Cmult38} {iopath_Amult9_Cmult39} {iopath_Amult9_Cmult40} {iopath_Amult9_Cmult41} {iopath_Amult9_Cmult42} {iopath_Amult9_Cmult43} {iopath_Amult9_Cmult44} {iopath_Amult9_Cmult45} {iopath_Amult9_Cmult46} {iopath_Amult9_Cmult47} {iopath_Amult9_Cmult48} {iopath_Amult9_Cmult49} {iopath_Amult9_Cmult50} {iopath_Amult9_Cmult51} {iopath_Amult9_Cmult52} {iopath_Amult9_Cmult53} {iopath_Amult9_Cmult54} {iopath_Amult9_Cmult55} {iopath_Amult9_Cmult56} {iopath_Amult9_Cmult57} {iopath_Amult9_Cmult58} {iopath_Amult9_Cmult59} {iopath_Amult9_Cmult60} {iopath_Amult9_Cmult61} {iopath_Amult9_Cmult62} {iopath_Amult9_Cmult63} 0 0 0 0 0 0 0 0 0 0 {iopath_Amult10_Cmult10} {iopath_Amult10_Cmult11} {iopath_Amult10_Cmult12} {iopath_Amult10_Cmult13} {iopath_Amult10_Cmult14} {iopath_Amult10_Cmult15} {iopath_Amult10_Cmult16} {iopath_Amult10_Cmult17} {iopath_Amult10_Cmult18} {iopath_Amult10_Cmult19} {iopath_Amult10_Cmult20} {iopath_Amult10_Cmult21} {iopath_Amult10_Cmult22} {iopath_Amult10_Cmult23} {iopath_Amult10_Cmult24} {iopath_Amult10_Cmult25} {iopath_Amult10_Cmult26} {iopath_Amult10_Cmult27} {iopath_Amult10_Cmult28} {iopath_Amult10_Cmult29} {iopath_Amult10_Cmult30} {iopath_Amult10_Cmult31} {iopath_Amult10_Cmult32} {iopath_Amult10_Cmult33} {iopath_Amult10_Cmult34} {iopath_Amult10_Cmult35} {iopath_Amult10_Cmult36} {iopath_Amult10_Cmult37} {iopath_Amult10_Cmult38} {iopath_Amult10_Cmult39} {iopath_Amult10_Cmult40} {iopath_Amult10_Cmult41} {iopath_Amult10_Cmult42} {iopath_Amult10_Cmult43} {iopath_Amult10_Cmult44} {iopath_Amult10_Cmult45} {iopath_Amult10_Cmult46} {iopath_Amult10_Cmult47} {iopath_Amult10_Cmult48} {iopath_Amult10_Cmult49} {iopath_Amult10_Cmult50} {iopath_Amult10_Cmult51} {iopath_Amult10_Cmult52} {iopath_Amult10_Cmult53} {iopath_Amult10_Cmult54} {iopath_Amult10_Cmult55} {iopath_Amult10_Cmult56} {iopath_Amult10_Cmult57} {iopath_Amult10_Cmult58} {iopath_Amult10_Cmult59} {iopath_Amult10_Cmult60} {iopath_Amult10_Cmult61} {iopath_Amult10_Cmult62} {iopath_Amult10_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult11_Cmult11} {iopath_Amult11_Cmult12} {iopath_Amult11_Cmult13} {iopath_Amult11_Cmult14} {iopath_Amult11_Cmult15} {iopath_Amult11_Cmult16} {iopath_Amult11_Cmult17} {iopath_Amult11_Cmult18} {iopath_Amult11_Cmult19} {iopath_Amult11_Cmult20} {iopath_Amult11_Cmult21} {iopath_Amult11_Cmult22} {iopath_Amult11_Cmult23} {iopath_Amult11_Cmult24} {iopath_Amult11_Cmult25} {iopath_Amult11_Cmult26} {iopath_Amult11_Cmult27} {iopath_Amult11_Cmult28} {iopath_Amult11_Cmult29} {iopath_Amult11_Cmult30} {iopath_Amult11_Cmult31} {iopath_Amult11_Cmult32} {iopath_Amult11_Cmult33} {iopath_Amult11_Cmult34} {iopath_Amult11_Cmult35} {iopath_Amult11_Cmult36} {iopath_Amult11_Cmult37} {iopath_Amult11_Cmult38} {iopath_Amult11_Cmult39} {iopath_Amult11_Cmult40} {iopath_Amult11_Cmult41} {iopath_Amult11_Cmult42} {iopath_Amult11_Cmult43} {iopath_Amult11_Cmult44} {iopath_Amult11_Cmult45} {iopath_Amult11_Cmult46} {iopath_Amult11_Cmult47} {iopath_Amult11_Cmult48} {iopath_Amult11_Cmult49} {iopath_Amult11_Cmult50} {iopath_Amult11_Cmult51} {iopath_Amult11_Cmult52} {iopath_Amult11_Cmult53} {iopath_Amult11_Cmult54} {iopath_Amult11_Cmult55} {iopath_Amult11_Cmult56} {iopath_Amult11_Cmult57} {iopath_Amult11_Cmult58} {iopath_Amult11_Cmult59} {iopath_Amult11_Cmult60} {iopath_Amult11_Cmult61} {iopath_Amult11_Cmult62} {iopath_Amult11_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult12_Cmult12} {iopath_Amult12_Cmult13} {iopath_Amult12_Cmult14} {iopath_Amult12_Cmult15} {iopath_Amult12_Cmult16} {iopath_Amult12_Cmult17} {iopath_Amult12_Cmult18} {iopath_Amult12_Cmult19} {iopath_Amult12_Cmult20} {iopath_Amult12_Cmult21} {iopath_Amult12_Cmult22} {iopath_Amult12_Cmult23} {iopath_Amult12_Cmult24} {iopath_Amult12_Cmult25} {iopath_Amult12_Cmult26} {iopath_Amult12_Cmult27} {iopath_Amult12_Cmult28} {iopath_Amult12_Cmult29} {iopath_Amult12_Cmult30} {iopath_Amult12_Cmult31} {iopath_Amult12_Cmult32} {iopath_Amult12_Cmult33} {iopath_Amult12_Cmult34} {iopath_Amult12_Cmult35} {iopath_Amult12_Cmult36} {iopath_Amult12_Cmult37} {iopath_Amult12_Cmult38} {iopath_Amult12_Cmult39} {iopath_Amult12_Cmult40} {iopath_Amult12_Cmult41} {iopath_Amult12_Cmult42} {iopath_Amult12_Cmult43} {iopath_Amult12_Cmult44} {iopath_Amult12_Cmult45} {iopath_Amult12_Cmult46} {iopath_Amult12_Cmult47} {iopath_Amult12_Cmult48} {iopath_Amult12_Cmult49} {iopath_Amult12_Cmult50} {iopath_Amult12_Cmult51} {iopath_Amult12_Cmult52} {iopath_Amult12_Cmult53} {iopath_Amult12_Cmult54} {iopath_Amult12_Cmult55} {iopath_Amult12_Cmult56} {iopath_Amult12_Cmult57} {iopath_Amult12_Cmult58} {iopath_Amult12_Cmult59} {iopath_Amult12_Cmult60} {iopath_Amult12_Cmult61} {iopath_Amult12_Cmult62} {iopath_Amult12_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult13_Cmult13} {iopath_Amult13_Cmult14} {iopath_Amult13_Cmult15} {iopath_Amult13_Cmult16} {iopath_Amult13_Cmult17} {iopath_Amult13_Cmult18} {iopath_Amult13_Cmult19} {iopath_Amult13_Cmult20} {iopath_Amult13_Cmult21} {iopath_Amult13_Cmult22} {iopath_Amult13_Cmult23} {iopath_Amult13_Cmult24} {iopath_Amult13_Cmult25} {iopath_Amult13_Cmult26} {iopath_Amult13_Cmult27} {iopath_Amult13_Cmult28} {iopath_Amult13_Cmult29} {iopath_Amult13_Cmult30} {iopath_Amult13_Cmult31} {iopath_Amult13_Cmult32} {iopath_Amult13_Cmult33} {iopath_Amult13_Cmult34} {iopath_Amult13_Cmult35} {iopath_Amult13_Cmult36} {iopath_Amult13_Cmult37} {iopath_Amult13_Cmult38} {iopath_Amult13_Cmult39} {iopath_Amult13_Cmult40} {iopath_Amult13_Cmult41} {iopath_Amult13_Cmult42} {iopath_Amult13_Cmult43} {iopath_Amult13_Cmult44} {iopath_Amult13_Cmult45} {iopath_Amult13_Cmult46} {iopath_Amult13_Cmult47} {iopath_Amult13_Cmult48} {iopath_Amult13_Cmult49} {iopath_Amult13_Cmult50} {iopath_Amult13_Cmult51} {iopath_Amult13_Cmult52} {iopath_Amult13_Cmult53} {iopath_Amult13_Cmult54} {iopath_Amult13_Cmult55} {iopath_Amult13_Cmult56} {iopath_Amult13_Cmult57} {iopath_Amult13_Cmult58} {iopath_Amult13_Cmult59} {iopath_Amult13_Cmult60} {iopath_Amult13_Cmult61} {iopath_Amult13_Cmult62} {iopath_Amult13_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult14_Cmult14} {iopath_Amult14_Cmult15} {iopath_Amult14_Cmult16} {iopath_Amult14_Cmult17} {iopath_Amult14_Cmult18} {iopath_Amult14_Cmult19} {iopath_Amult14_Cmult20} {iopath_Amult14_Cmult21} {iopath_Amult14_Cmult22} {iopath_Amult14_Cmult23} {iopath_Amult14_Cmult24} {iopath_Amult14_Cmult25} {iopath_Amult14_Cmult26} {iopath_Amult14_Cmult27} {iopath_Amult14_Cmult28} {iopath_Amult14_Cmult29} {iopath_Amult14_Cmult30} {iopath_Amult14_Cmult31} {iopath_Amult14_Cmult32} {iopath_Amult14_Cmult33} {iopath_Amult14_Cmult34} {iopath_Amult14_Cmult35} {iopath_Amult14_Cmult36} {iopath_Amult14_Cmult37} {iopath_Amult14_Cmult38} {iopath_Amult14_Cmult39} {iopath_Amult14_Cmult40} {iopath_Amult14_Cmult41} {iopath_Amult14_Cmult42} {iopath_Amult14_Cmult43} {iopath_Amult14_Cmult44} {iopath_Amult14_Cmult45} {iopath_Amult14_Cmult46} {iopath_Amult14_Cmult47} {iopath_Amult14_Cmult48} {iopath_Amult14_Cmult49} {iopath_Amult14_Cmult50} {iopath_Amult14_Cmult51} {iopath_Amult14_Cmult52} {iopath_Amult14_Cmult53} {iopath_Amult14_Cmult54} {iopath_Amult14_Cmult55} {iopath_Amult14_Cmult56} {iopath_Amult14_Cmult57} {iopath_Amult14_Cmult58} {iopath_Amult14_Cmult59} {iopath_Amult14_Cmult60} {iopath_Amult14_Cmult61} {iopath_Amult14_Cmult62} {iopath_Amult14_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult15_Cmult15} {iopath_Amult15_Cmult16} {iopath_Amult15_Cmult17} {iopath_Amult15_Cmult18} {iopath_Amult15_Cmult19} {iopath_Amult15_Cmult20} {iopath_Amult15_Cmult21} {iopath_Amult15_Cmult22} {iopath_Amult15_Cmult23} {iopath_Amult15_Cmult24} {iopath_Amult15_Cmult25} {iopath_Amult15_Cmult26} {iopath_Amult15_Cmult27} {iopath_Amult15_Cmult28} {iopath_Amult15_Cmult29} {iopath_Amult15_Cmult30} {iopath_Amult15_Cmult31} {iopath_Amult15_Cmult32} {iopath_Amult15_Cmult33} {iopath_Amult15_Cmult34} {iopath_Amult15_Cmult35} {iopath_Amult15_Cmult36} {iopath_Amult15_Cmult37} {iopath_Amult15_Cmult38} {iopath_Amult15_Cmult39} {iopath_Amult15_Cmult40} {iopath_Amult15_Cmult41} {iopath_Amult15_Cmult42} {iopath_Amult15_Cmult43} {iopath_Amult15_Cmult44} {iopath_Amult15_Cmult45} {iopath_Amult15_Cmult46} {iopath_Amult15_Cmult47} {iopath_Amult15_Cmult48} {iopath_Amult15_Cmult49} {iopath_Amult15_Cmult50} {iopath_Amult15_Cmult51} {iopath_Amult15_Cmult52} {iopath_Amult15_Cmult53} {iopath_Amult15_Cmult54} {iopath_Amult15_Cmult55} {iopath_Amult15_Cmult56} {iopath_Amult15_Cmult57} {iopath_Amult15_Cmult58} {iopath_Amult15_Cmult59} {iopath_Amult15_Cmult60} {iopath_Amult15_Cmult61} {iopath_Amult15_Cmult62} {iopath_Amult15_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult16_Cmult16} {iopath_Amult16_Cmult17} {iopath_Amult16_Cmult18} {iopath_Amult16_Cmult19} {iopath_Amult16_Cmult20} {iopath_Amult16_Cmult21} {iopath_Amult16_Cmult22} {iopath_Amult16_Cmult23} {iopath_Amult16_Cmult24} {iopath_Amult16_Cmult25} {iopath_Amult16_Cmult26} {iopath_Amult16_Cmult27} {iopath_Amult16_Cmult28} {iopath_Amult16_Cmult29} {iopath_Amult16_Cmult30} {iopath_Amult16_Cmult31} {iopath_Amult16_Cmult32} {iopath_Amult16_Cmult33} {iopath_Amult16_Cmult34} {iopath_Amult16_Cmult35} {iopath_Amult16_Cmult36} {iopath_Amult16_Cmult37} {iopath_Amult16_Cmult38} {iopath_Amult16_Cmult39} {iopath_Amult16_Cmult40} {iopath_Amult16_Cmult41} {iopath_Amult16_Cmult42} {iopath_Amult16_Cmult43} {iopath_Amult16_Cmult44} {iopath_Amult16_Cmult45} {iopath_Amult16_Cmult46} {iopath_Amult16_Cmult47} {iopath_Amult16_Cmult48} {iopath_Amult16_Cmult49} {iopath_Amult16_Cmult50} {iopath_Amult16_Cmult51} {iopath_Amult16_Cmult52} {iopath_Amult16_Cmult53} {iopath_Amult16_Cmult54} {iopath_Amult16_Cmult55} {iopath_Amult16_Cmult56} {iopath_Amult16_Cmult57} {iopath_Amult16_Cmult58} {iopath_Amult16_Cmult59} {iopath_Amult16_Cmult60} {iopath_Amult16_Cmult61} {iopath_Amult16_Cmult62} {iopath_Amult16_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult17_Cmult17} {iopath_Amult17_Cmult18} {iopath_Amult17_Cmult19} {iopath_Amult17_Cmult20} {iopath_Amult17_Cmult21} {iopath_Amult17_Cmult22} {iopath_Amult17_Cmult23} {iopath_Amult17_Cmult24} {iopath_Amult17_Cmult25} {iopath_Amult17_Cmult26} {iopath_Amult17_Cmult27} {iopath_Amult17_Cmult28} {iopath_Amult17_Cmult29} {iopath_Amult17_Cmult30} {iopath_Amult17_Cmult31} {iopath_Amult17_Cmult32} {iopath_Amult17_Cmult33} {iopath_Amult17_Cmult34} {iopath_Amult17_Cmult35} {iopath_Amult17_Cmult36} {iopath_Amult17_Cmult37} {iopath_Amult17_Cmult38} {iopath_Amult17_Cmult39} {iopath_Amult17_Cmult40} {iopath_Amult17_Cmult41} {iopath_Amult17_Cmult42} {iopath_Amult17_Cmult43} {iopath_Amult17_Cmult44} {iopath_Amult17_Cmult45} {iopath_Amult17_Cmult46} {iopath_Amult17_Cmult47} {iopath_Amult17_Cmult48} {iopath_Amult17_Cmult49} {iopath_Amult17_Cmult50} {iopath_Amult17_Cmult51} {iopath_Amult17_Cmult52} {iopath_Amult17_Cmult53} {iopath_Amult17_Cmult54} {iopath_Amult17_Cmult55} {iopath_Amult17_Cmult56} {iopath_Amult17_Cmult57} {iopath_Amult17_Cmult58} {iopath_Amult17_Cmult59} {iopath_Amult17_Cmult60} {iopath_Amult17_Cmult61} {iopath_Amult17_Cmult62} {iopath_Amult17_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult18_Cmult18} {iopath_Amult18_Cmult19} {iopath_Amult18_Cmult20} {iopath_Amult18_Cmult21} {iopath_Amult18_Cmult22} {iopath_Amult18_Cmult23} {iopath_Amult18_Cmult24} {iopath_Amult18_Cmult25} {iopath_Amult18_Cmult26} {iopath_Amult18_Cmult27} {iopath_Amult18_Cmult28} {iopath_Amult18_Cmult29} {iopath_Amult18_Cmult30} {iopath_Amult18_Cmult31} {iopath_Amult18_Cmult32} {iopath_Amult18_Cmult33} {iopath_Amult18_Cmult34} {iopath_Amult18_Cmult35} {iopath_Amult18_Cmult36} {iopath_Amult18_Cmult37} {iopath_Amult18_Cmult38} {iopath_Amult18_Cmult39} {iopath_Amult18_Cmult40} {iopath_Amult18_Cmult41} {iopath_Amult18_Cmult42} {iopath_Amult18_Cmult43} {iopath_Amult18_Cmult44} {iopath_Amult18_Cmult45} {iopath_Amult18_Cmult46} {iopath_Amult18_Cmult47} {iopath_Amult18_Cmult48} {iopath_Amult18_Cmult49} {iopath_Amult18_Cmult50} {iopath_Amult18_Cmult51} {iopath_Amult18_Cmult52} {iopath_Amult18_Cmult53} {iopath_Amult18_Cmult54} {iopath_Amult18_Cmult55} {iopath_Amult18_Cmult56} {iopath_Amult18_Cmult57} {iopath_Amult18_Cmult58} {iopath_Amult18_Cmult59} {iopath_Amult18_Cmult60} {iopath_Amult18_Cmult61} {iopath_Amult18_Cmult62} {iopath_Amult18_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult19_Cmult19} {iopath_Amult19_Cmult20} {iopath_Amult19_Cmult21} {iopath_Amult19_Cmult22} {iopath_Amult19_Cmult23} {iopath_Amult19_Cmult24} {iopath_Amult19_Cmult25} {iopath_Amult19_Cmult26} {iopath_Amult19_Cmult27} {iopath_Amult19_Cmult28} {iopath_Amult19_Cmult29} {iopath_Amult19_Cmult30} {iopath_Amult19_Cmult31} {iopath_Amult19_Cmult32} {iopath_Amult19_Cmult33} {iopath_Amult19_Cmult34} {iopath_Amult19_Cmult35} {iopath_Amult19_Cmult36} {iopath_Amult19_Cmult37} {iopath_Amult19_Cmult38} {iopath_Amult19_Cmult39} {iopath_Amult19_Cmult40} {iopath_Amult19_Cmult41} {iopath_Amult19_Cmult42} {iopath_Amult19_Cmult43} {iopath_Amult19_Cmult44} {iopath_Amult19_Cmult45} {iopath_Amult19_Cmult46} {iopath_Amult19_Cmult47} {iopath_Amult19_Cmult48} {iopath_Amult19_Cmult49} {iopath_Amult19_Cmult50} {iopath_Amult19_Cmult51} {iopath_Amult19_Cmult52} {iopath_Amult19_Cmult53} {iopath_Amult19_Cmult54} {iopath_Amult19_Cmult55} {iopath_Amult19_Cmult56} {iopath_Amult19_Cmult57} {iopath_Amult19_Cmult58} {iopath_Amult19_Cmult59} {iopath_Amult19_Cmult60} {iopath_Amult19_Cmult61} {iopath_Amult19_Cmult62} {iopath_Amult19_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult20_Cmult20} {iopath_Amult20_Cmult21} {iopath_Amult20_Cmult22} {iopath_Amult20_Cmult23} {iopath_Amult20_Cmult24} {iopath_Amult20_Cmult25} {iopath_Amult20_Cmult26} {iopath_Amult20_Cmult27} {iopath_Amult20_Cmult28} {iopath_Amult20_Cmult29} {iopath_Amult20_Cmult30} {iopath_Amult20_Cmult31} {iopath_Amult20_Cmult32} {iopath_Amult20_Cmult33} {iopath_Amult20_Cmult34} {iopath_Amult20_Cmult35} {iopath_Amult20_Cmult36} {iopath_Amult20_Cmult37} {iopath_Amult20_Cmult38} {iopath_Amult20_Cmult39} {iopath_Amult20_Cmult40} {iopath_Amult20_Cmult41} {iopath_Amult20_Cmult42} {iopath_Amult20_Cmult43} {iopath_Amult20_Cmult44} {iopath_Amult20_Cmult45} {iopath_Amult20_Cmult46} {iopath_Amult20_Cmult47} {iopath_Amult20_Cmult48} {iopath_Amult20_Cmult49} {iopath_Amult20_Cmult50} {iopath_Amult20_Cmult51} {iopath_Amult20_Cmult52} {iopath_Amult20_Cmult53} {iopath_Amult20_Cmult54} {iopath_Amult20_Cmult55} {iopath_Amult20_Cmult56} {iopath_Amult20_Cmult57} {iopath_Amult20_Cmult58} {iopath_Amult20_Cmult59} {iopath_Amult20_Cmult60} {iopath_Amult20_Cmult61} {iopath_Amult20_Cmult62} {iopath_Amult20_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult21_Cmult21} {iopath_Amult21_Cmult22} {iopath_Amult21_Cmult23} {iopath_Amult21_Cmult24} {iopath_Amult21_Cmult25} {iopath_Amult21_Cmult26} {iopath_Amult21_Cmult27} {iopath_Amult21_Cmult28} {iopath_Amult21_Cmult29} {iopath_Amult21_Cmult30} {iopath_Amult21_Cmult31} {iopath_Amult21_Cmult32} {iopath_Amult21_Cmult33} {iopath_Amult21_Cmult34} {iopath_Amult21_Cmult35} {iopath_Amult21_Cmult36} {iopath_Amult21_Cmult37} {iopath_Amult21_Cmult38} {iopath_Amult21_Cmult39} {iopath_Amult21_Cmult40} {iopath_Amult21_Cmult41} {iopath_Amult21_Cmult42} {iopath_Amult21_Cmult43} {iopath_Amult21_Cmult44} {iopath_Amult21_Cmult45} {iopath_Amult21_Cmult46} {iopath_Amult21_Cmult47} {iopath_Amult21_Cmult48} {iopath_Amult21_Cmult49} {iopath_Amult21_Cmult50} {iopath_Amult21_Cmult51} {iopath_Amult21_Cmult52} {iopath_Amult21_Cmult53} {iopath_Amult21_Cmult54} {iopath_Amult21_Cmult55} {iopath_Amult21_Cmult56} {iopath_Amult21_Cmult57} {iopath_Amult21_Cmult58} {iopath_Amult21_Cmult59} {iopath_Amult21_Cmult60} {iopath_Amult21_Cmult61} {iopath_Amult21_Cmult62} {iopath_Amult21_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult22_Cmult22} {iopath_Amult22_Cmult23} {iopath_Amult22_Cmult24} {iopath_Amult22_Cmult25} {iopath_Amult22_Cmult26} {iopath_Amult22_Cmult27} {iopath_Amult22_Cmult28} {iopath_Amult22_Cmult29} {iopath_Amult22_Cmult30} {iopath_Amult22_Cmult31} {iopath_Amult22_Cmult32} {iopath_Amult22_Cmult33} {iopath_Amult22_Cmult34} {iopath_Amult22_Cmult35} {iopath_Amult22_Cmult36} {iopath_Amult22_Cmult37} {iopath_Amult22_Cmult38} {iopath_Amult22_Cmult39} {iopath_Amult22_Cmult40} {iopath_Amult22_Cmult41} {iopath_Amult22_Cmult42} {iopath_Amult22_Cmult43} {iopath_Amult22_Cmult44} {iopath_Amult22_Cmult45} {iopath_Amult22_Cmult46} {iopath_Amult22_Cmult47} {iopath_Amult22_Cmult48} {iopath_Amult22_Cmult49} {iopath_Amult22_Cmult50} {iopath_Amult22_Cmult51} {iopath_Amult22_Cmult52} {iopath_Amult22_Cmult53} {iopath_Amult22_Cmult54} {iopath_Amult22_Cmult55} {iopath_Amult22_Cmult56} {iopath_Amult22_Cmult57} {iopath_Amult22_Cmult58} {iopath_Amult22_Cmult59} {iopath_Amult22_Cmult60} {iopath_Amult22_Cmult61} {iopath_Amult22_Cmult62} {iopath_Amult22_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult23_Cmult23} {iopath_Amult23_Cmult24} {iopath_Amult23_Cmult25} {iopath_Amult23_Cmult26} {iopath_Amult23_Cmult27} {iopath_Amult23_Cmult28} {iopath_Amult23_Cmult29} {iopath_Amult23_Cmult30} {iopath_Amult23_Cmult31} {iopath_Amult23_Cmult32} {iopath_Amult23_Cmult33} {iopath_Amult23_Cmult34} {iopath_Amult23_Cmult35} {iopath_Amult23_Cmult36} {iopath_Amult23_Cmult37} {iopath_Amult23_Cmult38} {iopath_Amult23_Cmult39} {iopath_Amult23_Cmult40} {iopath_Amult23_Cmult41} {iopath_Amult23_Cmult42} {iopath_Amult23_Cmult43} {iopath_Amult23_Cmult44} {iopath_Amult23_Cmult45} {iopath_Amult23_Cmult46} {iopath_Amult23_Cmult47} {iopath_Amult23_Cmult48} {iopath_Amult23_Cmult49} {iopath_Amult23_Cmult50} {iopath_Amult23_Cmult51} {iopath_Amult23_Cmult52} {iopath_Amult23_Cmult53} {iopath_Amult23_Cmult54} {iopath_Amult23_Cmult55} {iopath_Amult23_Cmult56} {iopath_Amult23_Cmult57} {iopath_Amult23_Cmult58} {iopath_Amult23_Cmult59} {iopath_Amult23_Cmult60} {iopath_Amult23_Cmult61} {iopath_Amult23_Cmult62} {iopath_Amult23_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult24_Cmult24} {iopath_Amult24_Cmult25} {iopath_Amult24_Cmult26} {iopath_Amult24_Cmult27} {iopath_Amult24_Cmult28} {iopath_Amult24_Cmult29} {iopath_Amult24_Cmult30} {iopath_Amult24_Cmult31} {iopath_Amult24_Cmult32} {iopath_Amult24_Cmult33} {iopath_Amult24_Cmult34} {iopath_Amult24_Cmult35} {iopath_Amult24_Cmult36} {iopath_Amult24_Cmult37} {iopath_Amult24_Cmult38} {iopath_Amult24_Cmult39} {iopath_Amult24_Cmult40} {iopath_Amult24_Cmult41} {iopath_Amult24_Cmult42} {iopath_Amult24_Cmult43} {iopath_Amult24_Cmult44} {iopath_Amult24_Cmult45} {iopath_Amult24_Cmult46} {iopath_Amult24_Cmult47} {iopath_Amult24_Cmult48} {iopath_Amult24_Cmult49} {iopath_Amult24_Cmult50} {iopath_Amult24_Cmult51} {iopath_Amult24_Cmult52} {iopath_Amult24_Cmult53} {iopath_Amult24_Cmult54} {iopath_Amult24_Cmult55} {iopath_Amult24_Cmult56} {iopath_Amult24_Cmult57} {iopath_Amult24_Cmult58} {iopath_Amult24_Cmult59} {iopath_Amult24_Cmult60} {iopath_Amult24_Cmult61} {iopath_Amult24_Cmult62} {iopath_Amult24_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult25_Cmult25} {iopath_Amult25_Cmult26} {iopath_Amult25_Cmult27} {iopath_Amult25_Cmult28} {iopath_Amult25_Cmult29} {iopath_Amult25_Cmult30} {iopath_Amult25_Cmult31} {iopath_Amult25_Cmult32} {iopath_Amult25_Cmult33} {iopath_Amult25_Cmult34} {iopath_Amult25_Cmult35} {iopath_Amult25_Cmult36} {iopath_Amult25_Cmult37} {iopath_Amult25_Cmult38} {iopath_Amult25_Cmult39} {iopath_Amult25_Cmult40} {iopath_Amult25_Cmult41} {iopath_Amult25_Cmult42} {iopath_Amult25_Cmult43} {iopath_Amult25_Cmult44} {iopath_Amult25_Cmult45} {iopath_Amult25_Cmult46} {iopath_Amult25_Cmult47} {iopath_Amult25_Cmult48} {iopath_Amult25_Cmult49} {iopath_Amult25_Cmult50} {iopath_Amult25_Cmult51} {iopath_Amult25_Cmult52} {iopath_Amult25_Cmult53} {iopath_Amult25_Cmult54} {iopath_Amult25_Cmult55} {iopath_Amult25_Cmult56} {iopath_Amult25_Cmult57} {iopath_Amult25_Cmult58} {iopath_Amult25_Cmult59} {iopath_Amult25_Cmult60} {iopath_Amult25_Cmult61} {iopath_Amult25_Cmult62} {iopath_Amult25_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult26_Cmult26} {iopath_Amult26_Cmult27} {iopath_Amult26_Cmult28} {iopath_Amult26_Cmult29} {iopath_Amult26_Cmult30} {iopath_Amult26_Cmult31} {iopath_Amult26_Cmult32} {iopath_Amult26_Cmult33} {iopath_Amult26_Cmult34} {iopath_Amult26_Cmult35} {iopath_Amult26_Cmult36} {iopath_Amult26_Cmult37} {iopath_Amult26_Cmult38} {iopath_Amult26_Cmult39} {iopath_Amult26_Cmult40} {iopath_Amult26_Cmult41} {iopath_Amult26_Cmult42} {iopath_Amult26_Cmult43} {iopath_Amult26_Cmult44} {iopath_Amult26_Cmult45} {iopath_Amult26_Cmult46} {iopath_Amult26_Cmult47} {iopath_Amult26_Cmult48} {iopath_Amult26_Cmult49} {iopath_Amult26_Cmult50} {iopath_Amult26_Cmult51} {iopath_Amult26_Cmult52} {iopath_Amult26_Cmult53} {iopath_Amult26_Cmult54} {iopath_Amult26_Cmult55} {iopath_Amult26_Cmult56} {iopath_Amult26_Cmult57} {iopath_Amult26_Cmult58} {iopath_Amult26_Cmult59} {iopath_Amult26_Cmult60} {iopath_Amult26_Cmult61} {iopath_Amult26_Cmult62} {iopath_Amult26_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult27_Cmult27} {iopath_Amult27_Cmult28} {iopath_Amult27_Cmult29} {iopath_Amult27_Cmult30} {iopath_Amult27_Cmult31} {iopath_Amult27_Cmult32} {iopath_Amult27_Cmult33} {iopath_Amult27_Cmult34} {iopath_Amult27_Cmult35} {iopath_Amult27_Cmult36} {iopath_Amult27_Cmult37} {iopath_Amult27_Cmult38} {iopath_Amult27_Cmult39} {iopath_Amult27_Cmult40} {iopath_Amult27_Cmult41} {iopath_Amult27_Cmult42} {iopath_Amult27_Cmult43} {iopath_Amult27_Cmult44} {iopath_Amult27_Cmult45} {iopath_Amult27_Cmult46} {iopath_Amult27_Cmult47} {iopath_Amult27_Cmult48} {iopath_Amult27_Cmult49} {iopath_Amult27_Cmult50} {iopath_Amult27_Cmult51} {iopath_Amult27_Cmult52} {iopath_Amult27_Cmult53} {iopath_Amult27_Cmult54} {iopath_Amult27_Cmult55} {iopath_Amult27_Cmult56} {iopath_Amult27_Cmult57} {iopath_Amult27_Cmult58} {iopath_Amult27_Cmult59} {iopath_Amult27_Cmult60} {iopath_Amult27_Cmult61} {iopath_Amult27_Cmult62} {iopath_Amult27_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult28_Cmult28} {iopath_Amult28_Cmult29} {iopath_Amult28_Cmult30} {iopath_Amult28_Cmult31} {iopath_Amult28_Cmult32} {iopath_Amult28_Cmult33} {iopath_Amult28_Cmult34} {iopath_Amult28_Cmult35} {iopath_Amult28_Cmult36} {iopath_Amult28_Cmult37} {iopath_Amult28_Cmult38} {iopath_Amult28_Cmult39} {iopath_Amult28_Cmult40} {iopath_Amult28_Cmult41} {iopath_Amult28_Cmult42} {iopath_Amult28_Cmult43} {iopath_Amult28_Cmult44} {iopath_Amult28_Cmult45} {iopath_Amult28_Cmult46} {iopath_Amult28_Cmult47} {iopath_Amult28_Cmult48} {iopath_Amult28_Cmult49} {iopath_Amult28_Cmult50} {iopath_Amult28_Cmult51} {iopath_Amult28_Cmult52} {iopath_Amult28_Cmult53} {iopath_Amult28_Cmult54} {iopath_Amult28_Cmult55} {iopath_Amult28_Cmult56} {iopath_Amult28_Cmult57} {iopath_Amult28_Cmult58} {iopath_Amult28_Cmult59} {iopath_Amult28_Cmult60} {iopath_Amult28_Cmult61} {iopath_Amult28_Cmult62} {iopath_Amult28_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult29_Cmult29} {iopath_Amult29_Cmult30} {iopath_Amult29_Cmult31} {iopath_Amult29_Cmult32} {iopath_Amult29_Cmult33} {iopath_Amult29_Cmult34} {iopath_Amult29_Cmult35} {iopath_Amult29_Cmult36} {iopath_Amult29_Cmult37} {iopath_Amult29_Cmult38} {iopath_Amult29_Cmult39} {iopath_Amult29_Cmult40} {iopath_Amult29_Cmult41} {iopath_Amult29_Cmult42} {iopath_Amult29_Cmult43} {iopath_Amult29_Cmult44} {iopath_Amult29_Cmult45} {iopath_Amult29_Cmult46} {iopath_Amult29_Cmult47} {iopath_Amult29_Cmult48} {iopath_Amult29_Cmult49} {iopath_Amult29_Cmult50} {iopath_Amult29_Cmult51} {iopath_Amult29_Cmult52} {iopath_Amult29_Cmult53} {iopath_Amult29_Cmult54} {iopath_Amult29_Cmult55} {iopath_Amult29_Cmult56} {iopath_Amult29_Cmult57} {iopath_Amult29_Cmult58} {iopath_Amult29_Cmult59} {iopath_Amult29_Cmult60} {iopath_Amult29_Cmult61} {iopath_Amult29_Cmult62} {iopath_Amult29_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult30_Cmult30} {iopath_Amult30_Cmult31} {iopath_Amult30_Cmult32} {iopath_Amult30_Cmult33} {iopath_Amult30_Cmult34} {iopath_Amult30_Cmult35} {iopath_Amult30_Cmult36} {iopath_Amult30_Cmult37} {iopath_Amult30_Cmult38} {iopath_Amult30_Cmult39} {iopath_Amult30_Cmult40} {iopath_Amult30_Cmult41} {iopath_Amult30_Cmult42} {iopath_Amult30_Cmult43} {iopath_Amult30_Cmult44} {iopath_Amult30_Cmult45} {iopath_Amult30_Cmult46} {iopath_Amult30_Cmult47} {iopath_Amult30_Cmult48} {iopath_Amult30_Cmult49} {iopath_Amult30_Cmult50} {iopath_Amult30_Cmult51} {iopath_Amult30_Cmult52} {iopath_Amult30_Cmult53} {iopath_Amult30_Cmult54} {iopath_Amult30_Cmult55} {iopath_Amult30_Cmult56} {iopath_Amult30_Cmult57} {iopath_Amult30_Cmult58} {iopath_Amult30_Cmult59} {iopath_Amult30_Cmult60} {iopath_Amult30_Cmult61} {iopath_Amult30_Cmult62} {iopath_Amult30_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult31_Cmult31} {iopath_Amult31_Cmult32} {iopath_Amult31_Cmult33} {iopath_Amult31_Cmult34} {iopath_Amult31_Cmult35} {iopath_Amult31_Cmult36} {iopath_Amult31_Cmult37} {iopath_Amult31_Cmult38} {iopath_Amult31_Cmult39} {iopath_Amult31_Cmult40} {iopath_Amult31_Cmult41} {iopath_Amult31_Cmult42} {iopath_Amult31_Cmult43} {iopath_Amult31_Cmult44} {iopath_Amult31_Cmult45} {iopath_Amult31_Cmult46} {iopath_Amult31_Cmult47} {iopath_Amult31_Cmult48} {iopath_Amult31_Cmult49} {iopath_Amult31_Cmult50} {iopath_Amult31_Cmult51} {iopath_Amult31_Cmult52} {iopath_Amult31_Cmult53} {iopath_Amult31_Cmult54} {iopath_Amult31_Cmult55} {iopath_Amult31_Cmult56} {iopath_Amult31_Cmult57} {iopath_Amult31_Cmult58} {iopath_Amult31_Cmult59} {iopath_Amult31_Cmult60} {iopath_Amult31_Cmult61} {iopath_Amult31_Cmult62} {iopath_Amult31_Cmult63} ",
            "DELAY_MATRIX_Bmult": "{iopath_Amult0_Cmult0} {iopath_Amult0_Cmult1} {iopath_Amult0_Cmult2} {iopath_Amult0_Cmult3} {iopath_Amult0_Cmult4} {iopath_Amult0_Cmult5} {iopath_Amult0_Cmult6} {iopath_Amult0_Cmult7} {iopath_Amult0_Cmult8} {iopath_Amult0_Cmult9} {iopath_Amult0_Cmult10} {iopath_Amult0_Cmult11} {iopath_Amult0_Cmult12} {iopath_Amult0_Cmult13} {iopath_Amult0_Cmult14} {iopath_Amult0_Cmult15} {iopath_Amult0_Cmult16} {iopath_Amult0_Cmult17} {iopath_Amult0_Cmult18} {iopath_Amult0_Cmult19} {iopath_Amult0_Cmult20} {iopath_Amult0_Cmult21} {iopath_Amult0_Cmult22} {iopath_Amult0_Cmult23} {iopath_Amult0_Cmult24} {iopath_Amult0_Cmult25} {iopath_Amult0_Cmult26} {iopath_Amult0_Cmult27} {iopath_Amult0_Cmult28} {iopath_Amult0_Cmult29} {iopath_Amult0_Cmult30} {iopath_Amult0_Cmult31} {iopath_Amult0_Cmult32} {iopath_Amult0_Cmult33} {iopath_Amult0_Cmult34} {iopath_Amult0_Cmult35} {iopath_Amult0_Cmult36} {iopath_Amult0_Cmult37} {iopath_Amult0_Cmult38} {iopath_Amult0_Cmult39} {iopath_Amult0_Cmult40} {iopath_Amult0_Cmult41} {iopath_Amult0_Cmult42} {iopath_Amult0_Cmult43} {iopath_Amult0_Cmult44} {iopath_Amult0_Cmult45} {iopath_Amult0_Cmult46} {iopath_Amult0_Cmult47} {iopath_Amult0_Cmult48} {iopath_Amult0_Cmult49} {iopath_Amult0_Cmult50} {iopath_Amult0_Cmult51} {iopath_Amult0_Cmult52} {iopath_Amult0_Cmult53} {iopath_Amult0_Cmult54} {iopath_Amult0_Cmult55} {iopath_Amult0_Cmult56} {iopath_Amult0_Cmult57} {iopath_Amult0_Cmult58} {iopath_Amult0_Cmult59} {iopath_Amult0_Cmult60} {iopath_Amult0_Cmult61} {iopath_Amult0_Cmult62} {iopath_Amult0_Cmult63} 0 {iopath_Amult1_Cmult1} {iopath_Amult1_Cmult2} {iopath_Amult1_Cmult3} {iopath_Amult1_Cmult4} {iopath_Amult1_Cmult5} {iopath_Amult1_Cmult6} {iopath_Amult1_Cmult7} {iopath_Amult1_Cmult8} {iopath_Amult1_Cmult9} {iopath_Amult1_Cmult10} {iopath_Amult1_Cmult11} {iopath_Amult1_Cmult12} {iopath_Amult1_Cmult13} {iopath_Amult1_Cmult14} {iopath_Amult1_Cmult15} {iopath_Amult1_Cmult16} {iopath_Amult1_Cmult17} {iopath_Amult1_Cmult18} {iopath_Amult1_Cmult19} {iopath_Amult1_Cmult20} {iopath_Amult1_Cmult21} {iopath_Amult1_Cmult22} {iopath_Amult1_Cmult23} {iopath_Amult1_Cmult24} {iopath_Amult1_Cmult25} {iopath_Amult1_Cmult26} {iopath_Amult1_Cmult27} {iopath_Amult1_Cmult28} {iopath_Amult1_Cmult29} {iopath_Amult1_Cmult30} {iopath_Amult1_Cmult31} {iopath_Amult1_Cmult32} {iopath_Amult1_Cmult33} {iopath_Amult1_Cmult34} {iopath_Amult1_Cmult35} {iopath_Amult1_Cmult36} {iopath_Amult1_Cmult37} {iopath_Amult1_Cmult38} {iopath_Amult1_Cmult39} {iopath_Amult1_Cmult40} {iopath_Amult1_Cmult41} {iopath_Amult1_Cmult42} {iopath_Amult1_Cmult43} {iopath_Amult1_Cmult44} {iopath_Amult1_Cmult45} {iopath_Amult1_Cmult46} {iopath_Amult1_Cmult47} {iopath_Amult1_Cmult48} {iopath_Amult1_Cmult49} {iopath_Amult1_Cmult50} {iopath_Amult1_Cmult51} {iopath_Amult1_Cmult52} {iopath_Amult1_Cmult53} {iopath_Amult1_Cmult54} {iopath_Amult1_Cmult55} {iopath_Amult1_Cmult56} {iopath_Amult1_Cmult57} {iopath_Amult1_Cmult58} {iopath_Amult1_Cmult59} {iopath_Amult1_Cmult60} {iopath_Amult1_Cmult61} {iopath_Amult1_Cmult62} {iopath_Amult1_Cmult63} 0 0 {iopath_Amult2_Cmult2} {iopath_Amult2_Cmult3} {iopath_Amult2_Cmult4} {iopath_Amult2_Cmult5} {iopath_Amult2_Cmult6} {iopath_Amult2_Cmult7} {iopath_Amult2_Cmult8} {iopath_Amult2_Cmult9} {iopath_Amult2_Cmult10} {iopath_Amult2_Cmult11} {iopath_Amult2_Cmult12} {iopath_Amult2_Cmult13} {iopath_Amult2_Cmult14} {iopath_Amult2_Cmult15} {iopath_Amult2_Cmult16} {iopath_Amult2_Cmult17} {iopath_Amult2_Cmult18} {iopath_Amult2_Cmult19} {iopath_Amult2_Cmult20} {iopath_Amult2_Cmult21} {iopath_Amult2_Cmult22} {iopath_Amult2_Cmult23} {iopath_Amult2_Cmult24} {iopath_Amult2_Cmult25} {iopath_Amult2_Cmult26} {iopath_Amult2_Cmult27} {iopath_Amult2_Cmult28} {iopath_Amult2_Cmult29} {iopath_Amult2_Cmult30} {iopath_Amult2_Cmult31} {iopath_Amult2_Cmult32} {iopath_Amult2_Cmult33} {iopath_Amult2_Cmult34} {iopath_Amult2_Cmult35} {iopath_Amult2_Cmult36} {iopath_Amult2_Cmult37} {iopath_Amult2_Cmult38} {iopath_Amult2_Cmult39} {iopath_Amult2_Cmult40} {iopath_Amult2_Cmult41} {iopath_Amult2_Cmult42} {iopath_Amult2_Cmult43} {iopath_Amult2_Cmult44} {iopath_Amult2_Cmult45} {iopath_Amult2_Cmult46} {iopath_Amult2_Cmult47} {iopath_Amult2_Cmult48} {iopath_Amult2_Cmult49} {iopath_Amult2_Cmult50} {iopath_Amult2_Cmult51} {iopath_Amult2_Cmult52} {iopath_Amult2_Cmult53} {iopath_Amult2_Cmult54} {iopath_Amult2_Cmult55} {iopath_Amult2_Cmult56} {iopath_Amult2_Cmult57} {iopath_Amult2_Cmult58} {iopath_Amult2_Cmult59} {iopath_Amult2_Cmult60} {iopath_Amult2_Cmult61} {iopath_Amult2_Cmult62} {iopath_Amult2_Cmult63} 0 0 0 {iopath_Amult3_Cmult3} {iopath_Amult3_Cmult4} {iopath_Amult3_Cmult5} {iopath_Amult3_Cmult6} {iopath_Amult3_Cmult7} {iopath_Amult3_Cmult8} {iopath_Amult3_Cmult9} {iopath_Amult3_Cmult10} {iopath_Amult3_Cmult11} {iopath_Amult3_Cmult12} {iopath_Amult3_Cmult13} {iopath_Amult3_Cmult14} {iopath_Amult3_Cmult15} {iopath_Amult3_Cmult16} {iopath_Amult3_Cmult17} {iopath_Amult3_Cmult18} {iopath_Amult3_Cmult19} {iopath_Amult3_Cmult20} {iopath_Amult3_Cmult21} {iopath_Amult3_Cmult22} {iopath_Amult3_Cmult23} {iopath_Amult3_Cmult24} {iopath_Amult3_Cmult25} {iopath_Amult3_Cmult26} {iopath_Amult3_Cmult27} {iopath_Amult3_Cmult28} {iopath_Amult3_Cmult29} {iopath_Amult3_Cmult30} {iopath_Amult3_Cmult31} {iopath_Amult3_Cmult32} {iopath_Amult3_Cmult33} {iopath_Amult3_Cmult34} {iopath_Amult3_Cmult35} {iopath_Amult3_Cmult36} {iopath_Amult3_Cmult37} {iopath_Amult3_Cmult38} {iopath_Amult3_Cmult39} {iopath_Amult3_Cmult40} {iopath_Amult3_Cmult41} {iopath_Amult3_Cmult42} {iopath_Amult3_Cmult43} {iopath_Amult3_Cmult44} {iopath_Amult3_Cmult45} {iopath_Amult3_Cmult46} {iopath_Amult3_Cmult47} {iopath_Amult3_Cmult48} {iopath_Amult3_Cmult49} {iopath_Amult3_Cmult50} {iopath_Amult3_Cmult51} {iopath_Amult3_Cmult52} {iopath_Amult3_Cmult53} {iopath_Amult3_Cmult54} {iopath_Amult3_Cmult55} {iopath_Amult3_Cmult56} {iopath_Amult3_Cmult57} {iopath_Amult3_Cmult58} {iopath_Amult3_Cmult59} {iopath_Amult3_Cmult60} {iopath_Amult3_Cmult61} {iopath_Amult3_Cmult62} {iopath_Amult3_Cmult63} 0 0 0 0 {iopath_Amult4_Cmult4} {iopath_Amult4_Cmult5} {iopath_Amult4_Cmult6} {iopath_Amult4_Cmult7} {iopath_Amult4_Cmult8} {iopath_Amult4_Cmult9} {iopath_Amult4_Cmult10} {iopath_Amult4_Cmult11} {iopath_Amult4_Cmult12} {iopath_Amult4_Cmult13} {iopath_Amult4_Cmult14} {iopath_Amult4_Cmult15} {iopath_Amult4_Cmult16} {iopath_Amult4_Cmult17} {iopath_Amult4_Cmult18} {iopath_Amult4_Cmult19} {iopath_Amult4_Cmult20} {iopath_Amult4_Cmult21} {iopath_Amult4_Cmult22} {iopath_Amult4_Cmult23} {iopath_Amult4_Cmult24} {iopath_Amult4_Cmult25} {iopath_Amult4_Cmult26} {iopath_Amult4_Cmult27} {iopath_Amult4_Cmult28} {iopath_Amult4_Cmult29} {iopath_Amult4_Cmult30} {iopath_Amult4_Cmult31} {iopath_Amult4_Cmult32} {iopath_Amult4_Cmult33} {iopath_Amult4_Cmult34} {iopath_Amult4_Cmult35} {iopath_Amult4_Cmult36} {iopath_Amult4_Cmult37} {iopath_Amult4_Cmult38} {iopath_Amult4_Cmult39} {iopath_Amult4_Cmult40} {iopath_Amult4_Cmult41} {iopath_Amult4_Cmult42} {iopath_Amult4_Cmult43} {iopath_Amult4_Cmult44} {iopath_Amult4_Cmult45} {iopath_Amult4_Cmult46} {iopath_Amult4_Cmult47} {iopath_Amult4_Cmult48} {iopath_Amult4_Cmult49} {iopath_Amult4_Cmult50} {iopath_Amult4_Cmult51} {iopath_Amult4_Cmult52} {iopath_Amult4_Cmult53} {iopath_Amult4_Cmult54} {iopath_Amult4_Cmult55} {iopath_Amult4_Cmult56} {iopath_Amult4_Cmult57} {iopath_Amult4_Cmult58} {iopath_Amult4_Cmult59} {iopath_Amult4_Cmult60} {iopath_Amult4_Cmult61} {iopath_Amult4_Cmult62} {iopath_Amult4_Cmult63} 0 0 0 0 0 {iopath_Amult5_Cmult5} {iopath_Amult5_Cmult6} {iopath_Amult5_Cmult7} {iopath_Amult5_Cmult8} {iopath_Amult5_Cmult9} {iopath_Amult5_Cmult10} {iopath_Amult5_Cmult11} {iopath_Amult5_Cmult12} {iopath_Amult5_Cmult13} {iopath_Amult5_Cmult14} {iopath_Amult5_Cmult15} {iopath_Amult5_Cmult16} {iopath_Amult5_Cmult17} {iopath_Amult5_Cmult18} {iopath_Amult5_Cmult19} {iopath_Amult5_Cmult20} {iopath_Amult5_Cmult21} {iopath_Amult5_Cmult22} {iopath_Amult5_Cmult23} {iopath_Amult5_Cmult24} {iopath_Amult5_Cmult25} {iopath_Amult5_Cmult26} {iopath_Amult5_Cmult27} {iopath_Amult5_Cmult28} {iopath_Amult5_Cmult29} {iopath_Amult5_Cmult30} {iopath_Amult5_Cmult31} {iopath_Amult5_Cmult32} {iopath_Amult5_Cmult33} {iopath_Amult5_Cmult34} {iopath_Amult5_Cmult35} {iopath_Amult5_Cmult36} {iopath_Amult5_Cmult37} {iopath_Amult5_Cmult38} {iopath_Amult5_Cmult39} {iopath_Amult5_Cmult40} {iopath_Amult5_Cmult41} {iopath_Amult5_Cmult42} {iopath_Amult5_Cmult43} {iopath_Amult5_Cmult44} {iopath_Amult5_Cmult45} {iopath_Amult5_Cmult46} {iopath_Amult5_Cmult47} {iopath_Amult5_Cmult48} {iopath_Amult5_Cmult49} {iopath_Amult5_Cmult50} {iopath_Amult5_Cmult51} {iopath_Amult5_Cmult52} {iopath_Amult5_Cmult53} {iopath_Amult5_Cmult54} {iopath_Amult5_Cmult55} {iopath_Amult5_Cmult56} {iopath_Amult5_Cmult57} {iopath_Amult5_Cmult58} {iopath_Amult5_Cmult59} {iopath_Amult5_Cmult60} {iopath_Amult5_Cmult61} {iopath_Amult5_Cmult62} {iopath_Amult5_Cmult63} 0 0 0 0 0 0 {iopath_Amult6_Cmult6} {iopath_Amult6_Cmult7} {iopath_Amult6_Cmult8} {iopath_Amult6_Cmult9} {iopath_Amult6_Cmult10} {iopath_Amult6_Cmult11} {iopath_Amult6_Cmult12} {iopath_Amult6_Cmult13} {iopath_Amult6_Cmult14} {iopath_Amult6_Cmult15} {iopath_Amult6_Cmult16} {iopath_Amult6_Cmult17} {iopath_Amult6_Cmult18} {iopath_Amult6_Cmult19} {iopath_Amult6_Cmult20} {iopath_Amult6_Cmult21} {iopath_Amult6_Cmult22} {iopath_Amult6_Cmult23} {iopath_Amult6_Cmult24} {iopath_Amult6_Cmult25} {iopath_Amult6_Cmult26} {iopath_Amult6_Cmult27} {iopath_Amult6_Cmult28} {iopath_Amult6_Cmult29} {iopath_Amult6_Cmult30} {iopath_Amult6_Cmult31} {iopath_Amult6_Cmult32} {iopath_Amult6_Cmult33} {iopath_Amult6_Cmult34} {iopath_Amult6_Cmult35} {iopath_Amult6_Cmult36} {iopath_Amult6_Cmult37} {iopath_Amult6_Cmult38} {iopath_Amult6_Cmult39} {iopath_Amult6_Cmult40} {iopath_Amult6_Cmult41} {iopath_Amult6_Cmult42} {iopath_Amult6_Cmult43} {iopath_Amult6_Cmult44} {iopath_Amult6_Cmult45} {iopath_Amult6_Cmult46} {iopath_Amult6_Cmult47} {iopath_Amult6_Cmult48} {iopath_Amult6_Cmult49} {iopath_Amult6_Cmult50} {iopath_Amult6_Cmult51} {iopath_Amult6_Cmult52} {iopath_Amult6_Cmult53} {iopath_Amult6_Cmult54} {iopath_Amult6_Cmult55} {iopath_Amult6_Cmult56} {iopath_Amult6_Cmult57} {iopath_Amult6_Cmult58} {iopath_Amult6_Cmult59} {iopath_Amult6_Cmult60} {iopath_Amult6_Cmult61} {iopath_Amult6_Cmult62} {iopath_Amult6_Cmult63} 0 0 0 0 0 0 0 {iopath_Amult7_Cmult7} {iopath_Amult7_Cmult8} {iopath_Amult7_Cmult9} {iopath_Amult7_Cmult10} {iopath_Amult7_Cmult11} {iopath_Amult7_Cmult12} {iopath_Amult7_Cmult13} {iopath_Amult7_Cmult14} {iopath_Amult7_Cmult15} {iopath_Amult7_Cmult16} {iopath_Amult7_Cmult17} {iopath_Amult7_Cmult18} {iopath_Amult7_Cmult19} {iopath_Amult7_Cmult20} {iopath_Amult7_Cmult21} {iopath_Amult7_Cmult22} {iopath_Amult7_Cmult23} {iopath_Amult7_Cmult24} {iopath_Amult7_Cmult25} {iopath_Amult7_Cmult26} {iopath_Amult7_Cmult27} {iopath_Amult7_Cmult28} {iopath_Amult7_Cmult29} {iopath_Amult7_Cmult30} {iopath_Amult7_Cmult31} {iopath_Amult7_Cmult32} {iopath_Amult7_Cmult33} {iopath_Amult7_Cmult34} {iopath_Amult7_Cmult35} {iopath_Amult7_Cmult36} {iopath_Amult7_Cmult37} {iopath_Amult7_Cmult38} {iopath_Amult7_Cmult39} {iopath_Amult7_Cmult40} {iopath_Amult7_Cmult41} {iopath_Amult7_Cmult42} {iopath_Amult7_Cmult43} {iopath_Amult7_Cmult44} {iopath_Amult7_Cmult45} {iopath_Amult7_Cmult46} {iopath_Amult7_Cmult47} {iopath_Amult7_Cmult48} {iopath_Amult7_Cmult49} {iopath_Amult7_Cmult50} {iopath_Amult7_Cmult51} {iopath_Amult7_Cmult52} {iopath_Amult7_Cmult53} {iopath_Amult7_Cmult54} {iopath_Amult7_Cmult55} {iopath_Amult7_Cmult56} {iopath_Amult7_Cmult57} {iopath_Amult7_Cmult58} {iopath_Amult7_Cmult59} {iopath_Amult7_Cmult60} {iopath_Amult7_Cmult61} {iopath_Amult7_Cmult62} {iopath_Amult7_Cmult63} 0 0 0 0 0 0 0 0 {iopath_Amult8_Cmult8} {iopath_Amult8_Cmult9} {iopath_Amult8_Cmult10} {iopath_Amult8_Cmult11} {iopath_Amult8_Cmult12} {iopath_Amult8_Cmult13} {iopath_Amult8_Cmult14} {iopath_Amult8_Cmult15} {iopath_Amult8_Cmult16} {iopath_Amult8_Cmult17} {iopath_Amult8_Cmult18} {iopath_Amult8_Cmult19} {iopath_Amult8_Cmult20} {iopath_Amult8_Cmult21} {iopath_Amult8_Cmult22} {iopath_Amult8_Cmult23} {iopath_Amult8_Cmult24} {iopath_Amult8_Cmult25} {iopath_Amult8_Cmult26} {iopath_Amult8_Cmult27} {iopath_Amult8_Cmult28} {iopath_Amult8_Cmult29} {iopath_Amult8_Cmult30} {iopath_Amult8_Cmult31} {iopath_Amult8_Cmult32} {iopath_Amult8_Cmult33} {iopath_Amult8_Cmult34} {iopath_Amult8_Cmult35} {iopath_Amult8_Cmult36} {iopath_Amult8_Cmult37} {iopath_Amult8_Cmult38} {iopath_Amult8_Cmult39} {iopath_Amult8_Cmult40} {iopath_Amult8_Cmult41} {iopath_Amult8_Cmult42} {iopath_Amult8_Cmult43} {iopath_Amult8_Cmult44} {iopath_Amult8_Cmult45} {iopath_Amult8_Cmult46} {iopath_Amult8_Cmult47} {iopath_Amult8_Cmult48} {iopath_Amult8_Cmult49} {iopath_Amult8_Cmult50} {iopath_Amult8_Cmult51} {iopath_Amult8_Cmult52} {iopath_Amult8_Cmult53} {iopath_Amult8_Cmult54} {iopath_Amult8_Cmult55} {iopath_Amult8_Cmult56} {iopath_Amult8_Cmult57} {iopath_Amult8_Cmult58} {iopath_Amult8_Cmult59} {iopath_Amult8_Cmult60} {iopath_Amult8_Cmult61} {iopath_Amult8_Cmult62} {iopath_Amult8_Cmult63} 0 0 0 0 0 0 0 0 0 {iopath_Amult9_Cmult9} {iopath_Amult9_Cmult10} {iopath_Amult9_Cmult11} {iopath_Amult9_Cmult12} {iopath_Amult9_Cmult13} {iopath_Amult9_Cmult14} {iopath_Amult9_Cmult15} {iopath_Amult9_Cmult16} {iopath_Amult9_Cmult17} {iopath_Amult9_Cmult18} {iopath_Amult9_Cmult19} {iopath_Amult9_Cmult20} {iopath_Amult9_Cmult21} {iopath_Amult9_Cmult22} {iopath_Amult9_Cmult23} {iopath_Amult9_Cmult24} {iopath_Amult9_Cmult25} {iopath_Amult9_Cmult26} {iopath_Amult9_Cmult27} {iopath_Amult9_Cmult28} {iopath_Amult9_Cmult29} {iopath_Amult9_Cmult30} {iopath_Amult9_Cmult31} {iopath_Amult9_Cmult32} {iopath_Amult9_Cmult33} {iopath_Amult9_Cmult34} {iopath_Amult9_Cmult35} {iopath_Amult9_Cmult36} {iopath_Amult9_Cmult37} {iopath_Amult9_Cmult38} {iopath_Amult9_Cmult39} {iopath_Amult9_Cmult40} {iopath_Amult9_Cmult41} {iopath_Amult9_Cmult42} {iopath_Amult9_Cmult43} {iopath_Amult9_Cmult44} {iopath_Amult9_Cmult45} {iopath_Amult9_Cmult46} {iopath_Amult9_Cmult47} {iopath_Amult9_Cmult48} {iopath_Amult9_Cmult49} {iopath_Amult9_Cmult50} {iopath_Amult9_Cmult51} {iopath_Amult9_Cmult52} {iopath_Amult9_Cmult53} {iopath_Amult9_Cmult54} {iopath_Amult9_Cmult55} {iopath_Amult9_Cmult56} {iopath_Amult9_Cmult57} {iopath_Amult9_Cmult58} {iopath_Amult9_Cmult59} {iopath_Amult9_Cmult60} {iopath_Amult9_Cmult61} {iopath_Amult9_Cmult62} {iopath_Amult9_Cmult63} 0 0 0 0 0 0 0 0 0 0 {iopath_Amult10_Cmult10} {iopath_Amult10_Cmult11} {iopath_Amult10_Cmult12} {iopath_Amult10_Cmult13} {iopath_Amult10_Cmult14} {iopath_Amult10_Cmult15} {iopath_Amult10_Cmult16} {iopath_Amult10_Cmult17} {iopath_Amult10_Cmult18} {iopath_Amult10_Cmult19} {iopath_Amult10_Cmult20} {iopath_Amult10_Cmult21} {iopath_Amult10_Cmult22} {iopath_Amult10_Cmult23} {iopath_Amult10_Cmult24} {iopath_Amult10_Cmult25} {iopath_Amult10_Cmult26} {iopath_Amult10_Cmult27} {iopath_Amult10_Cmult28} {iopath_Amult10_Cmult29} {iopath_Amult10_Cmult30} {iopath_Amult10_Cmult31} {iopath_Amult10_Cmult32} {iopath_Amult10_Cmult33} {iopath_Amult10_Cmult34} {iopath_Amult10_Cmult35} {iopath_Amult10_Cmult36} {iopath_Amult10_Cmult37} {iopath_Amult10_Cmult38} {iopath_Amult10_Cmult39} {iopath_Amult10_Cmult40} {iopath_Amult10_Cmult41} {iopath_Amult10_Cmult42} {iopath_Amult10_Cmult43} {iopath_Amult10_Cmult44} {iopath_Amult10_Cmult45} {iopath_Amult10_Cmult46} {iopath_Amult10_Cmult47} {iopath_Amult10_Cmult48} {iopath_Amult10_Cmult49} {iopath_Amult10_Cmult50} {iopath_Amult10_Cmult51} {iopath_Amult10_Cmult52} {iopath_Amult10_Cmult53} {iopath_Amult10_Cmult54} {iopath_Amult10_Cmult55} {iopath_Amult10_Cmult56} {iopath_Amult10_Cmult57} {iopath_Amult10_Cmult58} {iopath_Amult10_Cmult59} {iopath_Amult10_Cmult60} {iopath_Amult10_Cmult61} {iopath_Amult10_Cmult62} {iopath_Amult10_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult11_Cmult11} {iopath_Amult11_Cmult12} {iopath_Amult11_Cmult13} {iopath_Amult11_Cmult14} {iopath_Amult11_Cmult15} {iopath_Amult11_Cmult16} {iopath_Amult11_Cmult17} {iopath_Amult11_Cmult18} {iopath_Amult11_Cmult19} {iopath_Amult11_Cmult20} {iopath_Amult11_Cmult21} {iopath_Amult11_Cmult22} {iopath_Amult11_Cmult23} {iopath_Amult11_Cmult24} {iopath_Amult11_Cmult25} {iopath_Amult11_Cmult26} {iopath_Amult11_Cmult27} {iopath_Amult11_Cmult28} {iopath_Amult11_Cmult29} {iopath_Amult11_Cmult30} {iopath_Amult11_Cmult31} {iopath_Amult11_Cmult32} {iopath_Amult11_Cmult33} {iopath_Amult11_Cmult34} {iopath_Amult11_Cmult35} {iopath_Amult11_Cmult36} {iopath_Amult11_Cmult37} {iopath_Amult11_Cmult38} {iopath_Amult11_Cmult39} {iopath_Amult11_Cmult40} {iopath_Amult11_Cmult41} {iopath_Amult11_Cmult42} {iopath_Amult11_Cmult43} {iopath_Amult11_Cmult44} {iopath_Amult11_Cmult45} {iopath_Amult11_Cmult46} {iopath_Amult11_Cmult47} {iopath_Amult11_Cmult48} {iopath_Amult11_Cmult49} {iopath_Amult11_Cmult50} {iopath_Amult11_Cmult51} {iopath_Amult11_Cmult52} {iopath_Amult11_Cmult53} {iopath_Amult11_Cmult54} {iopath_Amult11_Cmult55} {iopath_Amult11_Cmult56} {iopath_Amult11_Cmult57} {iopath_Amult11_Cmult58} {iopath_Amult11_Cmult59} {iopath_Amult11_Cmult60} {iopath_Amult11_Cmult61} {iopath_Amult11_Cmult62} {iopath_Amult11_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult12_Cmult12} {iopath_Amult12_Cmult13} {iopath_Amult12_Cmult14} {iopath_Amult12_Cmult15} {iopath_Amult12_Cmult16} {iopath_Amult12_Cmult17} {iopath_Amult12_Cmult18} {iopath_Amult12_Cmult19} {iopath_Amult12_Cmult20} {iopath_Amult12_Cmult21} {iopath_Amult12_Cmult22} {iopath_Amult12_Cmult23} {iopath_Amult12_Cmult24} {iopath_Amult12_Cmult25} {iopath_Amult12_Cmult26} {iopath_Amult12_Cmult27} {iopath_Amult12_Cmult28} {iopath_Amult12_Cmult29} {iopath_Amult12_Cmult30} {iopath_Amult12_Cmult31} {iopath_Amult12_Cmult32} {iopath_Amult12_Cmult33} {iopath_Amult12_Cmult34} {iopath_Amult12_Cmult35} {iopath_Amult12_Cmult36} {iopath_Amult12_Cmult37} {iopath_Amult12_Cmult38} {iopath_Amult12_Cmult39} {iopath_Amult12_Cmult40} {iopath_Amult12_Cmult41} {iopath_Amult12_Cmult42} {iopath_Amult12_Cmult43} {iopath_Amult12_Cmult44} {iopath_Amult12_Cmult45} {iopath_Amult12_Cmult46} {iopath_Amult12_Cmult47} {iopath_Amult12_Cmult48} {iopath_Amult12_Cmult49} {iopath_Amult12_Cmult50} {iopath_Amult12_Cmult51} {iopath_Amult12_Cmult52} {iopath_Amult12_Cmult53} {iopath_Amult12_Cmult54} {iopath_Amult12_Cmult55} {iopath_Amult12_Cmult56} {iopath_Amult12_Cmult57} {iopath_Amult12_Cmult58} {iopath_Amult12_Cmult59} {iopath_Amult12_Cmult60} {iopath_Amult12_Cmult61} {iopath_Amult12_Cmult62} {iopath_Amult12_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult13_Cmult13} {iopath_Amult13_Cmult14} {iopath_Amult13_Cmult15} {iopath_Amult13_Cmult16} {iopath_Amult13_Cmult17} {iopath_Amult13_Cmult18} {iopath_Amult13_Cmult19} {iopath_Amult13_Cmult20} {iopath_Amult13_Cmult21} {iopath_Amult13_Cmult22} {iopath_Amult13_Cmult23} {iopath_Amult13_Cmult24} {iopath_Amult13_Cmult25} {iopath_Amult13_Cmult26} {iopath_Amult13_Cmult27} {iopath_Amult13_Cmult28} {iopath_Amult13_Cmult29} {iopath_Amult13_Cmult30} {iopath_Amult13_Cmult31} {iopath_Amult13_Cmult32} {iopath_Amult13_Cmult33} {iopath_Amult13_Cmult34} {iopath_Amult13_Cmult35} {iopath_Amult13_Cmult36} {iopath_Amult13_Cmult37} {iopath_Amult13_Cmult38} {iopath_Amult13_Cmult39} {iopath_Amult13_Cmult40} {iopath_Amult13_Cmult41} {iopath_Amult13_Cmult42} {iopath_Amult13_Cmult43} {iopath_Amult13_Cmult44} {iopath_Amult13_Cmult45} {iopath_Amult13_Cmult46} {iopath_Amult13_Cmult47} {iopath_Amult13_Cmult48} {iopath_Amult13_Cmult49} {iopath_Amult13_Cmult50} {iopath_Amult13_Cmult51} {iopath_Amult13_Cmult52} {iopath_Amult13_Cmult53} {iopath_Amult13_Cmult54} {iopath_Amult13_Cmult55} {iopath_Amult13_Cmult56} {iopath_Amult13_Cmult57} {iopath_Amult13_Cmult58} {iopath_Amult13_Cmult59} {iopath_Amult13_Cmult60} {iopath_Amult13_Cmult61} {iopath_Amult13_Cmult62} {iopath_Amult13_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult14_Cmult14} {iopath_Amult14_Cmult15} {iopath_Amult14_Cmult16} {iopath_Amult14_Cmult17} {iopath_Amult14_Cmult18} {iopath_Amult14_Cmult19} {iopath_Amult14_Cmult20} {iopath_Amult14_Cmult21} {iopath_Amult14_Cmult22} {iopath_Amult14_Cmult23} {iopath_Amult14_Cmult24} {iopath_Amult14_Cmult25} {iopath_Amult14_Cmult26} {iopath_Amult14_Cmult27} {iopath_Amult14_Cmult28} {iopath_Amult14_Cmult29} {iopath_Amult14_Cmult30} {iopath_Amult14_Cmult31} {iopath_Amult14_Cmult32} {iopath_Amult14_Cmult33} {iopath_Amult14_Cmult34} {iopath_Amult14_Cmult35} {iopath_Amult14_Cmult36} {iopath_Amult14_Cmult37} {iopath_Amult14_Cmult38} {iopath_Amult14_Cmult39} {iopath_Amult14_Cmult40} {iopath_Amult14_Cmult41} {iopath_Amult14_Cmult42} {iopath_Amult14_Cmult43} {iopath_Amult14_Cmult44} {iopath_Amult14_Cmult45} {iopath_Amult14_Cmult46} {iopath_Amult14_Cmult47} {iopath_Amult14_Cmult48} {iopath_Amult14_Cmult49} {iopath_Amult14_Cmult50} {iopath_Amult14_Cmult51} {iopath_Amult14_Cmult52} {iopath_Amult14_Cmult53} {iopath_Amult14_Cmult54} {iopath_Amult14_Cmult55} {iopath_Amult14_Cmult56} {iopath_Amult14_Cmult57} {iopath_Amult14_Cmult58} {iopath_Amult14_Cmult59} {iopath_Amult14_Cmult60} {iopath_Amult14_Cmult61} {iopath_Amult14_Cmult62} {iopath_Amult14_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult15_Cmult15} {iopath_Amult15_Cmult16} {iopath_Amult15_Cmult17} {iopath_Amult15_Cmult18} {iopath_Amult15_Cmult19} {iopath_Amult15_Cmult20} {iopath_Amult15_Cmult21} {iopath_Amult15_Cmult22} {iopath_Amult15_Cmult23} {iopath_Amult15_Cmult24} {iopath_Amult15_Cmult25} {iopath_Amult15_Cmult26} {iopath_Amult15_Cmult27} {iopath_Amult15_Cmult28} {iopath_Amult15_Cmult29} {iopath_Amult15_Cmult30} {iopath_Amult15_Cmult31} {iopath_Amult15_Cmult32} {iopath_Amult15_Cmult33} {iopath_Amult15_Cmult34} {iopath_Amult15_Cmult35} {iopath_Amult15_Cmult36} {iopath_Amult15_Cmult37} {iopath_Amult15_Cmult38} {iopath_Amult15_Cmult39} {iopath_Amult15_Cmult40} {iopath_Amult15_Cmult41} {iopath_Amult15_Cmult42} {iopath_Amult15_Cmult43} {iopath_Amult15_Cmult44} {iopath_Amult15_Cmult45} {iopath_Amult15_Cmult46} {iopath_Amult15_Cmult47} {iopath_Amult15_Cmult48} {iopath_Amult15_Cmult49} {iopath_Amult15_Cmult50} {iopath_Amult15_Cmult51} {iopath_Amult15_Cmult52} {iopath_Amult15_Cmult53} {iopath_Amult15_Cmult54} {iopath_Amult15_Cmult55} {iopath_Amult15_Cmult56} {iopath_Amult15_Cmult57} {iopath_Amult15_Cmult58} {iopath_Amult15_Cmult59} {iopath_Amult15_Cmult60} {iopath_Amult15_Cmult61} {iopath_Amult15_Cmult62} {iopath_Amult15_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult16_Cmult16} {iopath_Amult16_Cmult17} {iopath_Amult16_Cmult18} {iopath_Amult16_Cmult19} {iopath_Amult16_Cmult20} {iopath_Amult16_Cmult21} {iopath_Amult16_Cmult22} {iopath_Amult16_Cmult23} {iopath_Amult16_Cmult24} {iopath_Amult16_Cmult25} {iopath_Amult16_Cmult26} {iopath_Amult16_Cmult27} {iopath_Amult16_Cmult28} {iopath_Amult16_Cmult29} {iopath_Amult16_Cmult30} {iopath_Amult16_Cmult31} {iopath_Amult16_Cmult32} {iopath_Amult16_Cmult33} {iopath_Amult16_Cmult34} {iopath_Amult16_Cmult35} {iopath_Amult16_Cmult36} {iopath_Amult16_Cmult37} {iopath_Amult16_Cmult38} {iopath_Amult16_Cmult39} {iopath_Amult16_Cmult40} {iopath_Amult16_Cmult41} {iopath_Amult16_Cmult42} {iopath_Amult16_Cmult43} {iopath_Amult16_Cmult44} {iopath_Amult16_Cmult45} {iopath_Amult16_Cmult46} {iopath_Amult16_Cmult47} {iopath_Amult16_Cmult48} {iopath_Amult16_Cmult49} {iopath_Amult16_Cmult50} {iopath_Amult16_Cmult51} {iopath_Amult16_Cmult52} {iopath_Amult16_Cmult53} {iopath_Amult16_Cmult54} {iopath_Amult16_Cmult55} {iopath_Amult16_Cmult56} {iopath_Amult16_Cmult57} {iopath_Amult16_Cmult58} {iopath_Amult16_Cmult59} {iopath_Amult16_Cmult60} {iopath_Amult16_Cmult61} {iopath_Amult16_Cmult62} {iopath_Amult16_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult17_Cmult17} {iopath_Amult17_Cmult18} {iopath_Amult17_Cmult19} {iopath_Amult17_Cmult20} {iopath_Amult17_Cmult21} {iopath_Amult17_Cmult22} {iopath_Amult17_Cmult23} {iopath_Amult17_Cmult24} {iopath_Amult17_Cmult25} {iopath_Amult17_Cmult26} {iopath_Amult17_Cmult27} {iopath_Amult17_Cmult28} {iopath_Amult17_Cmult29} {iopath_Amult17_Cmult30} {iopath_Amult17_Cmult31} {iopath_Amult17_Cmult32} {iopath_Amult17_Cmult33} {iopath_Amult17_Cmult34} {iopath_Amult17_Cmult35} {iopath_Amult17_Cmult36} {iopath_Amult17_Cmult37} {iopath_Amult17_Cmult38} {iopath_Amult17_Cmult39} {iopath_Amult17_Cmult40} {iopath_Amult17_Cmult41} {iopath_Amult17_Cmult42} {iopath_Amult17_Cmult43} {iopath_Amult17_Cmult44} {iopath_Amult17_Cmult45} {iopath_Amult17_Cmult46} {iopath_Amult17_Cmult47} {iopath_Amult17_Cmult48} {iopath_Amult17_Cmult49} {iopath_Amult17_Cmult50} {iopath_Amult17_Cmult51} {iopath_Amult17_Cmult52} {iopath_Amult17_Cmult53} {iopath_Amult17_Cmult54} {iopath_Amult17_Cmult55} {iopath_Amult17_Cmult56} {iopath_Amult17_Cmult57} {iopath_Amult17_Cmult58} {iopath_Amult17_Cmult59} {iopath_Amult17_Cmult60} {iopath_Amult17_Cmult61} {iopath_Amult17_Cmult62} {iopath_Amult17_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult18_Cmult18} {iopath_Amult18_Cmult19} {iopath_Amult18_Cmult20} {iopath_Amult18_Cmult21} {iopath_Amult18_Cmult22} {iopath_Amult18_Cmult23} {iopath_Amult18_Cmult24} {iopath_Amult18_Cmult25} {iopath_Amult18_Cmult26} {iopath_Amult18_Cmult27} {iopath_Amult18_Cmult28} {iopath_Amult18_Cmult29} {iopath_Amult18_Cmult30} {iopath_Amult18_Cmult31} {iopath_Amult18_Cmult32} {iopath_Amult18_Cmult33} {iopath_Amult18_Cmult34} {iopath_Amult18_Cmult35} {iopath_Amult18_Cmult36} {iopath_Amult18_Cmult37} {iopath_Amult18_Cmult38} {iopath_Amult18_Cmult39} {iopath_Amult18_Cmult40} {iopath_Amult18_Cmult41} {iopath_Amult18_Cmult42} {iopath_Amult18_Cmult43} {iopath_Amult18_Cmult44} {iopath_Amult18_Cmult45} {iopath_Amult18_Cmult46} {iopath_Amult18_Cmult47} {iopath_Amult18_Cmult48} {iopath_Amult18_Cmult49} {iopath_Amult18_Cmult50} {iopath_Amult18_Cmult51} {iopath_Amult18_Cmult52} {iopath_Amult18_Cmult53} {iopath_Amult18_Cmult54} {iopath_Amult18_Cmult55} {iopath_Amult18_Cmult56} {iopath_Amult18_Cmult57} {iopath_Amult18_Cmult58} {iopath_Amult18_Cmult59} {iopath_Amult18_Cmult60} {iopath_Amult18_Cmult61} {iopath_Amult18_Cmult62} {iopath_Amult18_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult19_Cmult19} {iopath_Amult19_Cmult20} {iopath_Amult19_Cmult21} {iopath_Amult19_Cmult22} {iopath_Amult19_Cmult23} {iopath_Amult19_Cmult24} {iopath_Amult19_Cmult25} {iopath_Amult19_Cmult26} {iopath_Amult19_Cmult27} {iopath_Amult19_Cmult28} {iopath_Amult19_Cmult29} {iopath_Amult19_Cmult30} {iopath_Amult19_Cmult31} {iopath_Amult19_Cmult32} {iopath_Amult19_Cmult33} {iopath_Amult19_Cmult34} {iopath_Amult19_Cmult35} {iopath_Amult19_Cmult36} {iopath_Amult19_Cmult37} {iopath_Amult19_Cmult38} {iopath_Amult19_Cmult39} {iopath_Amult19_Cmult40} {iopath_Amult19_Cmult41} {iopath_Amult19_Cmult42} {iopath_Amult19_Cmult43} {iopath_Amult19_Cmult44} {iopath_Amult19_Cmult45} {iopath_Amult19_Cmult46} {iopath_Amult19_Cmult47} {iopath_Amult19_Cmult48} {iopath_Amult19_Cmult49} {iopath_Amult19_Cmult50} {iopath_Amult19_Cmult51} {iopath_Amult19_Cmult52} {iopath_Amult19_Cmult53} {iopath_Amult19_Cmult54} {iopath_Amult19_Cmult55} {iopath_Amult19_Cmult56} {iopath_Amult19_Cmult57} {iopath_Amult19_Cmult58} {iopath_Amult19_Cmult59} {iopath_Amult19_Cmult60} {iopath_Amult19_Cmult61} {iopath_Amult19_Cmult62} {iopath_Amult19_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult20_Cmult20} {iopath_Amult20_Cmult21} {iopath_Amult20_Cmult22} {iopath_Amult20_Cmult23} {iopath_Amult20_Cmult24} {iopath_Amult20_Cmult25} {iopath_Amult20_Cmult26} {iopath_Amult20_Cmult27} {iopath_Amult20_Cmult28} {iopath_Amult20_Cmult29} {iopath_Amult20_Cmult30} {iopath_Amult20_Cmult31} {iopath_Amult20_Cmult32} {iopath_Amult20_Cmult33} {iopath_Amult20_Cmult34} {iopath_Amult20_Cmult35} {iopath_Amult20_Cmult36} {iopath_Amult20_Cmult37} {iopath_Amult20_Cmult38} {iopath_Amult20_Cmult39} {iopath_Amult20_Cmult40} {iopath_Amult20_Cmult41} {iopath_Amult20_Cmult42} {iopath_Amult20_Cmult43} {iopath_Amult20_Cmult44} {iopath_Amult20_Cmult45} {iopath_Amult20_Cmult46} {iopath_Amult20_Cmult47} {iopath_Amult20_Cmult48} {iopath_Amult20_Cmult49} {iopath_Amult20_Cmult50} {iopath_Amult20_Cmult51} {iopath_Amult20_Cmult52} {iopath_Amult20_Cmult53} {iopath_Amult20_Cmult54} {iopath_Amult20_Cmult55} {iopath_Amult20_Cmult56} {iopath_Amult20_Cmult57} {iopath_Amult20_Cmult58} {iopath_Amult20_Cmult59} {iopath_Amult20_Cmult60} {iopath_Amult20_Cmult61} {iopath_Amult20_Cmult62} {iopath_Amult20_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult21_Cmult21} {iopath_Amult21_Cmult22} {iopath_Amult21_Cmult23} {iopath_Amult21_Cmult24} {iopath_Amult21_Cmult25} {iopath_Amult21_Cmult26} {iopath_Amult21_Cmult27} {iopath_Amult21_Cmult28} {iopath_Amult21_Cmult29} {iopath_Amult21_Cmult30} {iopath_Amult21_Cmult31} {iopath_Amult21_Cmult32} {iopath_Amult21_Cmult33} {iopath_Amult21_Cmult34} {iopath_Amult21_Cmult35} {iopath_Amult21_Cmult36} {iopath_Amult21_Cmult37} {iopath_Amult21_Cmult38} {iopath_Amult21_Cmult39} {iopath_Amult21_Cmult40} {iopath_Amult21_Cmult41} {iopath_Amult21_Cmult42} {iopath_Amult21_Cmult43} {iopath_Amult21_Cmult44} {iopath_Amult21_Cmult45} {iopath_Amult21_Cmult46} {iopath_Amult21_Cmult47} {iopath_Amult21_Cmult48} {iopath_Amult21_Cmult49} {iopath_Amult21_Cmult50} {iopath_Amult21_Cmult51} {iopath_Amult21_Cmult52} {iopath_Amult21_Cmult53} {iopath_Amult21_Cmult54} {iopath_Amult21_Cmult55} {iopath_Amult21_Cmult56} {iopath_Amult21_Cmult57} {iopath_Amult21_Cmult58} {iopath_Amult21_Cmult59} {iopath_Amult21_Cmult60} {iopath_Amult21_Cmult61} {iopath_Amult21_Cmult62} {iopath_Amult21_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult22_Cmult22} {iopath_Amult22_Cmult23} {iopath_Amult22_Cmult24} {iopath_Amult22_Cmult25} {iopath_Amult22_Cmult26} {iopath_Amult22_Cmult27} {iopath_Amult22_Cmult28} {iopath_Amult22_Cmult29} {iopath_Amult22_Cmult30} {iopath_Amult22_Cmult31} {iopath_Amult22_Cmult32} {iopath_Amult22_Cmult33} {iopath_Amult22_Cmult34} {iopath_Amult22_Cmult35} {iopath_Amult22_Cmult36} {iopath_Amult22_Cmult37} {iopath_Amult22_Cmult38} {iopath_Amult22_Cmult39} {iopath_Amult22_Cmult40} {iopath_Amult22_Cmult41} {iopath_Amult22_Cmult42} {iopath_Amult22_Cmult43} {iopath_Amult22_Cmult44} {iopath_Amult22_Cmult45} {iopath_Amult22_Cmult46} {iopath_Amult22_Cmult47} {iopath_Amult22_Cmult48} {iopath_Amult22_Cmult49} {iopath_Amult22_Cmult50} {iopath_Amult22_Cmult51} {iopath_Amult22_Cmult52} {iopath_Amult22_Cmult53} {iopath_Amult22_Cmult54} {iopath_Amult22_Cmult55} {iopath_Amult22_Cmult56} {iopath_Amult22_Cmult57} {iopath_Amult22_Cmult58} {iopath_Amult22_Cmult59} {iopath_Amult22_Cmult60} {iopath_Amult22_Cmult61} {iopath_Amult22_Cmult62} {iopath_Amult22_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult23_Cmult23} {iopath_Amult23_Cmult24} {iopath_Amult23_Cmult25} {iopath_Amult23_Cmult26} {iopath_Amult23_Cmult27} {iopath_Amult23_Cmult28} {iopath_Amult23_Cmult29} {iopath_Amult23_Cmult30} {iopath_Amult23_Cmult31} {iopath_Amult23_Cmult32} {iopath_Amult23_Cmult33} {iopath_Amult23_Cmult34} {iopath_Amult23_Cmult35} {iopath_Amult23_Cmult36} {iopath_Amult23_Cmult37} {iopath_Amult23_Cmult38} {iopath_Amult23_Cmult39} {iopath_Amult23_Cmult40} {iopath_Amult23_Cmult41} {iopath_Amult23_Cmult42} {iopath_Amult23_Cmult43} {iopath_Amult23_Cmult44} {iopath_Amult23_Cmult45} {iopath_Amult23_Cmult46} {iopath_Amult23_Cmult47} {iopath_Amult23_Cmult48} {iopath_Amult23_Cmult49} {iopath_Amult23_Cmult50} {iopath_Amult23_Cmult51} {iopath_Amult23_Cmult52} {iopath_Amult23_Cmult53} {iopath_Amult23_Cmult54} {iopath_Amult23_Cmult55} {iopath_Amult23_Cmult56} {iopath_Amult23_Cmult57} {iopath_Amult23_Cmult58} {iopath_Amult23_Cmult59} {iopath_Amult23_Cmult60} {iopath_Amult23_Cmult61} {iopath_Amult23_Cmult62} {iopath_Amult23_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult24_Cmult24} {iopath_Amult24_Cmult25} {iopath_Amult24_Cmult26} {iopath_Amult24_Cmult27} {iopath_Amult24_Cmult28} {iopath_Amult24_Cmult29} {iopath_Amult24_Cmult30} {iopath_Amult24_Cmult31} {iopath_Amult24_Cmult32} {iopath_Amult24_Cmult33} {iopath_Amult24_Cmult34} {iopath_Amult24_Cmult35} {iopath_Amult24_Cmult36} {iopath_Amult24_Cmult37} {iopath_Amult24_Cmult38} {iopath_Amult24_Cmult39} {iopath_Amult24_Cmult40} {iopath_Amult24_Cmult41} {iopath_Amult24_Cmult42} {iopath_Amult24_Cmult43} {iopath_Amult24_Cmult44} {iopath_Amult24_Cmult45} {iopath_Amult24_Cmult46} {iopath_Amult24_Cmult47} {iopath_Amult24_Cmult48} {iopath_Amult24_Cmult49} {iopath_Amult24_Cmult50} {iopath_Amult24_Cmult51} {iopath_Amult24_Cmult52} {iopath_Amult24_Cmult53} {iopath_Amult24_Cmult54} {iopath_Amult24_Cmult55} {iopath_Amult24_Cmult56} {iopath_Amult24_Cmult57} {iopath_Amult24_Cmult58} {iopath_Amult24_Cmult59} {iopath_Amult24_Cmult60} {iopath_Amult24_Cmult61} {iopath_Amult24_Cmult62} {iopath_Amult24_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult25_Cmult25} {iopath_Amult25_Cmult26} {iopath_Amult25_Cmult27} {iopath_Amult25_Cmult28} {iopath_Amult25_Cmult29} {iopath_Amult25_Cmult30} {iopath_Amult25_Cmult31} {iopath_Amult25_Cmult32} {iopath_Amult25_Cmult33} {iopath_Amult25_Cmult34} {iopath_Amult25_Cmult35} {iopath_Amult25_Cmult36} {iopath_Amult25_Cmult37} {iopath_Amult25_Cmult38} {iopath_Amult25_Cmult39} {iopath_Amult25_Cmult40} {iopath_Amult25_Cmult41} {iopath_Amult25_Cmult42} {iopath_Amult25_Cmult43} {iopath_Amult25_Cmult44} {iopath_Amult25_Cmult45} {iopath_Amult25_Cmult46} {iopath_Amult25_Cmult47} {iopath_Amult25_Cmult48} {iopath_Amult25_Cmult49} {iopath_Amult25_Cmult50} {iopath_Amult25_Cmult51} {iopath_Amult25_Cmult52} {iopath_Amult25_Cmult53} {iopath_Amult25_Cmult54} {iopath_Amult25_Cmult55} {iopath_Amult25_Cmult56} {iopath_Amult25_Cmult57} {iopath_Amult25_Cmult58} {iopath_Amult25_Cmult59} {iopath_Amult25_Cmult60} {iopath_Amult25_Cmult61} {iopath_Amult25_Cmult62} {iopath_Amult25_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult26_Cmult26} {iopath_Amult26_Cmult27} {iopath_Amult26_Cmult28} {iopath_Amult26_Cmult29} {iopath_Amult26_Cmult30} {iopath_Amult26_Cmult31} {iopath_Amult26_Cmult32} {iopath_Amult26_Cmult33} {iopath_Amult26_Cmult34} {iopath_Amult26_Cmult35} {iopath_Amult26_Cmult36} {iopath_Amult26_Cmult37} {iopath_Amult26_Cmult38} {iopath_Amult26_Cmult39} {iopath_Amult26_Cmult40} {iopath_Amult26_Cmult41} {iopath_Amult26_Cmult42} {iopath_Amult26_Cmult43} {iopath_Amult26_Cmult44} {iopath_Amult26_Cmult45} {iopath_Amult26_Cmult46} {iopath_Amult26_Cmult47} {iopath_Amult26_Cmult48} {iopath_Amult26_Cmult49} {iopath_Amult26_Cmult50} {iopath_Amult26_Cmult51} {iopath_Amult26_Cmult52} {iopath_Amult26_Cmult53} {iopath_Amult26_Cmult54} {iopath_Amult26_Cmult55} {iopath_Amult26_Cmult56} {iopath_Amult26_Cmult57} {iopath_Amult26_Cmult58} {iopath_Amult26_Cmult59} {iopath_Amult26_Cmult60} {iopath_Amult26_Cmult61} {iopath_Amult26_Cmult62} {iopath_Amult26_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult27_Cmult27} {iopath_Amult27_Cmult28} {iopath_Amult27_Cmult29} {iopath_Amult27_Cmult30} {iopath_Amult27_Cmult31} {iopath_Amult27_Cmult32} {iopath_Amult27_Cmult33} {iopath_Amult27_Cmult34} {iopath_Amult27_Cmult35} {iopath_Amult27_Cmult36} {iopath_Amult27_Cmult37} {iopath_Amult27_Cmult38} {iopath_Amult27_Cmult39} {iopath_Amult27_Cmult40} {iopath_Amult27_Cmult41} {iopath_Amult27_Cmult42} {iopath_Amult27_Cmult43} {iopath_Amult27_Cmult44} {iopath_Amult27_Cmult45} {iopath_Amult27_Cmult46} {iopath_Amult27_Cmult47} {iopath_Amult27_Cmult48} {iopath_Amult27_Cmult49} {iopath_Amult27_Cmult50} {iopath_Amult27_Cmult51} {iopath_Amult27_Cmult52} {iopath_Amult27_Cmult53} {iopath_Amult27_Cmult54} {iopath_Amult27_Cmult55} {iopath_Amult27_Cmult56} {iopath_Amult27_Cmult57} {iopath_Amult27_Cmult58} {iopath_Amult27_Cmult59} {iopath_Amult27_Cmult60} {iopath_Amult27_Cmult61} {iopath_Amult27_Cmult62} {iopath_Amult27_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult28_Cmult28} {iopath_Amult28_Cmult29} {iopath_Amult28_Cmult30} {iopath_Amult28_Cmult31} {iopath_Amult28_Cmult32} {iopath_Amult28_Cmult33} {iopath_Amult28_Cmult34} {iopath_Amult28_Cmult35} {iopath_Amult28_Cmult36} {iopath_Amult28_Cmult37} {iopath_Amult28_Cmult38} {iopath_Amult28_Cmult39} {iopath_Amult28_Cmult40} {iopath_Amult28_Cmult41} {iopath_Amult28_Cmult42} {iopath_Amult28_Cmult43} {iopath_Amult28_Cmult44} {iopath_Amult28_Cmult45} {iopath_Amult28_Cmult46} {iopath_Amult28_Cmult47} {iopath_Amult28_Cmult48} {iopath_Amult28_Cmult49} {iopath_Amult28_Cmult50} {iopath_Amult28_Cmult51} {iopath_Amult28_Cmult52} {iopath_Amult28_Cmult53} {iopath_Amult28_Cmult54} {iopath_Amult28_Cmult55} {iopath_Amult28_Cmult56} {iopath_Amult28_Cmult57} {iopath_Amult28_Cmult58} {iopath_Amult28_Cmult59} {iopath_Amult28_Cmult60} {iopath_Amult28_Cmult61} {iopath_Amult28_Cmult62} {iopath_Amult28_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult29_Cmult29} {iopath_Amult29_Cmult30} {iopath_Amult29_Cmult31} {iopath_Amult29_Cmult32} {iopath_Amult29_Cmult33} {iopath_Amult29_Cmult34} {iopath_Amult29_Cmult35} {iopath_Amult29_Cmult36} {iopath_Amult29_Cmult37} {iopath_Amult29_Cmult38} {iopath_Amult29_Cmult39} {iopath_Amult29_Cmult40} {iopath_Amult29_Cmult41} {iopath_Amult29_Cmult42} {iopath_Amult29_Cmult43} {iopath_Amult29_Cmult44} {iopath_Amult29_Cmult45} {iopath_Amult29_Cmult46} {iopath_Amult29_Cmult47} {iopath_Amult29_Cmult48} {iopath_Amult29_Cmult49} {iopath_Amult29_Cmult50} {iopath_Amult29_Cmult51} {iopath_Amult29_Cmult52} {iopath_Amult29_Cmult53} {iopath_Amult29_Cmult54} {iopath_Amult29_Cmult55} {iopath_Amult29_Cmult56} {iopath_Amult29_Cmult57} {iopath_Amult29_Cmult58} {iopath_Amult29_Cmult59} {iopath_Amult29_Cmult60} {iopath_Amult29_Cmult61} {iopath_Amult29_Cmult62} {iopath_Amult29_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult30_Cmult30} {iopath_Amult30_Cmult31} {iopath_Amult30_Cmult32} {iopath_Amult30_Cmult33} {iopath_Amult30_Cmult34} {iopath_Amult30_Cmult35} {iopath_Amult30_Cmult36} {iopath_Amult30_Cmult37} {iopath_Amult30_Cmult38} {iopath_Amult30_Cmult39} {iopath_Amult30_Cmult40} {iopath_Amult30_Cmult41} {iopath_Amult30_Cmult42} {iopath_Amult30_Cmult43} {iopath_Amult30_Cmult44} {iopath_Amult30_Cmult45} {iopath_Amult30_Cmult46} {iopath_Amult30_Cmult47} {iopath_Amult30_Cmult48} {iopath_Amult30_Cmult49} {iopath_Amult30_Cmult50} {iopath_Amult30_Cmult51} {iopath_Amult30_Cmult52} {iopath_Amult30_Cmult53} {iopath_Amult30_Cmult54} {iopath_Amult30_Cmult55} {iopath_Amult30_Cmult56} {iopath_Amult30_Cmult57} {iopath_Amult30_Cmult58} {iopath_Amult30_Cmult59} {iopath_Amult30_Cmult60} {iopath_Amult30_Cmult61} {iopath_Amult30_Cmult62} {iopath_Amult30_Cmult63} 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 {iopath_Amult31_Cmult31} {iopath_Amult31_Cmult32} {iopath_Amult31_Cmult33} {iopath_Amult31_Cmult34} {iopath_Amult31_Cmult35} {iopath_Amult31_Cmult36} {iopath_Amult31_Cmult37} {iopath_Amult31_Cmult38} {iopath_Amult31_Cmult39} {iopath_Amult31_Cmult40} {iopath_Amult31_Cmult41} {iopath_Amult31_Cmult42} {iopath_Amult31_Cmult43} {iopath_Amult31_Cmult44} {iopath_Amult31_Cmult45} {iopath_Amult31_Cmult46} {iopath_Amult31_Cmult47} {iopath_Amult31_Cmult48} {iopath_Amult31_Cmult49} {iopath_Amult31_Cmult50} {iopath_Amult31_Cmult51} {iopath_Amult31_Cmult52} {iopath_Amult31_Cmult53} {iopath_Amult31_Cmult54} {iopath_Amult31_Cmult55} {iopath_Amult31_Cmult56} {iopath_Amult31_Cmult57} {iopath_Amult31_Cmult58} {iopath_Amult31_Cmult59} {iopath_Amult31_Cmult60} {iopath_Amult31_Cmult61} {iopath_Amult31_Cmult62} {iopath_Amult31_Cmult63} ",
            "DELAY_MATRIX_Valid_mult": "1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 ",
            "DELAY_MATRIX_sel_mul_32x32": "1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 1e-10 ",
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:6.16-6.21"
          }
        },
        "Valid_mult": {
          "hide_name": 0,
          "bits": [ 66, 67 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:5.14-5.24"
          }
        },
        "sel_mul_32x32": {
          "hide_name": 0,
          "bits": [ 132 ],
          "attributes": {
            "src": "/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v:7.8-7.21"
          }
        }
      }
    }
  },
  "models": {
    "$mux:32": [
      /*   0 */ [ "port", "S", 0 ],
      /*   1 */ [ "port", "A", 0 ],
      /*   2 */ [ "port", "B", 0 ],
      /*   3 */ [ "nport", "S", 0 ],
      /*   4 */ [ "nand", 0, 2 ],
      /*   5 */ [ "nand", 1, 3 ],
      /*   6 */ [ "nand", 4, 5, "Y", 0 ],
      /*   7 */ [ "port", "A", 1 ],
      /*   8 */ [ "port", "B", 1 ],
      /*   9 */ [ "nand", 0, 8 ],
      /*  10 */ [ "nand", 3, 7 ],
      /*  11 */ [ "nand", 9, 10, "Y", 1 ],
      /*  12 */ [ "port", "A", 2 ],
      /*  13 */ [ "port", "B", 2 ],
      /*  14 */ [ "nand", 0, 13 ],
      /*  15 */ [ "nand", 3, 12 ],
      /*  16 */ [ "nand", 14, 15, "Y", 2 ],
      /*  17 */ [ "port", "A", 3 ],
      /*  18 */ [ "port", "B", 3 ],
      /*  19 */ [ "nand", 0, 18 ],
      /*  20 */ [ "nand", 3, 17 ],
      /*  21 */ [ "nand", 19, 20, "Y", 3 ],
      /*  22 */ [ "port", "A", 4 ],
      /*  23 */ [ "port", "B", 4 ],
      /*  24 */ [ "nand", 0, 23 ],
      /*  25 */ [ "nand", 3, 22 ],
      /*  26 */ [ "nand", 24, 25, "Y", 4 ],
      /*  27 */ [ "port", "A", 5 ],
      /*  28 */ [ "port", "B", 5 ],
      /*  29 */ [ "nand", 0, 28 ],
      /*  30 */ [ "nand", 3, 27 ],
      /*  31 */ [ "nand", 29, 30, "Y", 5 ],
      /*  32 */ [ "port", "A", 6 ],
      /*  33 */ [ "port", "B", 6 ],
      /*  34 */ [ "nand", 0, 33 ],
      /*  35 */ [ "nand", 3, 32 ],
      /*  36 */ [ "nand", 34, 35, "Y", 6 ],
      /*  37 */ [ "port", "A", 7 ],
      /*  38 */ [ "port", "B", 7 ],
      /*  39 */ [ "nand", 0, 38 ],
      /*  40 */ [ "nand", 3, 37 ],
      /*  41 */ [ "nand", 39, 40, "Y", 7 ],
      /*  42 */ [ "port", "A", 8 ],
      /*  43 */ [ "port", "B", 8 ],
      /*  44 */ [ "nand", 0, 43 ],
      /*  45 */ [ "nand", 3, 42 ],
      /*  46 */ [ "nand", 44, 45, "Y", 8 ],
      /*  47 */ [ "port", "A", 9 ],
      /*  48 */ [ "port", "B", 9 ],
      /*  49 */ [ "nand", 0, 48 ],
      /*  50 */ [ "nand", 3, 47 ],
      /*  51 */ [ "nand", 49, 50, "Y", 9 ],
      /*  52 */ [ "port", "A", 10 ],
      /*  53 */ [ "port", "B", 10 ],
      /*  54 */ [ "nand", 0, 53 ],
      /*  55 */ [ "nand", 3, 52 ],
      /*  56 */ [ "nand", 54, 55, "Y", 10 ],
      /*  57 */ [ "port", "A", 11 ],
      /*  58 */ [ "port", "B", 11 ],
      /*  59 */ [ "nand", 0, 58 ],
      /*  60 */ [ "nand", 3, 57 ],
      /*  61 */ [ "nand", 59, 60, "Y", 11 ],
      /*  62 */ [ "port", "A", 12 ],
      /*  63 */ [ "port", "B", 12 ],
      /*  64 */ [ "nand", 0, 63 ],
      /*  65 */ [ "nand", 3, 62 ],
      /*  66 */ [ "nand", 64, 65, "Y", 12 ],
      /*  67 */ [ "port", "A", 13 ],
      /*  68 */ [ "port", "B", 13 ],
      /*  69 */ [ "nand", 0, 68 ],
      /*  70 */ [ "nand", 3, 67 ],
      /*  71 */ [ "nand", 69, 70, "Y", 13 ],
      /*  72 */ [ "port", "A", 14 ],
      /*  73 */ [ "port", "B", 14 ],
      /*  74 */ [ "nand", 0, 73 ],
      /*  75 */ [ "nand", 3, 72 ],
      /*  76 */ [ "nand", 74, 75, "Y", 14 ],
      /*  77 */ [ "port", "A", 15 ],
      /*  78 */ [ "port", "B", 15 ],
      /*  79 */ [ "nand", 0, 78 ],
      /*  80 */ [ "nand", 3, 77 ],
      /*  81 */ [ "nand", 79, 80, "Y", 15 ],
      /*  82 */ [ "port", "A", 16 ],
      /*  83 */ [ "port", "B", 16 ],
      /*  84 */ [ "nand", 0, 83 ],
      /*  85 */ [ "nand", 3, 82 ],
      /*  86 */ [ "nand", 84, 85, "Y", 16 ],
      /*  87 */ [ "port", "A", 17 ],
      /*  88 */ [ "port", "B", 17 ],
      /*  89 */ [ "nand", 0, 88 ],
      /*  90 */ [ "nand", 3, 87 ],
      /*  91 */ [ "nand", 89, 90, "Y", 17 ],
      /*  92 */ [ "port", "A", 18 ],
      /*  93 */ [ "port", "B", 18 ],
      /*  94 */ [ "nand", 0, 93 ],
      /*  95 */ [ "nand", 3, 92 ],
      /*  96 */ [ "nand", 94, 95, "Y", 18 ],
      /*  97 */ [ "port", "A", 19 ],
      /*  98 */ [ "port", "B", 19 ],
      /*  99 */ [ "nand", 0, 98 ],
      /* 100 */ [ "nand", 3, 97 ],
      /* 101 */ [ "nand", 99, 100, "Y", 19 ],
      /* 102 */ [ "port", "A", 20 ],
      /* 103 */ [ "port", "B", 20 ],
      /* 104 */ [ "nand", 0, 103 ],
      /* 105 */ [ "nand", 3, 102 ],
      /* 106 */ [ "nand", 104, 105, "Y", 20 ],
      /* 107 */ [ "port", "A", 21 ],
      /* 108 */ [ "port", "B", 21 ],
      /* 109 */ [ "nand", 0, 108 ],
      /* 110 */ [ "nand", 3, 107 ],
      /* 111 */ [ "nand", 109, 110, "Y", 21 ],
      /* 112 */ [ "port", "A", 22 ],
      /* 113 */ [ "port", "B", 22 ],
      /* 114 */ [ "nand", 0, 113 ],
      /* 115 */ [ "nand", 3, 112 ],
      /* 116 */ [ "nand", 114, 115, "Y", 22 ],
      /* 117 */ [ "port", "A", 23 ],
      /* 118 */ [ "port", "B", 23 ],
      /* 119 */ [ "nand", 0, 118 ],
      /* 120 */ [ "nand", 3, 117 ],
      /* 121 */ [ "nand", 119, 120, "Y", 23 ],
      /* 122 */ [ "port", "A", 24 ],
      /* 123 */ [ "port", "B", 24 ],
      /* 124 */ [ "nand", 0, 123 ],
      /* 125 */ [ "nand", 3, 122 ],
      /* 126 */ [ "nand", 124, 125, "Y", 24 ],
      /* 127 */ [ "port", "A", 25 ],
      /* 128 */ [ "port", "B", 25 ],
      /* 129 */ [ "nand", 0, 128 ],
      /* 130 */ [ "nand", 3, 127 ],
      /* 131 */ [ "nand", 129, 130, "Y", 25 ],
      /* 132 */ [ "port", "A", 26 ],
      /* 133 */ [ "port", "B", 26 ],
      /* 134 */ [ "nand", 0, 133 ],
      /* 135 */ [ "nand", 3, 132 ],
      /* 136 */ [ "nand", 134, 135, "Y", 26 ],
      /* 137 */ [ "port", "A", 27 ],
      /* 138 */ [ "port", "B", 27 ],
      /* 139 */ [ "nand", 0, 138 ],
      /* 140 */ [ "nand", 3, 137 ],
      /* 141 */ [ "nand", 139, 140, "Y", 27 ],
      /* 142 */ [ "port", "A", 28 ],
      /* 143 */ [ "port", "B", 28 ],
      /* 144 */ [ "nand", 0, 143 ],
      /* 145 */ [ "nand", 3, 142 ],
      /* 146 */ [ "nand", 144, 145, "Y", 28 ],
      /* 147 */ [ "port", "A", 29 ],
      /* 148 */ [ "port", "B", 29 ],
      /* 149 */ [ "nand", 0, 148 ],
      /* 150 */ [ "nand", 3, 147 ],
      /* 151 */ [ "nand", 149, 150, "Y", 29 ],
      /* 152 */ [ "port", "A", 30 ],
      /* 153 */ [ "port", "B", 30 ],
      /* 154 */ [ "nand", 0, 153 ],
      /* 155 */ [ "nand", 3, 152 ],
      /* 156 */ [ "nand", 154, 155, "Y", 30 ],
      /* 157 */ [ "port", "A", 31 ],
      /* 158 */ [ "port", "B", 31 ],
      /* 159 */ [ "nand", 0, 158 ],
      /* 160 */ [ "nand", 3, 157 ],
      /* 161 */ [ "nand", 159, 160, "Y", 31 ]
    ],
    "$eq:1U:1U:1": [
      /*   0 */ [ "port", "A", 0 ],
      /*   1 */ [ "port", "B", 0 ],
      /*   2 */ [ "nport", "B", 0 ],
      /*   3 */ [ "nport", "A", 0 ],
      /*   4 */ [ "nand", 2, 3 ],
      /*   5 */ [ "nand", 0, 1 ],
      /*   6 */ [ "nand", 4, 5, "Y", 0 ]
    ]
  }
}
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v; proc; cd MULT; select -write /tmp/tmpp6edl7hp c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] c:* %d x:* %i']
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v; proc; cd MULT; select -write /tmp/tmpkcmlnquc Amult %co* o:* %i Amult %d']
stderr   =======================================================================
Warning: Selection "Amult" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v; proc; cd MULT; select -write /tmp/tmpamuwggc2 Bmult %co* o:* %i Bmult %d']
stderr   =======================================================================
Warning: Selection "Bmult" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v; proc; cd MULT; select -write /tmp/tmppht10oq6 Cmult %co* o:* %i Cmult %d']
stderr   =======================================================================
Warning: Selection "Cmult" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v; proc; cd MULT; select -write /tmp/tmp0jpe6gox Valid_mult %co* o:* %i Valid_mult %d']
stderr   =======================================================================
Warning: Selection "Valid_mult" did not match any object.
exitcode =======================================================================
0
================================================================================

command  =======================================================================
['/opt/openfpga/bin/yosys', '-e', "wire '[^']*' is assigned in a block", '-q', '-p', 'read_verilog   /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/primitives/mult/mult.sim.v; proc; cd MULT; select -write /tmp/tmpqytwuvch sel_mul_32x32 %co* o:* %i sel_mul_32x32 %d']
stderr   =======================================================================
Warning: Selection "sel_mul_32x32" did not match any object.
exitcode =======================================================================
0
================================================================================

make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Built target file_quicklogic_primitives_mult_mult.model.xml
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_arch.xml.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_arch.xml.dir/depend
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cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_arch.xml.dir/DependInfo.cmake --color=
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cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && /opt/openfpga/vtr/_pyenv/bin/python3 /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/arch_import.py --vpr-db db_vpr.pickle --arch-out arch.xml --device ql-eos-s3
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make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/CMakeFiles/vtr_xml_utils.dir/DependInfo.cmake --color=
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make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_arch.merged.xml.dir/DependInfo.cmake --color=
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[100%] Generating arch.merged.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/vtr-xml-utils/: /opt/openfpga/vtr/_pyenv/bin/python3 -m vtr_xml_utils arch.xml -o /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/arch.merged.xml
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Built target file_quicklogic_devices_ql-eos-s3-virt_arch.merged.xml
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_arch.unique_pack.xml.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_arch.unique_pack.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_arch.unique_pack.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_arch.unique_pack.xml.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_arch.unique_pack.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Generating arch.unique_pack.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && /opt/openfpga/vtr/_pyenv/bin/python3 /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/utils/specialize_carrychains.py --input_arch_xml /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/arch.merged.xml > arch.unique_pack.xml
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Built target file_quicklogic_devices_ql-eos-s3-virt_arch.unique_pack.xml
make -f CMakeFiles/sdf_timing.dir/build.make CMakeFiles/sdf_timing.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/CMakeFiles/sdf_timing.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f CMakeFiles/sdf_timing.dir/build.make CMakeFiles/sdf_timing.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make[2]: Nothing to be done for 'CMakeFiles/sdf_timing.dir/build'.
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Built target sdf_timing
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_MULT_ss_0p990v_m040c.sdf.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_MULT_ss_0p990v_m040c.sdf.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_MULT_ss_0p990v_m040c.sdf.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_MULT_ss_0p990v_m040c.sdf.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_MULT_ss_0p990v_m040c.sdf.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Generating sdf/MULT_ss_0p990v_m040c.sdf
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && /usr/bin/cmake -E make_directory sdf
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && /usr/bin/cmake -E env PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/quicklogic-timings-importer/quicklogic_timings_importer:YTHONPATH /opt/openfpga/vtr/_pyenv/bin/python3 /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/quicklogic-timings-importer/quicklogic_timings_importer/quicklogic_timings_importer.py /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/ql-eos-s3/Timing\ Data\ Files//MULT_ss_0p990v_m040c.lib sdf/MULT_ss_0p990v_m040c.sdf
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Built target file_quicklogic_devices_ql-eos-s3-virt_sdf_MULT_ss_0p990v_m040c.sdf
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_LOGIC_ss_0p990v_m040c.sdf.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_LOGIC_ss_0p990v_m040c.sdf.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_LOGIC_ss_0p990v_m040c.sdf.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_LOGIC_ss_0p990v_m040c.sdf.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_LOGIC_ss_0p990v_m040c.sdf.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Generating sdf/LOGIC_ss_0p990v_m040c.sdf
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && /usr/bin/cmake -E make_directory sdf
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && /usr/bin/cmake -E env PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/quicklogic-timings-importer/quicklogic_timings_importer:YTHONPATH /opt/openfpga/vtr/_pyenv/bin/python3 /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/quicklogic-timings-importer/quicklogic_timings_importer/quicklogic_timings_importer.py /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/ql-eos-s3/Timing\ Data\ Files//LOGIC_ss_0p990v_m040c.lib sdf/LOGIC_ss_0p990v_m040c.sdf
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Built target file_quicklogic_devices_ql-eos-s3-virt_sdf_LOGIC_ss_0p990v_m040c.sdf
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_GMUX_ss_0p990v_m040c.sdf.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_GMUX_ss_0p990v_m040c.sdf.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_GMUX_ss_0p990v_m040c.sdf.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_GMUX_ss_0p990v_m040c.sdf.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_GMUX_ss_0p990v_m040c.sdf.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Generating sdf/GMUX_ss_0p990v_m040c.sdf
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && /usr/bin/cmake -E make_directory sdf
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && /usr/bin/cmake -E env PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/quicklogic-timings-importer/quicklogic_timings_importer:YTHONPATH /opt/openfpga/vtr/_pyenv/bin/python3 /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/quicklogic-timings-importer/quicklogic_timings_importer/quicklogic_timings_importer.py /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/ql-eos-s3/Timing\ Data\ Files//GMUX_ss_0p990v_m040c.lib sdf/GMUX_ss_0p990v_m040c.sdf
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Built target file_quicklogic_devices_ql-eos-s3-virt_sdf_GMUX_ss_0p990v_m040c.sdf
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_CLKPAD_ss_0p990v_m040c.sdf.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_CLKPAD_ss_0p990v_m040c.sdf.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_CLKPAD_ss_0p990v_m040c.sdf.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_CLKPAD_ss_0p990v_m040c.sdf.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_CLKPAD_ss_0p990v_m040c.sdf.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Generating sdf/CLKPAD_ss_0p990v_m040c.sdf
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && /usr/bin/cmake -E make_directory sdf
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && /usr/bin/cmake -E env PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/quicklogic-timings-importer/quicklogic_timings_importer:YTHONPATH /opt/openfpga/vtr/_pyenv/bin/python3 /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/quicklogic-timings-importer/quicklogic_timings_importer/quicklogic_timings_importer.py /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/ql-eos-s3/Timing\ Data\ Files//CLKPAD_ss_0p990v_m040c.lib sdf/CLKPAD_ss_0p990v_m040c.sdf
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Built target file_quicklogic_devices_ql-eos-s3-virt_sdf_CLKPAD_ss_0p990v_m040c.sdf
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_RAM_ss_0p990v_m040c.sdf.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_RAM_ss_0p990v_m040c.sdf.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_RAM_ss_0p990v_m040c.sdf.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_RAM_ss_0p990v_m040c.sdf.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_RAM_ss_0p990v_m040c.sdf.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Generating sdf/RAM_ss_0p990v_m040c.sdf
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && /usr/bin/cmake -E make_directory sdf
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && /usr/bin/cmake -E env PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/quicklogic-timings-importer/quicklogic_timings_importer:YTHONPATH /opt/openfpga/vtr/_pyenv/bin/python3 /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/quicklogic-timings-importer/quicklogic_timings_importer/quicklogic_timings_importer.py /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/ql-eos-s3/Timing\ Data\ Files//RAM_ss_0p990v_m040c.lib sdf/RAM_ss_0p990v_m040c.sdf
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Built target file_quicklogic_devices_ql-eos-s3-virt_sdf_RAM_ss_0p990v_m040c.sdf
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_QLAL4S3B_ss_0p990v_m040c.sdf.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_QLAL4S3B_ss_0p990v_m040c.sdf.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_QLAL4S3B_ss_0p990v_m040c.sdf.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_QLAL4S3B_ss_0p990v_m040c.sdf.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_QLAL4S3B_ss_0p990v_m040c.sdf.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Generating sdf/QLAL4S3B_ss_0p990v_m040c.sdf
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && /usr/bin/cmake -E make_directory sdf
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && /usr/bin/cmake -E env PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/quicklogic-timings-importer/quicklogic_timings_importer:YTHONPATH /opt/openfpga/vtr/_pyenv/bin/python3 /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/quicklogic-timings-importer/quicklogic_timings_importer/quicklogic_timings_importer.py /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/ql-eos-s3/Timing\ Data\ Files//QLAL4S3B_ss_0p990v_m040c.lib sdf/QLAL4S3B_ss_0p990v_m040c.sdf
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Built target file_quicklogic_devices_ql-eos-s3-virt_sdf_QLAL4S3B_ss_0p990v_m040c.sdf
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_BIDIR_ss_0p990v_m040c_Cmax_2P97V.sdf.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_BIDIR_ss_0p990v_m040c_Cmax_2P97V.sdf.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_BIDIR_ss_0p990v_m040c_Cmax_2P97V.sdf.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_BIDIR_ss_0p990v_m040c_Cmax_2P97V.sdf.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_BIDIR_ss_0p990v_m040c_Cmax_2P97V.sdf.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Generating sdf/BIDIR_ss_0p990v_m040c_Cmax_2P97V.sdf
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && /usr/bin/cmake -E make_directory sdf
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && /usr/bin/cmake -E env PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/quicklogic-timings-importer/quicklogic_timings_importer:YTHONPATH /opt/openfpga/vtr/_pyenv/bin/python3 /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/quicklogic-timings-importer/quicklogic_timings_importer/quicklogic_timings_importer.py /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/ql-eos-s3/Timing\ Data\ Files//BIDIR_ss_0p990v_m040c_Cmax_2P97V.lib sdf/BIDIR_ss_0p990v_m040c_Cmax_2P97V.sdf
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Built target file_quicklogic_devices_ql-eos-s3-virt_sdf_BIDIR_ss_0p990v_m040c_Cmax_2P97V.sdf
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_SDIOMUX_ss_0p990v_m040c_Cmax_2P97V.sdf.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_SDIOMUX_ss_0p990v_m040c_Cmax_2P97V.sdf.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_SDIOMUX_ss_0p990v_m040c_Cmax_2P97V.sdf.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_SDIOMUX_ss_0p990v_m040c_Cmax_2P97V.sdf.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_SDIOMUX_ss_0p990v_m040c_Cmax_2P97V.sdf.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Generating sdf/SDIOMUX_ss_0p990v_m040c_Cmax_2P97V.sdf
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && /usr/bin/cmake -E make_directory sdf
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && /usr/bin/cmake -E env PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/quicklogic-timings-importer/quicklogic_timings_importer:YTHONPATH /opt/openfpga/vtr/_pyenv/bin/python3 /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/quicklogic-timings-importer/quicklogic_timings_importer/quicklogic_timings_importer.py /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/ql-eos-s3/Timing\ Data\ Files//SDIOMUX_ss_0p990v_m040c_Cmax_2P97V.lib sdf/SDIOMUX_ss_0p990v_m040c_Cmax_2P97V.sdf
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Built target file_quicklogic_devices_ql-eos-s3-virt_sdf_SDIOMUX_ss_0p990v_m040c_Cmax_2P97V.sdf
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_CAND_ss_0p990v_m040c.sdf.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_CAND_ss_0p990v_m040c.sdf.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_CAND_ss_0p990v_m040c.sdf.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_CAND_ss_0p990v_m040c.sdf.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_CAND_ss_0p990v_m040c.sdf.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Generating sdf/CAND_ss_0p990v_m040c.sdf
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && /usr/bin/cmake -E make_directory sdf
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && /usr/bin/cmake -E env PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/quicklogic-timings-importer/quicklogic_timings_importer:YTHONPATH /opt/openfpga/vtr/_pyenv/bin/python3 /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/quicklogic-timings-importer/quicklogic_timings_importer/quicklogic_timings_importer.py /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/ql-eos-s3/Timing\ Data\ Files//CAND_ss_0p990v_m040c.lib sdf/CAND_ss_0p990v_m040c.sdf
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Built target file_quicklogic_devices_ql-eos-s3-virt_sdf_CAND_ss_0p990v_m040c.sdf
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_QMUX_ss_0p990v_m040c.sdf.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_QMUX_ss_0p990v_m040c.sdf.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_QMUX_ss_0p990v_m040c.sdf.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_QMUX_ss_0p990v_m040c.sdf.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_sdf_QMUX_ss_0p990v_m040c.sdf.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Generating sdf/QMUX_ss_0p990v_m040c.sdf
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && /usr/bin/cmake -E make_directory sdf
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && /usr/bin/cmake -E env PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/quicklogic-timings-importer/quicklogic_timings_importer:YTHONPATH /opt/openfpga/vtr/_pyenv/bin/python3 /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/utils/quicklogic-timings-importer/quicklogic_timings_importer/quicklogic_timings_importer.py /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/ql-eos-s3/Timing\ Data\ Files//QMUX_ss_0p990v_m040c.lib sdf/QMUX_ss_0p990v_m040c.sdf
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Built target file_quicklogic_devices_ql-eos-s3-virt_sdf_QMUX_ss_0p990v_m040c.sdf
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_arch.timing.xml.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_arch.timing.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_arch.timing.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_arch.timing.xml.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/file_quicklogic_devices_ql-eos-s3-virt_arch.timing.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Generating arch.timing.xml
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt && /usr/bin/cmake -E env PYTHONPATH=/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/third_party/python-sdf-timing:YTHONPATH /opt/openfpga/vtr/_pyenv/bin/python3 /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/utils/update_arch_timings.py --sdf_dir sdf --bels_map /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/ql-eos-s3-bels.json --out_arch /dev/stdout --input_arch /dev/stdin < /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/arch.unique_pack.xml > arch.timing.xml
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Built target file_quicklogic_devices_ql-eos-s3-virt_arch.timing.xml
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/ql-eos-s3-virt.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/ql-eos-s3-virt.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/CMakeFiles/ql-eos-s3-virt.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/devices/ql-eos-s3-virt/CMakeFiles/ql-eos-s3-virt.dir/build.make quicklogic/devices/ql-eos-s3-virt/CMakeFiles/ql-eos-s3-virt.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make[2]: Nothing to be done for 'quicklogic/devices/ql-eos-s3-virt/CMakeFiles/ql-eos-s3-virt.dir/build'.
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Built target ql-eos-s3-virt
make -f quicklogic/devices/CMakeFiles/file_quicklogic_devices_rr_graph_ql-eos-s3_wlcsp.rr_graph.virt.xml.dir/build.make quicklogic/devices/CMakeFiles/file_quicklogic_devices_rr_graph_ql-eos-s3_wlcsp.rr_graph.virt.xml.dir/depend
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/devices /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/CMakeFiles/file_quicklogic_devices_rr_graph_ql-eos-s3_wlcsp.rr_graph.virt.xml.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make -f quicklogic/devices/CMakeFiles/file_quicklogic_devices_rr_graph_ql-eos-s3_wlcsp.rr_graph.virt.xml.dir/build.make quicklogic/devices/CMakeFiles/file_quicklogic_devices_rr_graph_ql-eos-s3_wlcsp.rr_graph.virt.xml.dir/build
make[2]: Entering directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
[100%] Generating rr_graph_ql-eos-s3_wlcsp.rr_graph.virt.xml, rr_graph_ql-eos-s3_wlcsp.virt.out
cd /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices && /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/utils/quiet_cmd.sh /opt/openfpga/vtr/bin/vpr /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/arch.timing.xml --device ql-eos-s3 /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/passthrough.eblif --place_algorithm bounding_box --enable_timing_computations off --route_chan_width 6 --echo_file on --min_route_chan_width_hint 1 --write_rr_graph /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/rr_graph_ql-eos-s3_wlcsp.rr_graph.virt.xml --outfile_prefix ql-eos-s3_wlcsp --pack --pack_verbosity 100 --place --allow_dangling_combinational_nodes on
+++ basename /opt/openfpga/vtr/bin/vpr
++ mktemp vpr.output.XXX
+ OUTPUT=vpr.output.sg9
+ set +e
+ /opt/openfpga/vtr/bin/vpr /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/arch.timing.xml --device ql-eos-s3 /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/passthrough.eblif --place_algorithm bounding_box --enable_timing_computations off --route_chan_width 6 --echo_file on --min_route_chan_width_hint 1 --write_rr_graph /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/rr_graph_ql-eos-s3_wlcsp.rr_graph.virt.xml --outfile_prefix ql-eos-s3_wlcsp --pack --pack_verbosity 100 --place --allow_dangling_combinational_nodes on
+ RESULT=1
+ set -e
+ [[ 1 -ne 0 ]]
+ cat vpr.output.sg9
VPR FPGA Placement and Routing.
Version: 8.1.0-dev+8980e4621
Revision: v8.0.0-rc2-4003-g8980e4621
Compiled: 2020-06-05T11:01:13
Compiler: GNU 9.2.0 on Linux-5.1.4-gentoo x86_64
Build Info: Release IPO VTR_ASSERT_LEVEL=2

University of Toronto
verilogtorouting.org
vtr-users@googlegroups.com
This is free open source code under MIT license.

VPR was run with the following command-line:
/opt/openfpga/vtr/bin/vpr /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/arch.timing.xml --device ql-eos-s3 /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/quicklogic/passthrough.eblif --place_algorithm bounding_box --enable_timing_computations off --route_chan_width 6 --echo_file on --min_route_chan_width_hint 1 --write_rr_graph /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/rr_graph_ql-eos-s3_wlcsp.rr_graph.virt.xml --outfile_prefix ql-eos-s3_wlcsp --pack --pack_verbosity 100 --place --allow_dangling_combinational_nodes on


Architecture file: /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/arch.timing.xml
Circuit name: passthrough

# Loading Architecture Description
Warning 1: Model 'T_FRAG' input port 'XSL' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 2: Model 'T_FRAG' input port 'XB2' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 3: Model 'T_FRAG' input port 'XB1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 4: Model 'T_FRAG' input port 'XAB' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 5: Model 'T_FRAG' input port 'XA2' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 6: Model 'T_FRAG' input port 'XA1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 7: Model 'T_FRAG' input port 'TBS' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 8: Model 'T_FRAG' output port 'XZ' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 9: Model 'F_FRAG' input port 'FS' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 10: Model 'F_FRAG' input port 'F2' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 11: Model 'F_FRAG' input port 'F1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 12: Model 'F_FRAG' output port 'FZ' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 13: Model 'Q_FRAG' input port 'QST' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 14: Model 'Q_FRAG' input port 'QRT' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 15: Model 'Q_FRAG' input port 'QEN' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 16: Model 'Q_FRAG' input port 'QDS' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 17: Model 'Q_FRAG' input port 'QDI' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 18: Model 'Q_FRAG' input port 'CZI' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 19: Model 'Q_FRAG' output port 'QZ' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 20: Model 'ASSP' input port 'WBs_RD_DAT' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 21: Model 'ASSP' input port 'WBs_ACK' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 22: Model 'ASSP' input port 'Sys_PSel' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 23: Model 'ASSP' input port 'SPIm_Paddr' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 24: Model 'ASSP' input port 'SPIm_PWrite' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 25: Model 'ASSP' input port 'SPIm_PWdata' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 26: Model 'ASSP' input port 'SPIm_PEnable' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 27: Model 'ASSP' input port 'SDMA_Sreq' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 28: Model 'ASSP' input port 'SDMA_Req' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 29: Model 'ASSP' input port 'FB_msg_out' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 30: Model 'ASSP' input port 'FB_PKfbSOF' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 31: Model 'ASSP' input port 'FB_PKfbPush' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 32: Model 'ASSP' input port 'FB_PKfbEOF' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 33: Model 'ASSP' input port 'FB_PKfbData' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 34: Model 'ASSP' input port 'FB_Int_Clr' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 35: Model 'ASSP' input port 'FB_Busy' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 36: Model 'ASSP' input port 'Device_ID' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 37: Model 'ASSP' output port 'WBs_WR_DAT' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 38: Model 'ASSP' output port 'WBs_WE' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 39: Model 'ASSP' output port 'WBs_STB' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 40: Model 'ASSP' output port 'WBs_RD' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 41: Model 'ASSP' output port 'WBs_CYC' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 42: Model 'ASSP' output port 'WBs_BYTE_STB' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 43: Model 'ASSP' output port 'WBs_ADR' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 44: Model 'ASSP' output port 'WB_RST' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 45: Model 'ASSP' output port 'TimeStamp' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 46: Model 'ASSP' output port 'Sys_Pclk_Rst' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 47: Model 'ASSP' output port 'Sys_PKfb_Rst' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 48: Model 'ASSP' output port 'Sys_Clk1_Rst' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 49: Model 'ASSP' output port 'Sys_Clk0_Rst' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 50: Model 'ASSP' output port 'Sensor_Int' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 51: Model 'ASSP' output port 'SPIm_Prdata' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 52: Model 'ASSP' output port 'SPIm_PSlvErr' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 53: Model 'ASSP' output port 'SPIm_PReady' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 54: Model 'ASSP' output port 'SDMA_Done' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 55: Model 'ASSP' output port 'SDMA_Active' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 56: Model 'ASSP' output port 'FB_Start' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 57: Model 'ASSP' output port 'FB_PKfbOverflow' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 58: Model 'VCC' output port 'VCC' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 59: Model 'GND' output port 'GND' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 60: Model 'RAM' input port 'WIDTH_SELECT2_1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 61: Model 'RAM' input port 'WIDTH_SELECT2_0' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 62: Model 'RAM' input port 'WIDTH_SELECT1_1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 63: Model 'RAM' input port 'WIDTH_SELECT1_0' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 64: Model 'RAM' input port 'WEN1_1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 65: Model 'RAM' input port 'WEN1_0' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 66: Model 'RAM' input port 'WD_1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 67: Model 'RAM' input port 'WD_0' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 68: Model 'RAM' input port 'TEST1B' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 69: Model 'RAM' input port 'TEST1A' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 70: Model 'RAM' input port 'SYNC_FIFO_1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 71: Model 'RAM' input port 'SYNC_FIFO_0' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 72: Model 'RAM' input port 'SD_RB1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 73: Model 'RAM' input port 'SD' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 74: Model 'RAM' input port 'RMEB' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 75: Model 'RAM' input port 'RMEA' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 76: Model 'RAM' input port 'RMB' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 77: Model 'RAM' input port 'RMA' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 78: Model 'RAM' input port 'PIPELINE_RD_1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 79: Model 'RAM' input port 'PIPELINE_RD_0' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 80: Model 'RAM' input port 'P2_1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 81: Model 'RAM' input port 'P2_0' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 82: Model 'RAM' input port 'P1_1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 83: Model 'RAM' input port 'P1_0' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 84: Model 'RAM' input port 'LS_RB1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 85: Model 'RAM' input port 'LS' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 86: Model 'RAM' input port 'FIFO_EN_1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 87: Model 'RAM' input port 'FIFO_EN_0' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 88: Model 'RAM' input port 'DS_RB1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 89: Model 'RAM' input port 'DS' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 90: Model 'RAM' input port 'DIR_1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 91: Model 'RAM' input port 'DIR_0' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 92: Model 'RAM' input port 'CS2_1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 93: Model 'RAM' input port 'CS2_0' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 94: Model 'RAM' input port 'CS1_1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 95: Model 'RAM' input port 'CS1_0' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 96: Model 'RAM' input port 'CONCAT_EN_1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 97: Model 'RAM' input port 'CONCAT_EN_0' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 98: Model 'RAM' input port 'CLK2_1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 99: Model 'RAM' input port 'CLK2_0' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 100: Model 'RAM' input port 'CLK2EN_1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 101: Model 'RAM' input port 'CLK2EN_0' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 102: Model 'RAM' input port 'CLK1_1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 103: Model 'RAM' input port 'CLK1_0' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 104: Model 'RAM' input port 'CLK1EN_1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 105: Model 'RAM' input port 'CLK1EN_0' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 106: Model 'RAM' input port 'ASYNC_FLUSH_1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 107: Model 'RAM' input port 'ASYNC_FLUSH_0' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 108: Model 'RAM' input port 'A2_1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 109: Model 'RAM' input port 'A2_0' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 110: Model 'RAM' input port 'A1_1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 111: Model 'RAM' input port 'A1_0' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 112: Model 'RAM' output port 'RD_1' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 113: Model 'RAM' output port 'RD_0' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 114: Model 'RAM' output port 'PUSH_FLAG_1' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 115: Model 'RAM' output port 'PUSH_FLAG_0' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 116: Model 'RAM' output port 'POP_FLAG_1' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 117: Model 'RAM' output port 'POP_FLAG_0' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 118: Model 'RAM' output port 'Almost_Full_1' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 119: Model 'RAM' output port 'Almost_Full_0' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 120: Model 'RAM' output port 'Almost_Empty_1' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
WarninError 1: /home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build/quicklogic/devices/ql-eos-s3-virt/arch.timing.xml:2427 <pb_type> timing-annotation/<model> mismatch on port 'TBS' of model 'T_FRAG', timing annotation specifies combinational connection to port 'XZ' but the connection does not exist in the model
g 121: Model 'RAM' output port 'Almost_Empty_0' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 122: Model 'MULT' input port 'sel_mul_32x32' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 123: Model 'MULT' input port 'Valid_mult' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 124: Model 'MULT' input port 'Bmult' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 125: Model 'MULT' input port 'Amult' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 126: Model 'MULT' output port 'Cmult' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 127: Model 'BIDIR_CELL' input port 'O_EN' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 128: Model 'BIDIR_CELL' input port 'O_DAT' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 129: Model 'BIDIR_CELL' input port 'I_PAD_$inp' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 130: Model 'BIDIR_CELL' input port 'I_EN' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 131: Model 'BIDIR_CELL' output port 'O_PAD_$out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 132: Model 'BIDIR_CELL' output port 'I_DAT' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 133: Model 'SDIOMUX_CELL' input port 'O_EN' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 134: Model 'SDIOMUX_CELL' input port 'O_DAT' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 135: Model 'SDIOMUX_CELL' input port 'I_PAD_$inp' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 136: Model 'SDIOMUX_CELL' input port 'I_EN' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 137: Model 'SDIOMUX_CELL' output port 'O_PAD_$out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 138: Model 'SDIOMUX_CELL' output port 'I_DAT' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
# Loading Architecture Description took 0.02 seconds (max_rss 17.2 MiB, delta_rss +4.0 MiB)
The entire flow of VPR took 0.02 seconds (max_rss 17.2 MiB)
+ rm vpr.output.sg9
+ exit 1
make[2]: *** [quicklogic/devices/CMakeFiles/file_quicklogic_devices_rr_graph_ql-eos-s3_wlcsp.rr_graph.virt.xml.dir/build.make:64: quicklogic/devices/rr_graph_ql-eos-s3_wlcsp.rr_graph.virt.xml] Error 1
make[2]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make[1]: *** [CMakeFiles/Makefile2:7174: quicklogic/devices/CMakeFiles/file_quicklogic_devices_rr_graph_ql-eos-s3_wlcsp.rr_graph.virt.xml.dir/all] Error 2
make[1]: Leaving directory '/home/tnt/projects/fpga/toolchain/symbiflow-arch-defs/build'
make: *** [Makefile:141: all] Error 2
